From: Jim Grosbach Date: Wed, 24 Aug 2011 21:42:27 +0000 (+0000) Subject: Thumb parsing and encoding for SUB (SP minu immediate). X-Git-Tag: android-x86-6.0-r1~928^2~1909 X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=f69c80403620ef38674e037ae2664f1bbe5a4f3c;p=android-x86%2Fexternal-llvm.git Thumb parsing and encoding for SUB (SP minu immediate). Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that form is Thumb2 only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index a5ddec3d23e..837d853f378 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -335,10 +335,6 @@ def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), let DecoderMethod = "DecodeThumbAddSPImm"; } -// Can optionally specify SP as a three operand instruction. -def : tInstAlias<"add${p} sp, sp, $imm", - (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; - // SUB sp, sp, # // FIXME: The encoding and the ASM string don't match up. def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), @@ -350,6 +346,12 @@ def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), let DecoderMethod = "DecodeThumbAddSPImm"; } +// Can optionally specify SP as a three operand instruction. +def : tInstAlias<"add${p} sp, sp, $imm", + (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; +def : tInstAlias<"sub${p} sp, sp, $imm", + (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; + // ADD , sp def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr, "add", "\t$Rdn, $sp, $Rn", []>, diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 965b39412c8..50fa8eaa2df 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -2923,9 +2923,13 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, static_cast(Operands[4])->getReg() == ARM::SP && static_cast(Operands[1])->getReg() == 0) return true; - // Register-register 'add' for thumb does not have a cc_out operand - // when it's an ADD SP, #imm. - if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && + // Register-register 'add/sub' for thumb does not have a cc_out operand + // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also + // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't + // right, this will result in better diagnostics (which operand is off) + // anyway. + if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && + (Operands.size() == 5 || Operands.size() == 6) && static_cast(Operands[3])->isReg() && static_cast(Operands[3])->getReg() == ARM::SP && static_cast(Operands[1])->getReg() == 0) diff --git a/test/MC/ARM/basic-thumb-instructions.s b/test/MC/ARM/basic-thumb-instructions.s index ba02ec2902d..91f8e15c1f4 100644 --- a/test/MC/ARM/basic-thumb-instructions.s +++ b/test/MC/ARM/basic-thumb-instructions.s @@ -538,11 +538,13 @@ _func: @------------------------------------------------------------------------------ -@ FIXME: SUB (SP minus immediate) -@------------------------------------------------------------------------------ -@------------------------------------------------------------------------------ -@ FIXME: SUB (SP minus register) +@ SUB (SP minus immediate) @------------------------------------------------------------------------------ + sub sp, #12 + sub sp, sp, #508 + +@ CHECK: sub sp, #12 @ encoding: [0x83,0xb0] +@ CHECK: sub sp, #508 @ encoding: [0xff,0xb0] @------------------------------------------------------------------------------