From: Quentin Colombet <qcolombet@apple.com>
Date: Mon, 18 Aug 2014 17:55:32 +0000 (+0000)
Subject: [X86][Haswell][SchedModel] Add architecture specific scheduling models.
X-Git-Tag: android-x86-7.1-r4~58403
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=f8da7e552cdc7d369397db12dbb3169332d658f5;p=android-x86%2Fexternal-llvm.git

[X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Floating Point x87 instructions.
Sub-group: Math instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215913 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td
index ec408d13d17..4dda178d0b0 100644
--- a/lib/Target/X86/X86SchedHaswell.td
+++ b/lib/Target/X86/X86SchedHaswell.td
@@ -1175,4 +1175,20 @@ def WriteFRNDINT : SchedWriteRes<[]> {
 }
 def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>;
 
+//-- Math instructions --//
+
+// FSCALE.
+def WriteFSCALE : SchedWriteRes<[]> {
+  let Latency = 75; // 49-125
+  let NumMicroOps = 50; // 25-75
+}
+def : InstRW<[WriteFSCALE], (instregex "FSCALE")>;
+
+// FXTRACT.
+def WriteFXTRACT : SchedWriteRes<[]> {
+  let Latency = 15;
+  let NumMicroOps = 17;
+}
+def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>;
+
 } // SchedModel