From: Andrew Lenharth <andrewl@lenharth.org>
Date: Wed, 26 Jan 2005 02:53:56 +0000 (+0000)
Subject: hum, writing on one machine, testing on another...
X-Git-Tag: android-x86-6.0-r1~1003^2~50004
X-Git-Url: http://git.osdn.net/view?a=commitdiff_plain;h=fc16691925f550fcb17c8f03858ea11c488bdf12;p=android-x86%2Fexternal-llvm.git

hum, writing on one machine, testing on another...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19844 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 5fa16d0e694..c5220bc9017 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -665,10 +665,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
     // the ops are expanded into special library calls with
     // special calling conventions
     switch(N.getOpcode()) {
-    case UREM: Opc = Alpha::REMQU; break;
-    case SREM: Opc = Alpha::REMQ; break;
-    case UDIV: Opc = Alpha::DIVQU; break;
-    case SDIV: Opc = Alpha::DIVQ; break;
+    case ISD::UREM: Opc = Alpha::REMQU; break;
+    case ISD::SREM: Opc = Alpha::REMQ; break;
+    case ISD::UDIV: Opc = Alpha::DIVQU; break;
+    case ISD::SDIV: Opc = Alpha::DIVQ; break;
+    };
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));
     BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);