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plugins: update lockstep to use g_memdup2
[qmiga/qemu.git] / target / riscv /
2023-06-30 Richard HendersonMerge tag 'pull-request-2023-06-29' of https://gitlab...
2023-06-29 Richard HendersonMerge tag 'for-upstream' of https://gitlab.com/bonzini...
2023-06-29 Richard HendersonMerge tag 'accel-20230628' of https://github.com/philmd...
2023-06-28 Richard HendersonMerge tag 'for-upstream' of https://repo.or.cz/qemu...
2023-06-28 Richard HendersonMerge tag 'for_upstream' of https://git./virt/kvm/mst...
2023-06-28 Philippe Mathieu... target/riscv: Restrict KVM-specific fields from ArchCPU
2023-06-26 Richard HendersonMerge tag 'pull-tcg-20230626' of https://gitlab.com...
2023-06-26 Anton Johanssontarget: Widen pc/cs_base in cpu_get_tb_cpu_state
2023-06-21 Richard HendersonMerge tag 'seabios-hppa-v7-pull-request' of https:...
2023-06-20 Richard HendersonMerge tag 'pull-tcg-20230620' of https://gitlab.com...
2023-06-20 Philippe Mathieu... meson: Replace softmmu_ss -> system_ss
2023-06-14 Richard HendersonMerge tag 'pull-riscv-to-apply-20230614' of https:...
2023-06-13 Himanshu Chauhantarget/riscv: Smepmp: Return error when access permissi...
2023-06-13 Xiao Wangtarget/riscv/vector_helper.c: Remove the check for...
2023-06-13 Xiao Wangtarget/riscv/vector_helper.c: clean up reference of...
2023-06-13 Weiwei Litarget/riscv: Fix initialized value for cur_pmmask
2023-06-13 Weiwei Litarget/riscv: Remove pc_succ_insn from DisasContext
2023-06-13 Weiwei Litarget/riscv: Enable PC-relative translation
2023-06-13 Weiwei Litarget/riscv: Use true diff for gen_pc_plus_diff
2023-06-13 Weiwei Litarget/riscv: Change gen_set_pc_imm to gen_update_pc
2023-06-13 Weiwei Litarget/riscv: Change gen_goto_tb to work on displacements
2023-06-13 Weiwei Litarget/riscv: Introduce cur_insn_len into DisasContext
2023-06-13 Weiwei Litarget/riscv: Fix target address to update badaddr
2023-06-13 Weiwei Litarget/riscv: Pass RISCVCPUConfig as target_info to...
2023-06-13 Weiwei Litarget/riscv: Split RISCVCPUConfig declarations from...
2023-06-13 Mayuresh Chitaletarget/riscv: smstateen knobs
2023-06-13 Mayuresh Chitaletarget/riscv: Reuse tb->flags.FS
2023-06-13 Mayuresh Chitaletarget/riscv: smstateen check for fcsr
2023-06-13 Weiwei Litarget/riscv: Update cur_pmmask/base when xl changes
2023-06-13 Weiwei Litarget/riscv: Fix pointer mask transformation for vecto...
2023-06-13 Weiwei Litarget/riscv: Deny access if access is partially inside...
2023-06-13 Weiwei Litarget/riscv: Separate pmp_update_rule() in pmpcfg_csr_...
2023-06-13 Weiwei Litarget/riscv: Flush TLB only when pmpcfg/pmpaddr really...
2023-06-13 Weiwei Litarget/riscv: Flush TLB when pmpaddr is updated
2023-06-13 Weiwei Litarget/riscv: Update the next rule addr in pmpaddr_csr_...
2023-06-13 Weiwei Litarget/riscv: Flush TLB when MMWP or MML bits are changed
2023-06-13 Weiwei Litarget/riscv: Remove unused paramters in pmp_hart_has_p...
2023-06-13 Weiwei Litarget/riscv: Make RLB/MML/MMWP bits writable only...
2023-06-13 Weiwei Litarget/riscv: Change the return type of pmp_hart_has_pr...
2023-06-13 Weiwei Litarget/riscv: Make the short cut really work in pmp_har...
2023-06-13 Weiwei Litarget/riscv: Move pmp_get_tlb_size apart from get_phys...
2023-06-13 Weiwei Litarget/riscv: Update pmp_get_tlb_size()
2023-06-13 Daniel Henrique... target/riscv: rework write_misa()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: validate extensions before riscv_ti...
2023-06-13 Daniel Henrique... target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: add priv_spec validate/disable_exts...
2023-06-13 Weiwei Litarget/riscv: Update check for Zca/Zcf/Zcd
2023-06-13 Weiwei Litarget/riscv: Mask the implicitly enabled extensions...
2023-06-13 Daniel Henrique... target/riscv: add PRIV_VERSION_LATEST
2023-06-13 Daniel Henrique... target/riscv/cpu.c: remove set_priv_version()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: remove set_vext_version()
2023-06-13 Daniel Henrique... target/riscv/cpu.c: add riscv_cpu_validate_v()
2023-06-13 Weiwei Litarget/riscv: Move zc* out of the experimental properties
2023-06-13 Daniel Henrique... target/riscv/vector_helper.c: skip set tail when vta...
2023-06-06 Richard HendersonMerge tag 'pull-request-2023-06-06' of https://gitlab...
2023-06-05 Richard HendersonMerge tag 'pull-tcg-20230605' of https://gitlab.com...
2023-06-05 Richard Hendersonaccel/tcg: Introduce translator_io_start
2023-06-05 Richard Hendersontcg: Pass TCGHelperInfo to tcg_gen_callN
2023-06-05 Richard Hendersontcg: Split out tcg/oversized-guest.h
2023-05-17 Richard HendersonMerge tag 'linux-user-for-8.1-pull-request' of https...
2023-05-13 Richard HendersonMerge tag 'or1k-pull-request-20230513' of https://githu...
2023-05-05 Richard HendersonMerge tag 'pw-pull-request' of https://gitlab.com/marca...
2023-05-05 Richard HendersonMerge tag 'migration-20230505-pull-request' of https...
2023-05-05 Richard HendersonMerge tag 'pull-riscv-to-apply-20230505-1' of https...
2023-05-05 Rahul Pathaktarget/riscv: add Ventana's Veyron V1 CPU
2023-05-05 Alexandre Ghitiriscv: Make sure an exception is raised if a pte is...
2023-05-05 Irina Ryapolovatarget/riscv: Fix Guest Physical Address Translation
2023-05-05 Bin Mengtarget/riscv: Restore the predicate() NULL check behavior
2023-05-05 Daniel Henrique... target/riscv: add TYPE_RISCV_DYNAMIC_CPU
2023-05-05 Daniel Henrique... target/riscv: add query-cpy-definitions support
2023-05-05 Daniel Henrique... target/riscv: add CPU QOM header
2023-05-05 Richard Hendersontarget/riscv: Reorg sum check in get_physical_address
2023-05-05 Richard Hendersontarget/riscv: Reorg access check in get_physical_address
2023-05-05 Richard Hendersontarget/riscv: Merge checks for reserved pte flags
2023-05-05 Richard Hendersontarget/riscv: Don't modify SUM with is_debug
2023-05-05 Richard Hendersontarget/riscv: Suppress pte update with is_debug
2023-05-05 Richard Hendersontarget/riscv: Move leaf pte processing out of level...
2023-05-05 Richard Hendersontarget/riscv: Hoist pbmte and hade out of the level...
2023-05-05 Richard Hendersontarget/riscv: Hoist second stage mode change to callers
2023-05-05 Richard Hendersontarget/riscv: Check SUM in the correct register
2023-05-05 Richard Hendersontarget/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index
2023-05-05 Richard Hendersontarget/riscv: Move hstatus.spvp check to check_access_hlsv
2023-05-05 Richard Hendersontarget/riscv: Introduce mmuidx_2stage
2023-05-05 Richard Hendersontarget/riscv: Introduce mmuidx_priv
2023-05-05 Richard Hendersontarget/riscv: Introduce mmuidx_sum
2023-05-05 Richard Hendersontarget/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT
2023-05-05 Richard Hendersontarget/riscv: Handle HLV, HSV via helpers
2023-05-05 Richard Hendersontarget/riscv: Use cpu_ld*_code_mmu for HLVX
2023-05-05 Fei Wutarget/riscv: Reduce overhead of MSTATUS_SUM change
2023-05-05 Fei Wutarget/riscv: Separate priv from mmu_idx
2023-05-05 LIU Zhiweitarget/riscv: Add a tb flags field for vstart
2023-05-05 Richard Hendersontarget/riscv: Remove mstatus_hs_{fs, vs} from tb_flags
2023-05-05 LIU Zhiweitarget/riscv: Encode the FS and VS on a normal way...
2023-05-05 LIU Zhiweitarget/riscv: Add a general status enum for extensions
2023-05-05 LIU Zhiweitarget/riscv: Extract virt enabled state from tb flags
2023-05-05 Yi Chentarget/riscv: fix H extension TVM trap
2023-05-05 Weiwei Litarget/riscv: Use check for relationship between Zdinx...
2023-05-05 Weiwei Litarget/riscv: Legalize MPP value in write_mstatus
2023-05-05 Weiwei Litarget/riscv: Use PRV_RESERVED instead of PRV_H
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