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Marek Olšák [Fri, 30 Sep 2016 23:53:05 +0000 (01:53 +0200)]
amd: add texture format definitions for GFX9
the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums
differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show
enums for both.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 30 Aug 2016 21:42:29 +0000 (23:42 +0200)]
amd: resolve remaining definition conflicts with gfx9d.h
Add _GFX6 and _GFX9 suffixes to conflicting definitions.
sid.h and gfx9d.h can now be included in the same file.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 30 Aug 2016 21:37:13 +0000 (23:37 +0200)]
amd: normalize register definition formatting
This resolves trivial conflicts with gfx9d.h caused by different formatting.
Some fields are also renamed.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 30 Aug 2016 20:32:34 +0000 (22:32 +0200)]
amd: import GFX9 register definitions
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 15 Oct 2016 13:16:05 +0000 (15:16 +0200)]
radeonsi: code shuffling in si_init_depth_surface
use fewer local variables, re-order the assignments, so that the GFX9 diff
is smaller here.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 14 Mar 2017 21:32:25 +0000 (22:32 +0100)]
amd/addrlib: silence warnings
Nicolai Hähnle [Thu, 6 Oct 2016 16:55:25 +0000 (18:55 +0200)]
amd/addrlib: import gfx9 support
Kevin Furrow [Wed, 5 Oct 2016 13:07:01 +0000 (09:07 -0400)]
amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to differentiate between 64 and 128bpp formats.
Kevin Furrow [Sat, 1 Oct 2016 17:39:20 +0000 (13:39 -0400)]
amd/addrlib: Fix selection of swizzle modes for 3D compressed images.
Kevin Furrow [Fri, 16 Sep 2016 12:48:54 +0000 (08:48 -0400)]
amd/addrlib: Add support for ETC2 and ASTC formats.
Joe Ma [Fri, 2 Sep 2016 06:13:40 +0000 (02:13 -0400)]
amd/addrlib: Bump version to 6.02
Frans Gu [Thu, 7 Jul 2016 11:08:16 +0000 (07:08 -0400)]
amd/addrlib: Adjust slie size after pitch and actual height adjustment
Frans Gu [Fri, 1 Jul 2016 08:54:44 +0000 (04:54 -0400)]
amd/addrlib: Apply input pitch after internal pitch aligning
Nicolai Hähnle [Wed, 20 Jul 2016 08:56:35 +0000 (10:56 +0200)]
amdgpu/addrlib: Bump version to 6.01
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 08:33:44 +0000 (10:33 +0200)]
amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags
1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
Nicolai Hähnle [Wed, 20 Jul 2016 08:51:50 +0000 (10:51 +0200)]
amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calculated correctly
Nicolai Hähnle [Wed, 20 Jul 2016 08:34:41 +0000 (10:34 +0200)]
amdgpu/addrlib: Add a new output flag to notify client that the returned tile index is for PRT on SI
If this flag is set for mip0, client should set prt flag for sub mips,
so that address lib can select the correct tile index for sub mips.
Xavi Zhang [Tue, 1 Mar 2016 08:40:15 +0000 (03:40 -0500)]
amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixes
The usage should be client first call AddrComputeSurfaceInfo() on
depth surface with flag "matchStencilTilecfg", AddrLib will use
2DThin1 tile index for depth as much as possible and do not down grade
unless alignment requirement cannot be met.
1. If there is a matched 2DThin1 tile index for stencil which make
sure they will share same tile config parameters, then return the
stencil 2DThin1 tile index as well.
2. If using 2DThin1 tile mode cannot make sure such thing happen, and
TcCompatible flag was set, then ignore this flag then try 2DThin1 tile
mode for depth and stencil again.
3. If 2DThin1 tile mode cannot make sure depth and stencil to have
same tile config parameters, then down grade depth surface tile mode
to 1DThin1.
4. If depth surface's tile mode was 1DThin1, then return 1DThin1 tile
index for stencil.
5. If depth surface's tile mode is PRT, then return invalid tile index
to stencil since their tile config parameters will never be met.
Client driver then check the returned tile index of stencil -- if it
is not invalid tile index, then call AddrComputeSurfaceInfo() on
stencil surface with the returned stencil tile index to get full
output information. Please note, client needs to set flag
"useTileIndex" when AddrLib get created.
Frans Gu [Fri, 4 Mar 2016 10:04:23 +0000 (05:04 -0500)]
amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect ratio settings
By this way, we can have valid equation for 2D_THIN1 tile mode.
Add flag "preferEquation" to return equation index without adjusting
input tile mode.
Frans Gu [Thu, 10 Mar 2016 07:24:00 +0000 (02:24 -0500)]
amdgpu/addrlib: do some tile mode conversions to display surface
Xavi Zhang [Mon, 29 Feb 2016 06:36:08 +0000 (01:36 -0500)]
amdgpu/addrlib: Check prt flag for PRT_THIN1 extra padding for DCC.
Frans Gu [Tue, 18 Aug 2015 03:56:23 +0000 (23:56 -0400)]
amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign
1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.
Also, related changes to tile mode optimization for needEquation.
Xavi Zhang [Fri, 26 Feb 2016 07:49:28 +0000 (02:49 -0500)]
amdgpu/addrlib: Always returns pixelPitch in original pixels
Sabre Shao [Thu, 25 Feb 2016 10:30:33 +0000 (05:30 -0500)]
amdgpu/addrlib: fix crash on allocation failure
Frans Gu [Tue, 23 Feb 2016 03:05:19 +0000 (22:05 -0500)]
amdgpu/addrlib: Add flag to report if a surface can have dcc ram
Roy Zhan [Sun, 10 Jan 2016 12:56:11 +0000 (07:56 -0500)]
amdgpu/addrlib: support non-power2 height alignment (for linear surface)
Frans Gu [Thu, 22 Oct 2015 06:11:51 +0000 (02:11 -0400)]
amdgpu/addrlib: Fix family setting for VI and CZ ASICs
Nicolai Hähnle [Wed, 20 Jul 2016 19:31:24 +0000 (21:31 +0200)]
amdgpu/addrlib: style cleanup
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 19:30:56 +0000 (21:30 +0200)]
amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji
The change also modifies function CiLib::HwlPadDimensions to report
adjusted pitch alignment.
Xavi Zhang [Fri, 21 Aug 2015 10:25:12 +0000 (06:25 -0400)]
amdgpu/addrlib: Fix number of //
Find ^/{80,99}$ and replace them to 100 "/"
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 19:13:41 +0000 (21:13 +0200)]
amdgpu/addrlib: Cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Xavi Zhang [Thu, 20 Aug 2015 07:59:01 +0000 (03:59 -0400)]
amdgpu/addrlib: Use namespaces
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Kevin Zhao [Tue, 18 Aug 2015 04:17:31 +0000 (00:17 -0400)]
amdgpu/addrlib: Adjust 99 "*" to 100 "*" alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Frans Gu [Fri, 14 Aug 2015 10:03:24 +0000 (06:03 -0400)]
amdgpu/addrlib: Add a new tile mode ADDR_TM_UNKNOWN
This can be used by address lib client to ask address lib to select
tile mode.
Xavi Zhang [Sun, 28 Jun 2015 05:02:59 +0000 (01:02 -0400)]
amdgpu/addrlib: Stylish cleanup.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Roy Zhan [Tue, 9 Jun 2015 08:46:59 +0000 (04:46 -0400)]
amdgpu/addrlib: Disable tcComaptible when depth surface is not macro tiled
Experiment show 1D tiling + TcCompatible cannot work together.
Xavi Zhang [Tue, 12 May 2015 08:26:59 +0000 (04:26 -0400)]
amdgpu/addrlib: fix pixel index calculation of thick micro tiling
Xavi Zhang [Fri, 17 Apr 2015 07:22:34 +0000 (03:22 -0400)]
amdgpu/addrlib: Add a flag to skip calculate indices
This is useful for debugging and special cases for stencil surfaces
do not require texture fetch compatible.
Nicolai Hähnle [Wed, 20 Jul 2016 18:25:15 +0000 (20:25 +0200)]
amdgpu/addrlib: add equation generation
1. Add new surface flags needEquation for client driver use to force
the surface tile setting equation compatible. Override 2D/3D macro
tile mode to PRT_* tile mode if this flag is TRUE and num slice > 1.
2. Add numEquations and pEquationTable in ADDR_CREATE_OUTPUT structure
to return number of equations and the equation table to client driver
3. Add equationIndex in ADDR_COMPUTE_SURFACE_INFO_OUTPUT structure to
return the equation index to client driver
Please note the use of address equation has following restrictions:
1) The surface can't be splitable
2) The surface can't have non zero tile swizzle value
3) Surface with > 1 slices must have PRT tile mode, which disable
slice rotation
Nicolai Hähnle [Wed, 20 Jul 2016 18:24:59 +0000 (20:24 +0200)]
amdgpu/addrlib: rename ComputeSurfaceThickness to Thickness
Xavi Zhang [Thu, 7 May 2015 06:26:29 +0000 (02:26 -0400)]
amdgpu/addrlib: add define HAVE_TSERVER
Frans Gu [Fri, 10 Apr 2015 08:20:06 +0000 (04:20 -0400)]
amdgpu/addrlib: Add new interface to support macro mode index query
Roy Zhan [Thu, 9 Apr 2015 03:03:34 +0000 (23:03 -0400)]
amdgpu/addrlib: add explicit Log2NonPow2 function
Nicolai Hähnle [Wed, 27 Jul 2016 17:14:41 +0000 (19:14 +0200)]
amdgpu/addrlib: Fix invalid access to m_tileTable
Sometimes client driver passes valid tile info into address library,
in this case, the tile index is computed in function
HwlPostCheckTileIndex instead of CiAddrLib::HwlSetupTileCfg.
We need to call HwlPostCheckTileIndex to calculate the correct tile
index to get tile split bytes for this case.
Nicolai Hähnle [Wed, 27 Jul 2016 17:13:57 +0000 (19:13 +0200)]
amdgpu/addrlib: add ADDR_ANALYSIS_ASSUME
It helps fix analysis warnings in MSC.
XiaoYuan Zheng [Thu, 22 Jan 2015 10:08:05 +0000 (05:08 -0500)]
amdgpu/addrlib: add tcCompatible htile addr from coordinate support.
Carlos Xiong [Mon, 15 Dec 2014 03:50:15 +0000 (22:50 -0500)]
amdgpu/addrlib: force all zero tile info for linear general.
Nicolai Hähnle [Wed, 20 Jul 2016 17:22:18 +0000 (19:22 +0200)]
amdgpu/addrlib: Add a member "bpp" for input of method AddrConvertTileIndex and AddrConvertTileInfoToHW
When clients queries tile Info from tile index and expects accurate
tileSplit info, bits per pixel info is required to be provided since
this is necessary for computing tileSplitBytes; otherwise Addrlib will
return value of "tileBytes" instead if bpp is 0 - which is also
current logic. If clients don't need tileSplit info, it's OK to pass
bpp with value 0.
Frans Gu [Wed, 3 Dec 2014 10:47:09 +0000 (05:47 -0500)]
amdgpu/addrlib: Refine the PRT tile mode selection
Switch the tile index based on logic instead of hardcoded threshold
for different ASIC.
Xavi Zhang [Tue, 25 Nov 2014 03:49:50 +0000 (22:49 -0500)]
amdgpu/addrlib: add dccRamSizeAligned output flag
This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.
Nicolai Hähnle [Wed, 20 Jul 2016 08:51:35 +0000 (10:51 +0200)]
amdgpu/addrlib: Change comment alignment
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 10:30:54 +0000 (12:30 +0200)]
amdgpu/addrlib: style changes and minor cleanups
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 10:57:14 +0000 (12:57 +0200)]
amdgpu/addrlib: AddrLib inheritance refactor
Add one more abstraction layer into inheritance system.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Wed, 20 Jul 2016 10:21:13 +0000 (12:21 +0200)]
amdgpu/addrlib: rearrange code in preparation of refactoring
No code changes.
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Xavi Zhang [Tue, 22 Jul 2014 08:53:24 +0000 (04:53 -0400)]
amdgpu/addrlib: add disableLinearOpt flag
Xavi Zhang [Wed, 20 Aug 2014 08:46:51 +0000 (04:46 -0400)]
amdgpu/addrlib: Add GetMaxAlignments
Xavi Zhang [Fri, 1 Aug 2014 06:18:00 +0000 (02:18 -0400)]
amdgpu/addrlib: Let Kaveri go general stereo right eye offset padding path
Kaveri (2-pipe) macro tiling mode table was initially set to all
4-aspect-ratio so the swizzling path did not work for it and then we
chose to pad the offset. We now discover the root cause is that if
ratio > 2, the swizzling path does not work. So we can safely use the
same path for Kaveri.
Xavi Zhang [Wed, 9 Jul 2014 06:46:00 +0000 (02:46 -0400)]
amdgpu/addrlib: Rewrite tile mode optmization code
Note: remove reference to degrade4Space and use opt4Space instead.
Carlos Xiong [Wed, 2 Jul 2014 05:46:06 +0000 (01:46 -0400)]
amdgpu/addrlib: Add a flag "tcCompatible" to surface info output structure.
Even if surface info input flag "tcComaptible" is enabled, tc
compatible may be not supported if tile split happens for depth
surfaces. Add a new flag in output structure to notify client to
disable tc compatible in this case.
Xavi Zhang [Mon, 30 Jun 2014 03:48:44 +0000 (23:48 -0400)]
amdgpu/addrlib: Make comments shorter
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
XiaoYuan Zheng [Thu, 26 Jun 2014 07:47:51 +0000 (03:47 -0400)]
amdgpu/addrlib: add new flag nonSplit
Flag tcCompatible has different usage in CI and VI. Add a new flag
"nonSplit" for CI.
Xiao-Tao Zai [Wed, 25 Jun 2014 15:06:00 +0000 (11:06 -0400)]
amdgpu/addrlib: allow tileSplitBytes greater than row size
Carrizo row size is 1K, while tileSplitBytes is 2K for a 4xAA 32bpp
depth surface. Remove the sanity check that tileSplitBytes must be
greater than row size. There could be performance loss but may be
covered by non-split depth which enables tc-compatible read.
Carlos Xiong [Tue, 10 Jun 2014 07:43:44 +0000 (03:43 -0400)]
amdgpu/addrlib: Change to compute TC compatible stencil info
Change the logic to compute tc compatible stencil info via depth's
tileIndex instead of using depth's tileInfo. So the clients can get
the stencil's tileInfo computed from macroModeTable. If the stencil
tileInfo is same as depth tileInfo, then stencil is tc compatible;
otherwise, stencil is not tc compatible. The current suggestion is to
create another stencil buffer with the tc compatible tileInfo, use
depth-to-color copy to decompress and tile convert the rendered
stencil to tc compoatible stencil (And use the new stencil buffer to
program TC).
Nicolai Hähnle [Wed, 22 Jun 2016 18:19:47 +0000 (20:19 +0200)]
amdgpu/addrlib: rename SiAddrLib/CiAddrLib to match internal spelling
Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Wed, 29 Mar 2017 18:23:07 +0000 (20:23 +0200)]
configure.ac: require libdrm_amdgpu 2.4.76 for Vega
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Samuel Pitoiset [Wed, 29 Mar 2017 22:28:24 +0000 (00:28 +0200)]
st/glsl_to_tgsi: use glsl_type::sampler_index()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Samuel Pitoiset [Wed, 29 Mar 2017 22:33:15 +0000 (00:33 +0200)]
glsl: allow glsl_type::sampler_index() with images
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Nicolai Hähnle [Thu, 30 Mar 2017 09:22:23 +0000 (11:22 +0200)]
st/mesa: improve error messages and fix security warning
Debian, Ubuntu set default build flag: -Werror=format-security
CC state_tracker/st_cb_texturebarrier.lo
state_tracker/st_cb_eglimage.c: In function ‘st_egl_image_get_surface’:
state_tracker/st_cb_eglimage.c:64:7: error: format not a string literal and no format arguments [-Werror=format-security]
_mesa_error(ctx, GL_INVALID_VALUE, error);
^~~~~~~~~~~
state_tracker/st_cb_eglimage.c:71:7: error: format not a string literal and no format arguments [-Werror=format-security]
_mesa_error(ctx, GL_INVALID_OPERATION, error);
^~~~~~~~~~~
Reported-by: Krzysztof Kolasa <kkolasa@winsoft.pl>
Fixes:
83e9de25f325 ("st/mesa: EGLImageTarget* error handling")
Kenneth Graunke [Tue, 28 Mar 2017 21:45:59 +0000 (14:45 -0700)]
i965: Combine intel_batchbuffer_reloc and intel_batchbuffer_reloc64
These two functions do the exact same thing. One returns a uint64_t,
and the other takes the same uint64_t and truncates it to a uint32_t.
We only need the uint64_t variant - the caller can truncate if it wants.
This patch gives us one function, intel_batchbuffer_reloc, that does
the 64-bit thing.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Kenneth Graunke [Wed, 29 Mar 2017 03:31:45 +0000 (20:31 -0700)]
i965: Use WARN_ONCE instead of open coding it.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Harish Krupo [Tue, 28 Mar 2017 18:38:12 +0000 (04:08 +0930)]
android: pass sse4.1 flag as appropriate
We have functions which depend on sse4.1 support but we didnt pass
the right compile flag for it. This patch fixes it.
Signed-off-by: Kalyan Kondapally <kalyan.kondapally@intel.com>
Signed-off-by: Harish Krupo <harish.krupo.kps@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Dave Airlie [Thu, 30 Mar 2017 03:09:03 +0000 (13:09 +1000)]
radv: fix mask attribs properly.
some days it just doesn't pay to get out of bed.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 30 Mar 2017 02:06:52 +0000 (12:06 +1000)]
radv: fix regression with mask attrib setting code.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 29 Mar 2017 05:12:31 +0000 (15:12 +1000)]
radv: move to using nir clip/cull merge pass.
Doing this before tessellation makes doing some bits of
tessellation a bit cleaner. It also cleans up a bit of the
llvm generator code.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
George Kyriazis [Tue, 28 Mar 2017 18:27:27 +0000 (12:27 -0600)]
swr: [scons] Fix windows build
Fix codegen build break that was introduced earlier
v2: update rules for gen_knobs.cpp and gen_knobs.h
v3: Introduce bldroot and revert generator file changes, making patch simpler.
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
Craig Stout [Wed, 29 Mar 2017 19:14:30 +0000 (12:14 -0700)]
anv/cmd_buffer: fix host memory leak
push_constants must be free'd.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100452
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
Timothy Arceri [Wed, 29 Mar 2017 05:30:59 +0000 (16:30 +1100)]
mesa/glthread: fallback to sync if count validation fails
The old code would sync and then throw a cryptic error message.
There is no need for a custom error, we can just fallback to
the real function and have it do proper validation.
Fixes piglit test:
glsl-uniform-out-of-bounds
Which was returning the wrong error code.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 29 Mar 2017 05:30:58 +0000 (16:30 +1100)]
mesa/glthread: add async support to glProgramUniform*() functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Wed, 29 Mar 2017 02:20:36 +0000 (13:20 +1100)]
mesa/glthread: print out syncs when MARSHAL_MAX_CMD_SIZE is exceeded
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jason Ekstrand [Wed, 29 Mar 2017 00:33:06 +0000 (17:33 -0700)]
anv/batch_chain: Handle another OOM in cmd_buffer_execbuf
Found by inspection while rebasing other patches.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Philipp Zabel [Wed, 29 Mar 2017 07:44:21 +0000 (09:44 +0200)]
st/mesa: EGLImageTarget* error handling
Stop trying to specify texture or renderbuffer objects for unsupported
EGL images. Generate the error codes specified in the OES_EGL_image
extension.
EGLImageTargetTexture2D and EGLImageTargetRenderbuffer would call
the pipe driver's create_surface callback without ever checking that
the given EGL image is actually compatible with the chosen target
texture or renderbuffer. This patch adds a call to the pipe driver's
is_format_supported callback and generates an INVALID_OPERATION error
for unsupported EGL images. If the EGL image handle does not describe
a valid EGL image, an INVALID_VALUE error is generated.
v2: fixed get_surface to actually use the usage and error parameters
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Philipp Zabel [Wed, 29 Mar 2017 07:44:20 +0000 (09:44 +0200)]
st/mesa: move st_manager_get_egl_image_surface into st_cb_eglimage.c
The only callers are here, and we will add generation of GL errors in
the following patch. Rename the function to st_egl_image_get_surface,
pass the gl_context instead of st_context, and move the cast from
GLeglImageOES to void* into st_egl_image_get_surface.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Alejandro Piñeiro [Tue, 28 Mar 2017 17:24:12 +0000 (19:24 +0200)]
i965: expose BRW_OPCODE_[F32TO16/F16TO32] name on gen8+
Technically those hw operations are only available on gen7, as gen8+
support the conversion on the MOV. But, when using the builder to
implement nir operations (example: nir_op_fquantize2f16), it is not
needed to do the gen check. This check is done later, on the final
emission at brw_F32TO16 (brw_eu_emit), choosing between the MOV or the
specific operation accordingly.
So in the middle, during optimization phases those hw operations can
be around for gen8+ too.
Without this patch, several (at least 95) vulkan-cts quantize tests
crashes when using INTEL_DEBUG=optimizer. For example:
dEQP-VK.spirv_assembly.instruction.graphics.opquantize.too_small_vert
v2: simplify the code using GEN_GE (Ilia Mirkin)
v3: tweak brw_instruction_name instead of changing opcode_descs
table, that is used for validation (Matt Turner)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Marek Olšák [Thu, 23 Mar 2017 22:59:56 +0000 (23:59 +0100)]
mesa: remove dd_function_table::BindProgram
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Mar 2017 22:54:52 +0000 (23:54 +0100)]
r200: remove BindProgram
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Mar 2017 22:51:35 +0000 (23:51 +0100)]
i915: remove BindProgram
The same thing is done in i915_update_program called by i915InvalidateState.
Why do it twice.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Mar 2017 21:59:08 +0000 (22:59 +0100)]
mesa: don't use _NEW_TEXTURE mainly in mesa/main
v2: add missing %s
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Mar 2017 21:42:56 +0000 (22:42 +0100)]
mesa: split _NEW_TEXTURE into _NEW_TEXTURE_OBJECT & _NEW_TEXTURE_STATE
No performance testing has been done, because it makes sense to make this
change regardless of that. Also, _NEW_TEXTURE is still used in many places,
but the obvious occurences are replaced here.
It's now possible to split _NEW_TEXTURE_OBJECT further.
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Mar 2017 21:35:03 +0000 (22:35 +0100)]
mesa: inline _mesa_update_texture
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jose Fonseca [Tue, 28 Mar 2017 10:39:26 +0000 (11:39 +0100)]
appveyor: Update dependencies.
- Use explicit versions everywhere.
- Avoid deprecate `--egg` pip option.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Tue, 28 Mar 2017 10:25:04 +0000 (11:25 +0100)]
c11/threads: Include thr/xtimec.h for xtime definition when building with MSVC.
MSVC has been including a xtime definition in thr/xtimec.h ever since
MSVC 2013 (which is the minimum we require for building Mesa), and
including it prevents duplicate definitions when it gets included by
LLVM.
In fact, it looks that MSVC has been including a partial C11 threads
implementation too for some time, which we should consider migrating to
once we eliminate the use of _MTX_INITIALIZER_NP in our tree.
Thanks to the anonymous helper from
https://bugs.freedesktop.org/show_bug.cgi?id=100201#c4 for spotting
this.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100201
CC: "17.0" <mesa-stable@lists.freedesktop.org>
Timothy Arceri [Wed, 29 Mar 2017 09:30:19 +0000 (20:30 +1100)]
mesa: update lower_jumps tests after bug fix
This change updates the tests to reflect the IR after
the following bug fix.
Fixes:
c1096b7f1d49 ("glsl: fix lower jumps for returns when loop is
inside an if")
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Bugzilla: https://bugs.freedesktop.org/100441
Thomas Hellstrom [Tue, 28 Mar 2017 19:32:22 +0000 (21:32 +0200)]
gbm/dri: Flush after unmap
Drivers may queue dma operations on the context at unmap time so we need
to flush to make sure the data gets to the bo. Ideally the application
would take care of this, but since there appears to be no exported gbm
flush functionality we need to explicitly flush at unmap time.
This fixes a problem where kmscube on vmwgfx in rgba textured mode would
render using an uninitialized texture rather than the intended
rgba pattern.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Bas Nieuwenhuizen [Tue, 31 Jan 2017 22:59:02 +0000 (23:59 +0100)]
radv: Enable sparseBinding feature.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 4 Feb 2017 22:26:50 +0000 (23:26 +0100)]
radv/amdgpu: Use reference counting for bos.
Per the Vulkan spec, memory objects may be deleted before the buffers
and images using them are deleted, although those resources then
cannot be used except for deletion themselves.
For the virtual buffers, we need to access them on resource destruction
to unmap the regions, so this results in a use-after-free. Implement
reference counting to avoid this.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 4 Feb 2017 14:58:39 +0000 (15:58 +0100)]
radv: Implement sparse memory binding.
v2: Only submit when semaphores are specified.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 4 Feb 2017 14:56:20 +0000 (15:56 +0100)]
radv: Implement sparse image creation.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 4 Feb 2017 10:15:59 +0000 (11:15 +0100)]
radv: Implement sparse buffer creation.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 4 Feb 2017 00:18:05 +0000 (01:18 +0100)]
radv/amdgpu: Add winsys implementation of virtual buffers.
v2: - Added comments.
- Fixed a double unmap bug.
- Actually unmap the non-edge old ranges.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Tue, 28 Mar 2017 20:29:16 +0000 (22:29 +0200)]
radv: Assert when setting 0 registers in a sequence.
To catch more of those hangs early.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Acked-by: Dave Airlie <airlied@redhat.com>