OSDN Git Service
Diego Caballero [Mon, 30 Jul 2018 21:33:31 +0000 (21:33 +0000)]
[VPlan] Introduce VPlan-based dominator analysis.
The patch introduces dominator analysis for VPBlockBases and extend
VPlan's GraphTraits specialization with the required interfaces. Dominator
analysis will be necessary to perform some H-CFG transformations and
to introduce VPLoopInfo (LoopInfo analysis on top of the VPlan representation).
Reviewers: fhahn, rengolin, mkuper, hfinkel, mssimpso
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D48815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338310
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexandre Ganea [Mon, 30 Jul 2018 21:14:25 +0000 (21:14 +0000)]
This fixes a crash when a second pass is required for the Codeview Type merging *and* the index points outside of the table (which should lead to an error being printed).
This occurs currently until MS precompiled headers .obj is added (see D45213)
Differential Revision: https://reviews.llvm.org/D50006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338308
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Mon, 30 Jul 2018 21:08:06 +0000 (21:08 +0000)]
[ORC] Add SerializationTraits for std::set and std::map.
Also, make SerializationTraits for pairs forward the actual pair
template type arguments to the underlying serializer. This allows, for example,
std::pair<StringRef, bool> to be passed as an argument to an RPC call expecting
a std::pair<std::string, bool>, since there is an underlying serializer from
StringRef to std::string that can be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338305
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 30 Jul 2018 21:04:38 +0000 (21:04 +0000)]
[TargetLowering] In BuildSDIV, add the MULHS/SMUL_LOHI to the Created vector.
BuildUDIV was already correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338304
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 30 Jul 2018 21:04:34 +0000 (21:04 +0000)]
[DAGCombiner][PowerPC][AArch64] Pass Created vector by reference to BuildSDIVPow2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338303
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Mon, 30 Jul 2018 20:38:53 +0000 (20:38 +0000)]
[InstCombine] Fold Select with binary op
Summary:
Fold
%A = icmp eq i8 %x, 0
%B = xor i8 %x, %z
%C = select i1 %A, i8 %B, i8 %y
To
%C = select i1 %A, i8 %z, i8 %y
Fixes https://bugs.llvm.org/show_bug.cgi?id=38345
Proof: https://rise4fun.com/Alive/43J
Reviewers: lebedev.ri, spatel
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49954
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338300
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 30 Jul 2018 20:27:10 +0000 (20:27 +0000)]
Revert r338222 "[DAGCombiner] Remove unnecessary calls to AddToWorklist."
Thinking about it more it might be possible for the later nodes to be folded in getNode in such a way that the other created nodes are left dead. This can cause use counts to be incorrect on nodes that aren't dead.
So its probably safer to leave this alone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338298
91177308-0d34-0410-b5e6-
96231b3b80d8
Vlad Tsyrklevich [Mon, 30 Jul 2018 20:07:33 +0000 (20:07 +0000)]
Revert "[GVNHoist] Re-enable GVNHoist by default"
This reverts commit r338240 because it was causing OOMs on the UBSan
buildbot when building clang/lib/Sema/SemaChecking.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338297
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Mon, 30 Jul 2018 19:41:25 +0000 (19:41 +0000)]
Remove trailing space
sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338293
91177308-0d34-0410-b5e6-
96231b3b80d8
Manoj Gupta [Mon, 30 Jul 2018 19:33:53 +0000 (19:33 +0000)]
[Inline] Copy "null-pointer-is-valid" attribute in caller.
Summary:
Normally, inling does not happen if caller does not have
"null-pointer-is-valid"="true" attibute but callee has it.
However, alwaysinline may force callee to be inlined.
In this case, if the caller has the "null-pointer-is-valid"="true"
attribute, copy the attribute to caller.
Reviewers: efriedma, a.elovikov, lebedev.ri, jyknight
Reviewed By: efriedma
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D50000
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338292
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Mon, 30 Jul 2018 18:22:18 +0000 (18:22 +0000)]
[InstSimplify] [NFC] Tests for Select with AND/OR fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338285
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Mon, 30 Jul 2018 17:45:28 +0000 (17:45 +0000)]
[MachineOutliner][AArch64] Add support for saving LR to a register
This teaches the outliner to save LR to a register rather than the stack when
possible. This allows us to avoid bumping the stack in outlined functions in
some cases. By doing this, in a later patch, we can teach the outliner to do
something like this:
f1:
...
bl OUTLINED_FUNCTION
...
f2:
...
move LR's contents to a register
bl OUTLINED_FUNCTION
move the register's contents back
instead of falling back to saving LR in both cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338278
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 30 Jul 2018 17:34:31 +0000 (17:34 +0000)]
[X86] Fix typo in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338274
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 30 Jul 2018 17:29:57 +0000 (17:29 +0000)]
Recommit r338204 "[X86] Correct the immediate cost for 'add/sub i64 %x, 0x80000000'."
This checks in a more direct way without triggering a UBSAN error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338273
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Mon, 30 Jul 2018 17:13:25 +0000 (17:13 +0000)]
Add machine verifier to arm64-opt-remarks-lazy-bfi
Previously, I thought this was a Windows failure. Then I realized it failed on
every bot that used the verifier. This makes it use the verifier always, and
adds that pass to the pipeline checks so that it's consistent across all bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338272
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Mon, 30 Jul 2018 16:50:00 +0000 (16:50 +0000)]
[DAGCombiner] Bug 31275- Extract a shift from a constant mul or udiv if a rotate can be formed
Summary:
Attempt to extract a shrl from a udiv or a shl from a mul if this allows a rotate to be formed. This targets cases where the input to a rotate pattern was a mul or udiv by a constant and InstCombine merged one of the shifts with the op.
Patch by: sameconrad (Sam Conrad)
Reviewers: RKSimon, craig.topper, spatel, lebedev.ri, javed.absar
Reviewed By: lebedev.ri
Subscribers: efriedma, kparzysz, llvm-commits
Differential Revision: https://reviews.llvm.org/D47681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338270
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Preud'homme [Mon, 30 Jul 2018 16:48:39 +0000 (16:48 +0000)]
Reapply "Fix crash on inline asm with 64bit matching input in 32bit GPR"
This reapplies commit r338206 reverted by r338214 since the bug that
r338206 uncovered has been fixed in r338268.
Add support for inline assembly with matching input operand that do not
naturally go in the register class it is constrained to (eg. double in a
32-bit GPR). Note that regular input is already handled by existing
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338269
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Preud'homme [Mon, 30 Jul 2018 16:45:40 +0000 (16:45 +0000)]
Fix uninitialized read in ARM's PrintAsmOperand
Summary:
Fix read of uninitialized RC variable in ARM's PrintAsmOperand when
hasRegClassConstraint returns false. This was causing
inline-asm-operand-implicit-cast test to fail in r338206.
Reviewers: t.p.northover, weimingz, javed.absar, chill
Reviewed By: chill
Subscribers: chill, eraman, kristof.beyls, chrib, llvm-commits
Differential Revision: https://reviews.llvm.org/D49984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338268
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Mon, 30 Jul 2018 16:36:22 +0000 (16:36 +0000)]
Attempt to fix Windows test failure caused by r338133
It seems like the pass pipeline on Windows is slightly different than on Linux
and macOS. As a result, the arm64-opt-remarks-lazy-bfi test has been failing.
This switches a CHECK-NEXT to a CHECK-DAG to try and get this running properly
again.
It'd be nice to switch it back to a CHECK-NEXT if possible, but the CHECK-NEXT
lines following the line we care about (the optimization remark emitter)
do a pretty good job of enforcing the ordering we want.
Hopefully this works, since I don't have a Windows machine. ;)
Example failure: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/11295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338267
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Mon, 30 Jul 2018 16:20:04 +0000 (16:20 +0000)]
[SLC] Refactor the simplication of pow() (NFC)
Use more meaningful variable names. Mostly NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338266
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 30 Jul 2018 16:18:38 +0000 (16:18 +0000)]
[X86] Regenerate NOBMI/BMI combine-select tests.
Test cleanup for D38128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338265
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 30 Jul 2018 16:15:18 +0000 (16:15 +0000)]
[X86] Regenerate PKU test to merge 32/64-bit rdpkru checks
Test cleanup for D38128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338264
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 30 Jul 2018 16:13:40 +0000 (16:13 +0000)]
[X86] Regenerate fast-isel tests.
Test cleanup for D38128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338262
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Mon, 30 Jul 2018 16:05:45 +0000 (16:05 +0000)]
[AArch64][SVE] Asm: Enable instructions to be prefixed.
This patch enables instructions that are destructive on their
destination- and first source operand, to be prefixed with a
MOVPRFX instruction.
This patch also adds a variety of tests:
- positive tests for all instructions and forms that accept a
movprfx for either or both predicated and unpredicated forms.
- negative tests for all instructions and forms that do not accept
an unpredicated or predicated movprfx.
- negative tests for the diagnostics that get emitted when a MOVPRFX
instruction is used incorrectly.
This is patch [2/2] in a series to add MOVPRFX instructions:
- Patch [1/2]: https://reviews.llvm.org/D49592
- Patch [2/2]: https://reviews.llvm.org/D49593
Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D49593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338261
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Mon, 30 Jul 2018 15:42:46 +0000 (15:42 +0000)]
[AArch64][SVE] Asm: Add MOVPRFX instructions.
This patch adds predicated and unpredicated MOVPRFX instructions, which
can be prepended to SVE instructions that are destructive on their first
source operand, to make them a constructive operation, e.g.
add z1.s, p0/m, z1.s, z2.s <=> z1 = z1 + z2
can be made constructive:
movprfx z0, z1
add z0.s, p0/m, z0.s, z2.s <=> z0 = z1 + z2
The predicated MOVPRFX instruction can additionally be used to zero
inactive elements, e.g.
movprfx z0.s, p0/z, z1.s
add z0.s, p0/m, z0.s, z2.s
Not all instructions can be prefixed with the MOVPRFX instruction
which is why this patch also adds a mechanism to validate prefixed
instructions. The exact rules when a MOVPRFX applies is detailed in
the SVE supplement of the Architectural Reference Manual.
This is patch [1/2] in a series to add MOVPRFX instructions:
- Patch [1/2]: https://reviews.llvm.org/D49592
- Patch [2/2]: https://reviews.llvm.org/D49593
Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D49592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338258
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Mon, 30 Jul 2018 15:38:42 +0000 (15:38 +0000)]
[InstCombine] [NFC] Added tests for Select with binop fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338257
91177308-0d34-0410-b5e6-
96231b3b80d8
Joel Galenson [Mon, 30 Jul 2018 15:14:24 +0000 (15:14 +0000)]
[doc] Fix Getting Started typo.
This makes it easier for someone to copy-paste this line, change the path, and run the command.
Differential Revision: https://reviews.llvm.org/D49201
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338254
91177308-0d34-0410-b5e6-
96231b3b80d8
Krzysztof Parzyszek [Mon, 30 Jul 2018 14:28:02 +0000 (14:28 +0000)]
[Hexagon] Simplify A4_rcmp[n]eqi R, 0
Consider cases when register R is known to be zero/non-zero, or when it
is defined by a C2_muxii instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338251
91177308-0d34-0410-b5e6-
96231b3b80d8
John Brawn [Mon, 30 Jul 2018 14:26:24 +0000 (14:26 +0000)]
Adjust opt pass pipeline tests to cope with combination of r338240 and r338242
The combination of r338240 and r338242 causes the opt pass pipeline tests to
fail because of how r338242 makes BasicAA be invalidated more often. Adjust the
tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338250
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 30 Jul 2018 12:16:58 +0000 (12:16 +0000)]
AMDGPU: Reduce code size with fcanonicalize (fneg x)
When fcanonicalize is lowered to a mul, we can
use -1.0 for free and avoid the cost of the bigger
encoding for source modifers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338244
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 30 Jul 2018 12:16:47 +0000 (12:16 +0000)]
AMDGPU: Make fneg combine handle fcanonicalize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338243
91177308-0d34-0410-b5e6-
96231b3b80d8
John Brawn [Mon, 30 Jul 2018 11:52:08 +0000 (11:52 +0000)]
[BasicAA] Use PhiValuesAnalysis if available when handling phi alias
By using PhiValuesAnalysis we can get all the values reachable from a phi, so
we can be more precise instead of giving up when a phi has phi operands. We
can't make BaseicAA directly use PhiValuesAnalysis though, as the user of
BasicAA may modify the function in ways that PhiValuesAnalysis can't cope with.
For this optional usage to work correctly BasicAAWrapperPass now needs to be not
marked as CFG-only (i.e. it is now invalidated even when CFG is preserved) due
to how the legacy pass manager handles dependent passes being invalidated,
namely the depending pass still has a pointer to the now-dead dependent pass.
Differential Revision: https://reviews.llvm.org/D44564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338242
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexandros Lamprineas [Mon, 30 Jul 2018 10:50:18 +0000 (10:50 +0000)]
[GVNHoist] Re-enable GVNHoist by default
My initial motivation for this came from https://reviews.llvm.org/D48122,
where it was pointed out that my change didn't fit well in SimplifyCFG and
therefore using GVNHoist was a better way to go. GVNHoist has been disabled
for a while as there was a list of bugs related to it.
I have fixed the following bugs:
https://bugs.llvm.org/show_bug.cgi?id=37808 -> https://reviews.llvm.org/D48372 (rL337149)
https://bugs.llvm.org/show_bug.cgi?id=36787 -> https://reviews.llvm.org/D49555 (rL337674)
https://bugs.llvm.org/show_bug.cgi?id=37445 -> https://reviews.llvm.org/D49425 (rL337680)
The next two bugs no longer occur, and it's unclear which commit fixed them:
https://bugs.llvm.org/show_bug.cgi?id=36635
https://bugs.llvm.org/show_bug.cgi?id=37791
I investigated this one and proved to be unrelated to GVNHoist, but a genuine bug in NewGvn:
https://bugs.llvm.org/show_bug.cgi?id=37660
To convince myself GVNHoist is in a good state I made a successful bootstrap build of LLVM.
Merging this change now in order to make it to the LLVM 7.0.0 branch.
Differential Revision: https://reviews.llvm.org/D49858
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338240
91177308-0d34-0410-b5e6-
96231b3b80d8
Francis Visoiu Mistrih [Mon, 30 Jul 2018 09:59:33 +0000 (09:59 +0000)]
[MachineOutliner][X86] Use TAILJMPd64 instead of JMP_1 for TailCall construction
The machine verifier asserts with:
Assertion failed: (isMBB() && "Wrong MachineOperand accessor"), function getMBB, file ../include/llvm/CodeGen/MachineOperand.h, line 542.
It calls analyzeBranch which tries to call getMBB if the opcode is
JMP_1, but in this case we do:
JMP_1 @OUTLINED_FUNCTION
I believe we have to use TAILJMPd64 instead of JMP_1 since JMP_1 is used
with brtarget8.
Differential Revision: https://reviews.llvm.org/D49299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338237
91177308-0d34-0410-b5e6-
96231b3b80d8
Dean Michael Berris [Mon, 30 Jul 2018 09:45:09 +0000 (09:45 +0000)]
Revert "[X86] Correct the immediate cost for 'add/sub i64 %x, 0x80000000'."
This reverts commit r338204.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338236
91177308-0d34-0410-b5e6-
96231b3b80d8
Nicolai Haehnle [Mon, 30 Jul 2018 09:23:59 +0000 (09:23 +0000)]
AMDGPU: Force skip over s_sendmsg and exp instructions
Summary:
These instructions interact with hardware blocks outside the shader core,
and they can have "scalar" side effects even when EXEC = 0. We don't
want these scalar side effects to occur when all lanes want to skip
these instructions, so always add the execz skip branch instruction
for basic blocks that contain them.
Also ensure that we skip scalar stores / atomics, though we don't
code-gen those yet.
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D48431
Change-Id: Ieaeb58352e2789ffd64745603c14970c60819d44
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338235
91177308-0d34-0410-b5e6-
96231b3b80d8
Petr Pavlu [Mon, 30 Jul 2018 08:49:30 +0000 (08:49 +0000)]
[ARM] Fix over-alignment in arguments that are HA of 128-bit vectors
Code in `CC_ARM_AAPCS_Custom_Aggregate()` is responsible for handling
homogeneous aggregates for `CC_ARM_AAPCS_VFP`. When an aggregate ends up
fully on stack, the function tries to pack all resulting items of the
aggregate as tightly as possible according to AAPCS.
Once the first item was laid out, the alignment used for consecutive
items was the size of one item. This logic went wrong for 128-bit
vectors because their alignment is normally only 64 bits, and so could
result in inserting unexpected padding between the first and second
element.
The patch fixes the problem by updating the alignment with the item size
only if this results in reducing it.
Differential Revision: https://reviews.llvm.org/D49720
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338233
91177308-0d34-0410-b5e6-
96231b3b80d8
Karl-Johan Karlsson [Mon, 30 Jul 2018 08:17:00 +0000 (08:17 +0000)]
[RegisterScavenger] Fix debug print
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338231
91177308-0d34-0410-b5e6-
96231b3b80d8
Max Kazantsev [Mon, 30 Jul 2018 07:07:32 +0000 (07:07 +0000)]
[NFC] Prepare GuardWidening for widening of cond branches
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338229
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Mon, 30 Jul 2018 03:25:27 +0000 (03:25 +0000)]
Try to fix build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338227
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Mon, 30 Jul 2018 03:12:34 +0000 (03:12 +0000)]
[MS Demangler] Demangle symbols in function scopes.
There are a couple of issues you run into when you start getting into
more complex names, especially with regards to function local statics.
When you've got something like:
int x() {
static int n = 0;
return n;
}
Then this needs to demangle to something like
int `int __cdecl x()'::`1'::n
The nested mangled symbols (e.g. `int __cdecl x()` in the above
example) also share state with regards to back-referencing, so
we need to be able to re-use the demangler in the middle of
demangling a symbol while sharing back-ref state.
To make matters more complicated, there are a lot of ambiguities
when demangling a symbol's qualified name, because a function local
scope pattern (usually something like `?1??name?`) looks suspiciously
like many other possible things that can occur, such as `?1` meaning
the second back-ref and disambiguating these cases is rather
interesting. The `?1?` in a local scope pattern is actually a special
case of the more general pattern of `? + <encoded number> + ?`, where
"encoded number" can itself have embedded `@` symbols, which is a
common delimeter in mangled names. So we have to take care during the
disambiguation, which is the reason for the overly complicated
`isLocalScopePattern` function in this patch.
I've added some pretty obnoxious tests to exercise all of this, which
exposed several other problems related to back-referencing, so those
are fixed here as well. Finally, I've uncommented some tests that were
previously marked as `FIXME`, since now these work.
Differential Revision: https://reviews.llvm.org/D49965
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338226
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sun, 29 Jul 2018 18:39:26 +0000 (18:39 +0000)]
[DAGCombiner] Remove unnecessary calls to AddToWorklist.
The DAGCombiner has a mechanism for ensuring all nodes have been visited at least once. Every time a node is visited, it makes sure its operands have been in the worklist at least once. This ensures that when multiple nodes are created by a combine, only the last node needs to be returned. The earlier nodes can all be found Through this operand check. These means we don't need to explicitly add nodes to the worklist when a combine creates multiple nodes.
I've removed the most obvious cases here. There are probably more than can be removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338222
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 29 Jul 2018 18:13:16 +0000 (18:13 +0000)]
[InstCombine] try to fold 'add+sub' to 'not+add'
These are reassociated versions of the same pattern and
similar transforms as in rL338200 and rL338118.
The motivation is identical to those commits:
Patterns with add/sub combos can be improved using
'not' ops. This is better for analysis and may lead
to follow-on transforms because 'xor' and 'add' are
commutative/associative. It can also help codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338221
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 29 Jul 2018 18:07:28 +0000 (18:07 +0000)]
[InstCombine] add tests for another sub-not variant; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338220
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Sun, 29 Jul 2018 16:38:02 +0000 (16:38 +0000)]
[MS Demangler] NFC - Remove state from Demangler class.
We need to be able to initiate a nested demangling from inside
of an "outer" demangling. These need to be able to share some
state, such as back-references. As a result, we can't store
things like the output stream or the mangled name in the Demangler
class, since each demangling will have different values. So
remove this state and pass it through the necessary methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338219
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 29 Jul 2018 16:36:38 +0000 (16:36 +0000)]
[InstSimplify] fold funnel shifts with 0-shift amount
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338218
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 29 Jul 2018 16:27:17 +0000 (16:27 +0000)]
[InstSimplify] add tests for funnel shift intrinsics; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338217
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonas Devlieghere [Sun, 29 Jul 2018 14:56:15 +0000 (14:56 +0000)]
[dsymutil] Simplify temporary file handling.
Dsymutil's update functionality was broken on Windows because we tried
to rename a file while we're holding open handles to that file. TempFile
provides a solution for this through its keep(Twine) method. This patch
changes dsymutil to make use of that functionality.
Differential revision: https://reviews.llvm.org/D49860
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338216
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 29 Jul 2018 14:42:08 +0000 (14:42 +0000)]
[InstSimplify] refactor intrinsic simplifications; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338215
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sun, 29 Jul 2018 14:30:49 +0000 (14:30 +0000)]
revert r338206 because the test does not pass
Example of bot failure:
http://lab.llvm.org:8011/builders/clang-cmake-armv8-quick/builds/5107/steps/ninja%20check%201/logs/FAIL%3A%20LLVM%3A%3Ainline-asm-operand-implicit-cast.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338214
91177308-0d34-0410-b5e6-
96231b3b80d8
Dylan McKay [Sun, 29 Jul 2018 11:38:36 +0000 (11:38 +0000)]
[AVR] Re-enable expansion of ADDE/ADDC/SUBE/SUBC in ISel
This was disabled in r333748, which broke four tests.
In the future, these need to be updated to UADDO/ADDCARRY or
USUBO/SUBCARRY.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338212
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Sun, 29 Jul 2018 08:51:08 +0000 (08:51 +0000)]
[AArch64][SVE] Asm: Support for WHILE(LE|LO|LS|LT) instructions.
The WHILE instructions generate a predicate that is true while the
comparison of the first scalar operand (incremented for each predicate
element) with the second scalar operand is true and false thereafter.
WHILELE While incrementing signed scalar less than or equal to scalar
WHILELO While incrementing unsigned scalar lower than scalar
WHILELS While incrementing unsigned scalar lower than or same as scalar
WHILELT While incrementing signed scalar less than scalar
e.g.
whilele p0.s, x0, x1
generates predicate p0 (for 32bit elements) by incrementing
(signed) x0 and comparing that vector to splat(x1).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338211
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Sun, 29 Jul 2018 08:00:16 +0000 (08:00 +0000)]
[AArch64][SVE] Asm: Instructions to perform serialized operations.
The instructions added in this patch permit active elements within
a vector to be processed sequentially without unpacking the vector.
PFIRST Set the first active element to true.
PNEXT Find next active element in predicate.
CTERMEQ Compare and terminate loop when equal.
CTERMNE Compare and terminate loop when not equal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338210
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Sat, 28 Jul 2018 22:10:42 +0000 (22:10 +0000)]
[MS Demangler] Refactor some of the name parsing code.
There are some very subtle differences between how one should
parse symbol names and type names. They differ with respect
to back-referencing, the set of legal values that can appear
as the unqualified portion, and various other aspects.
By separating the parsing code into separate paths, we can
remove a lot of ambiguity during the demangling process, which
is necessary for demangling more complicated things like
function local statics, nested classes, and lambdas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338207
91177308-0d34-0410-b5e6-
96231b3b80d8
Thomas Preud'homme [Sat, 28 Jul 2018 21:33:39 +0000 (21:33 +0000)]
Fix crash on inline asm with 64bit matching input in 32bit GPR
Add support for inline assembly with matching input operand that do not
naturally go in the register class it is constrained to (eg. double in a
32-bit GPR). Note that regular input is already handled by existing
code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338206
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 28 Jul 2018 19:44:20 +0000 (19:44 +0000)]
[SelectionDAG] Pass std::vector by reference instead of by pointer to BuildSDIV/BuildUDIV.
This removes the need for an assert to ensure the pointer isn't null.
Years ago we had ifs the checked the pointer was non-null before very access to the vector. These checks were removed and replaced with a single assert. But a reference seems more suitable here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338205
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 28 Jul 2018 18:21:46 +0000 (18:21 +0000)]
[X86] Correct the immediate cost for 'add/sub i64 %x, 0x80000000'.
X86 normally requires immediates to be a signed 32-bit value which would exclude i64 0x80000000. But for add/sub we can negate the constant and use the opposite instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338204
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 28 Jul 2018 18:21:45 +0000 (18:21 +0000)]
[X86] Use alignTo and divideCeil to make some code more readable. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338203
91177308-0d34-0410-b5e6-
96231b3b80d8
Zachary Turner [Sat, 28 Jul 2018 17:25:42 +0000 (17:25 +0000)]
Add VS natvis support for LLVMDemangle's StringView.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338202
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Sat, 28 Jul 2018 17:13:33 +0000 (17:13 +0000)]
[InstCombine] Tests for fold Select with binary op
Differential Revision: https://reviews.llvm.org/D49961
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338201
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Sat, 28 Jul 2018 16:48:44 +0000 (16:48 +0000)]
[InstCombine] try to fold 'sub' to 'not'
https://rise4fun.com/Alive/jDd
Patterns with add/sub combos can be improved using
'not' ops. This is better for analysis and may lead
to follow-on transforms because 'xor' and 'add' are
commutative/associative. It can also help codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338200
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Sat, 28 Jul 2018 14:18:11 +0000 (14:18 +0000)]
[AArch64][SVE] Asm: Support for PFALSE and PTEST instructions.
This patch adds PFALSE (unconditionally sets all elements of
the predicate to false) and PTEST (set the status flags for the
predicate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338198
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Sat, 28 Jul 2018 14:11:34 +0000 (14:11 +0000)]
AMDGPU: Stop wasting argument registers with v3i32/v3f32
SelectionDAGBuilder widens v3i32/v3f32 arguments to
to v4i32/v4f32 which consume an additional register.
In addition to wasting argument space, this produces extra
instructions since now it appears the 4th vector component has
a meaningful value to most combines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338197
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Sat, 28 Jul 2018 14:04:52 +0000 (14:04 +0000)]
[AArch64][SVE] Asm: Data-dependent loop predicate partitioning instructions.
This patch adds support for instructions that partition a predicate
based on data-dependent termination conditions in a loop.
BRKA Break after the first true condition
BRKAS Break after the first true condition, setting condition flags
BRKB Break before the first true condition
BRKBS Break before the first true condition, setting condition flags
BRKPA Break after the first true condition, propagating from the
previous partition
BRKPAS Break after the first true condition, propagating from the
previous partition, setting condition flags
BRKPB Break before the first true condition, propagating from the
previous partition
BRKPBS Break before the first true condition, propagating from the
previous partition, setting condition flags
BRKN Propagate break to next partition
BKRNS Propagate break to next partition, setting condition flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338196
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Sat, 28 Jul 2018 13:52:45 +0000 (13:52 +0000)]
[InstSimplify] Moved Select + AND/OR tests from InstCombine
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338195
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Sat, 28 Jul 2018 13:25:19 +0000 (13:25 +0000)]
DAG: Add calling convention argument to calling convention funcs
This seems like a pretty glaring omission, and AMDGPU
wants to treat kernels differently from other calling
conventions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338194
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Sat, 28 Jul 2018 12:34:25 +0000 (12:34 +0000)]
AMDGPU: Stop trying to extend arguments for clover
This was trying to replace i8/i16 arguments with i32, which
was broken and no longer necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338193
91177308-0d34-0410-b5e6-
96231b3b80d8
David Green [Sat, 28 Jul 2018 08:20:10 +0000 (08:20 +0000)]
[GlobalOpt] Test array indices inside structs for out-of-bounds accesses
We now, from clang, can turn arrays of
static short g_data[] = {16, 16, 16, 16, 16, 16, 16, 16, 0, 0, 0, 0, 0, 0, 0, 0};
into structs of the form
@g_data = internal global <{ [8 x i16], [8 x i16] }> ...
GlobalOpt will incorrectly SROA it, not realising that the access to the first
element may overflow into the second. This fixes it by checking geps more
thoroughly.
I believe this makes the globalsra-partial.ll test case invalid as the %i value
could be out of bounds. I've re-purposed it as a negative test for this case.
Differential Revision: https://reviews.llvm.org/D49816
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338192
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Sat, 28 Jul 2018 06:55:51 +0000 (06:55 +0000)]
[InstCombine] Fold Select with AND/OR condition
Summary:
Fold
```
%A = icmp ne i8 %X, %V1
%B = icmp ne i8 %X, %V2
%C = or i1 %A, %B
%D = select i1 %C, i8 %X, i8 %V1
ret i8 %D
=>
ret i8 %X
Fixes https://bugs.llvm.org/show_bug.cgi?id=38334
Proof: https://rise4fun.com/Alive/plI8
Reviewers: spatel, lebedev.ri
Reviewed By: lebedev.ri
Subscribers: craig.topper, llvm-commits
Differential Revision: https://reviews.llvm.org/D49919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338191
91177308-0d34-0410-b5e6-
96231b3b80d8
Erik Pilkington [Sat, 28 Jul 2018 04:06:30 +0000 (04:06 +0000)]
[demangler] Fix an oss-fuzz bug from r338138
Stack overflow on invalid. While collapsing references, we were skipping over a
cycle check in ForwardTemplateReference leading to a stack overflow. This commit
fixes the problem by duplicating the cycle check in ReferenceType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338190
91177308-0d34-0410-b5e6-
96231b3b80d8
Jakub Kuderski [Sat, 28 Jul 2018 00:54:07 +0000 (00:54 +0000)]
[Dominators] Make applyUpdate's documentation less confusing [NFC]
Summary:
It was pointed out by @chandlerc that it's not clear whether both applyUpdates and insert/deleteEdge can be used to perform multiple updates.
IMO, the confusing part was that the comment above applyUpdates made a comparison of expected update time between calling it and calling insert/deleteEdge multiple times. It's generally not possible to safely call insert/deleteEdge multiple times, which documentation for each of the 3 functions warns about, so the whole comparison makes very little sense. On top of that, the comment is already lengthy, so I think it's best to just get rid of this comparison.
Reviewers: chandlerc, asbirlea, NutshellySima, grosser
Reviewed By: chandlerc
Subscribers: llvm-commits, chandlerc
Differential Revision: https://reviews.llvm.org/D49944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338184
91177308-0d34-0410-b5e6-
96231b3b80d8
Vedant Kumar [Sat, 28 Jul 2018 00:33:47 +0000 (00:33 +0000)]
[docs] Clarify role of DIExpressions within debug intrinsics
This should make the semantics of DIExpressions within llvm.dbg.{addr,
declare, value} easier to understand.
Differential Revision: https://reviews.llvm.org/D49572
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338182
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Sat, 28 Jul 2018 00:27:25 +0000 (00:27 +0000)]
[DAGCombiner] Teach DAG combiner that A-(B-C) can be folded to A+(C-B)
This can be useful since addition is commutable, and subtraction is not.
This matches a transform that is also done by InstCombine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338181
91177308-0d34-0410-b5e6-
96231b3b80d8
Alina Sbirlea [Sat, 28 Jul 2018 00:01:05 +0000 (00:01 +0000)]
[SimpleLoopUnswitch] Fix DT updates for trivial branch unswitching.
Summary:
Fixing 2 issues with the DT update in trivial branch switching, though I don't have a case where DT update fails.
1. After splitting ParentBB->UnswitchedBB edge, new edges become: ParentBB->LoopExitBB->UnswitchedBB, so remove ParentBB->LoopExitBB edge.
2. AFAIU, for multiple CFG changes, DT should be updated using batch updates, vs consecutive addEdge and removeEdge calls.
Reviewers: chandlerc, kuhar
Subscribers: sanjoy, jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D49925
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338180
91177308-0d34-0410-b5e6-
96231b3b80d8
Wouter van Oortmerssen [Fri, 27 Jul 2018 23:19:51 +0000 (23:19 +0000)]
Revert "[WebAssembly] Added default stack-only instruction mode for MC."
This reverts commit
d3c9af4179eae7793d1487d652e2d4e23844555f.
(SVN revision 338164)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338176
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 27 Jul 2018 23:12:11 +0000 (23:12 +0000)]
[Support] Remove unnecessary MemoryBuffer::anchor (where the destructor serves as the key function)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338175
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Fri, 27 Jul 2018 23:04:59 +0000 (23:04 +0000)]
[X86] Add support expanding multiplies by constant where the constant is -3/-5/-9 multplied by a power of 2.
These can be replaced with an LEA, a shift, and a negate. This seems to match what gcc and icc would do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338174
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 27 Jul 2018 22:51:36 +0000 (22:51 +0000)]
[llvm-objcopy] Make --strip-debug strip .zdebug* (zlib-gnu) sections
This behavior matches GNU objcopy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338173
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Fri, 27 Jul 2018 22:21:35 +0000 (22:21 +0000)]
[InstrProf] Don't register __llvm_profile_runtime_user
Refactor some FileCheck prefixes while I'm at it.
Fixes PR38340
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338172
91177308-0d34-0410-b5e6-
96231b3b80d8
Wouter van Oortmerssen [Fri, 27 Jul 2018 20:56:43 +0000 (20:56 +0000)]
[WebAssembly] Added default stack-only instruction mode for MC.
Summary:
Moved Explicit Locals pass to last.
Made that pass obligatory.
Made it convert from register to stack based instructions, and removed the registers.
Fixes to related code that was expecting register based instructions.
Added the correct testing flag to all tests, depending on what the
format they were expecting so far.
Translated one test to stack format as example: reg-stackify-stack.ll
tested:
llvm-lit -v `find test -name WebAssembly`
unittests/MC/*
Reviewers: dschuff, sunfish
Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits
Differential Revision: https://reviews.llvm.org/D49160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338164
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Fri, 27 Jul 2018 20:29:32 +0000 (20:29 +0000)]
[InstCombine] [NFC] [Tests] Fold Select with AND/OR condition - fixed
Differential Revision: https://reviews.llvm.org/D49933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338161
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Fri, 27 Jul 2018 20:18:27 +0000 (20:18 +0000)]
Recommit "Enable MachineOutliner by default under -Oz for AArch64"
Fixed the ASAN failure from before in r338148, so recommiting.
This patch enables the MachineOutliner by default in AArch64 under -Oz.
The MachineOutliner offers around a 4.5% improvement on the current -Oz code
size improvements.
We have done work into improving the debuggability of outlined code, so that
users of -Oz won't be surprised by the optimization. We have also been executing
the LLVM test suite and common external tests such as the SPEC suites
continuously with no issue. The outliner has a low compile-time overhead of
roughly 1%. At this point, the outliner would be a really good addition to the
-Oz pass pipeline!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338160
91177308-0d34-0410-b5e6-
96231b3b80d8
David Bolvansky [Fri, 27 Jul 2018 20:18:12 +0000 (20:18 +0000)]
[InstCombine] [NFC] [Tests] Fold Select with AND/OR condition
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D49932
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338159
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Fri, 27 Jul 2018 18:56:47 +0000 (18:56 +0000)]
[SLC] Test simplification of pow(x, 0.333...) to cbrt(x) (NFC)
Add test case for simplifying `pow(x, 0.333...)` into `cbrt(x)`, which
D49040 enables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338152
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 27 Jul 2018 18:31:21 +0000 (18:31 +0000)]
[AArch64, PowerPC, x86] add more signbit math tests; NFC
The tests with a constant sub operand were added with rL338143,
but the potential transform doesn't have that requirement, so
adding more tests with variable operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338150
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Fri, 27 Jul 2018 18:21:57 +0000 (18:21 +0000)]
[MachineOutliner] Exit getOutliningCandidateInfo when we erase all candidates
There was a missing check for if a candidate list was entirely deleted. This
adds that check.
This fixes an asan failure caused by running test/CodeGen/AArch64/addsub_ext.ll
with the MachineOutliner enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338148
91177308-0d34-0410-b5e6-
96231b3b80d8
Evandro Menezes [Fri, 27 Jul 2018 18:16:47 +0000 (18:16 +0000)]
[ARM] Add new target feature to fuse literal generation
This feature enables the fusion of such operations on Cortex A57 and Cortex
A72, as recommended in their Software Optimisation Guides, sections 4.14 and
4.11, respectively.
Differential revision: https://reviews.llvm.org/D49563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338147
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 27 Jul 2018 18:12:29 +0000 (18:12 +0000)]
[AArch64, PowerPC, x86] add more signbit math tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338143
91177308-0d34-0410-b5e6-
96231b3b80d8
Erik Pilkington [Fri, 27 Jul 2018 17:27:40 +0000 (17:27 +0000)]
[demangler] Support for reference collapsing
llvm.org/PR38323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338138
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Fri, 27 Jul 2018 17:25:38 +0000 (17:25 +0000)]
Revert "Enable MachineOutliner by default under -Oz for AArch64"
It failed an Asan test on a bot:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/21543/steps/check-llvm%20asan/logs/stdio
Fixing that before recommitting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338136
91177308-0d34-0410-b5e6-
96231b3b80d8
Yonghong Song [Fri, 27 Jul 2018 16:58:52 +0000 (16:58 +0000)]
bpf: add missing RegState to notify MachineInstr verifier necessary register usage
Errors like the following are reported by:
https://urldefense.proofpoint.com/v2/url?u=http-3A__lab.llvm.org-3A8011_builders_llvm-2Dclang-2Dx86-5F64-2Dexpensive-2Dchecks-2Dwin_builds_11261&d=DwIBAg&c=5VD0RTtNlTh3ycd41b3MUw&r=DA8e1B5r073vIqRrFz7MRA&m=929oWPCf7Bf2qQnir4GBtowB8ZAlIRWsAdTfRkDaK-g&s=9k-wbEUVpUm474hhzsmAO29VXVvbxJPWD9RTgCD71fQ&e=
*** Bad machine code: Explicit definition marked as use ***
- function: cal_align1
- basic block: %bb.0 entry (0x47edd98)
- instruction: LDB $r3, $r2, 0
- operand 0: $r3
This is because RegState info was missing for ScratchReg inside
expandMEMCPY. This caused incomplete register usage information to
MachineInstr verifier which then would complain as there could be potential
code-gen issue if the complained MachineInstr is used in place where
register usage information matters even though the memcpy expanding is not
in such case as it happens at the last stage of IR optimization pipeline.
We should always specify those register usage information which compiler
couldn't deduct automatically whenever we add a hardware register manually.
Reported-by: Builder llvm-clang-x86_64-expensive-checks-win Build #11261
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338134
91177308-0d34-0410-b5e6-
96231b3b80d8
Jessica Paquette [Fri, 27 Jul 2018 16:44:42 +0000 (16:44 +0000)]
Enable MachineOutliner by default under -Oz for AArch64
This patch enables the MachineOutliner by default in AArch64 under -Oz.
The MachineOutliner offers around a 4.5% improvement on the current -Oz code
size improvements.
We have done work into improving the debuggability of outlined code, so that
users of -Oz won't be surprised by the optimization. We have also been executing
the LLVM test suite and common external tests such as the SPEC suites
continuously with no issue. The outliner has a low compile-time overhead of
roughly 1%. At this point, the outliner would be a really good addition to the
-Oz pass pipeline!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338133
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 27 Jul 2018 16:42:55 +0000 (16:42 +0000)]
[DAGCombiner] fold 'not' with signbit math
This is a follow-up suggested in D48970.
Alive proofs:
https://rise4fun.com/Alive/sII
We can eliminate an instruction in the usual select-of-constants
to bit hack transform by adjusting the add/sub with constant.
This is always a win.
There are more transforms that are likely wins, but they may need
target hooks in case some targets do not benefit.
This is another step towards making up for canonicalizing to
select-of-constants in rL331486.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338132
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 27 Jul 2018 16:22:40 +0000 (16:22 +0000)]
[x86] add more tests for signbit math; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338131
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 27 Jul 2018 16:22:18 +0000 (16:22 +0000)]
[PowerPC] add more tests for signbit math; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338130
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Fri, 27 Jul 2018 16:21:56 +0000 (16:21 +0000)]
[AArch64] add more tests for signbit math; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338129
91177308-0d34-0410-b5e6-
96231b3b80d8
Fangrui Song [Fri, 27 Jul 2018 16:01:09 +0000 (16:01 +0000)]
[Support] Use unsigned char for xxHash 64-bit
Before, the last 3 bytes were char-signedness dependent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338128
91177308-0d34-0410-b5e6-
96231b3b80d8
Jan Vesely [Fri, 27 Jul 2018 15:00:13 +0000 (15:00 +0000)]
AMDGPU/R600: Add MOV instructions to BFE patterns
R600 can't handle immediates for BFE, these will be eliminated later.
Fixes powr/pow regressions n r600 since r334817
Differential Revision: https://reviews.llvm.org/D49641
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338127
91177308-0d34-0410-b5e6-
96231b3b80d8
Sander de Smalen [Fri, 27 Jul 2018 14:24:55 +0000 (14:24 +0000)]
[AArch64][SVE] Asm: Predicated integer reductions.
This patch adds support for various integer reduction operations:
SADDV signed add reduction to scalar
UADDV unsigned add reduction to scalar
SMAXV signed maximum reduction to scalar
SMINV signed minimum reduction to scalar
UMAXV unsigned maximum reduction to scalar
UMINV unsigned minimum reduction to scalar
ANDV logical AND reduction to scalar
ORV logical OR reduction to scalar
EORV logical EOR reduction to scalar
The reduction is predicated, e.g.
smaxv s0, p0, z1.s
performs a signed maximum reduction on active elements in z1,
and stores the (signed max value) result in s0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338126
91177308-0d34-0410-b5e6-
96231b3b80d8
Dmitry Preobrazhensky [Fri, 27 Jul 2018 14:17:15 +0000 (14:17 +0000)]
[AMDGPU][MC][DOC] Updated AMD GPU assembler description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338125
91177308-0d34-0410-b5e6-
96231b3b80d8