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Xiang, Haihao [Mon, 17 Jun 2013 07:06:11 +0000 (15:06 +0800)]
Fix copy&paste error
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 06:54:53 +0000 (14:54 +0800)]
VEBOX: output 2 frames for advanced DI
Both current frame and previous frame are outputted
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 06:40:26 +0000 (14:40 +0800)]
VEBOX: motion adaptive DI on HSW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 14 Jun 2013 03:40:42 +0000 (11:40 +0800)]
VEBOX: update internal surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 12:31:11 +0000 (20:31 +0800)]
VEBOX: track the frame sequence
Preparation work for advanced DI
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 12:50:58 +0000 (20:50 +0800)]
VEBOX: clean up
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 08:39:13 +0000 (16:39 +0800)]
VEBOX: Update VEBOX_STATE for Bob DI
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 07:55:27 +0000 (15:55 +0800)]
VEBOX: Update DNDI table on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 13 Jun 2013 03:31:36 +0000 (11:31 +0800)]
Update the supported render target format and pixel format
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 7 Jun 2013 08:56:45 +0000 (16:56 +0800)]
Update the implementation of vaQueryVideoProcFilterCaps()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 30 May 2013 08:41:09 +0000 (16:41 +0800)]
Update the implementation of vaQueryVideoProcFilters()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 30 May 2013 06:52:15 +0000 (14:52 +0800)]
VAProcFilterNone isn't a actual filter
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 7 Jun 2013 01:47:22 +0000 (09:47 +0800)]
Return supported external memory types in vaQuerySurfaceAttributes()
Return the number of elements actually filled in output as well.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 6 Jun 2013 08:51:02 +0000 (16:51 +0800)]
Add support for vaQuerySurfaceAttributes()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 6 Jun 2013 07:38:09 +0000 (15:38 +0800)]
Add support for VA_SURFACE_ATTRIB_MEM_TYPE_KERNEL_DRM and VA_SURFACE_ATTRIB_MEM_TYPE_DRM_PRIME
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li Xiaowei [Wed, 19 Jun 2013 18:07:48 +0000 (02:07 +0800)]
VEBOX: Fix image garbage at border when pro amp
Aligned width/height are required to be registered
to surface state, instead of original width/height
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Wed, 19 Jun 2013 17:33:01 +0000 (01:33 +0800)]
VEBOX: Fix endingX setting for dndi/iecp command
The endingX need be aligned to 64 and subtract 1
before setting to VEBOX command.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Sun, 9 Jun 2013 15:26:15 +0000 (23:26 +0800)]
VEBOX: Turn off CSC function in VEBOX pipeline
all surface format conversion process and CSC will
be done through shader, this will simplify the pipeline
data flow especially for multiple filters case.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Sun, 9 Jun 2013 07:43:08 +0000 (15:43 +0800)]
More reserved PCI IDs for Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
a9c66609b289c815b2bfc0385dc1f3bff6677125)
Xiang, Haihao [Sun, 9 Jun 2013 07:34:20 +0000 (15:34 +0800)]
Update max_wm_threads on Haswell
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
c31f6130793c68a83d1cb1116da60489d5e4a1d4)
Xiang, Haihao [Sun, 9 Jun 2013 07:29:15 +0000 (15:29 +0800)]
Fix Haswell GT3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
3c9e778718cb4d24695a880afb45e32cdf43a434)
Xiang, Haihao [Mon, 27 May 2013 02:19:10 +0000 (10:19 +0800)]
A workaround for clearing a Y-tiled surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
9c698455fec340ced7dbf93cc5be004bb4a1eb22)
Xiang, Haihao [Wed, 22 May 2013 06:23:53 +0000 (14:23 +0800)]
version 1.2.0.pre1
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 22 May 2013 05:34:16 +0000 (13:34 +0800)]
VPP: Update the mapping of VPP filter to internal flag
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 22 May 2013 05:30:53 +0000 (13:30 +0800)]
remove VAProcFilterColorStandard
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 21 May 2013 08:48:54 +0000 (16:48 +0800)]
VPP/HSW: don't use VAProcFilterColorStandard
VAProcFilterColorStandard will be removed from va_vpp.h
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 20 May 2013 08:08:54 +0000 (16:08 +0800)]
Support tiled surface for IMC1/IMC3
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 20 May 2013 08:19:41 +0000 (16:19 +0800)]
Use IMC3 for JPEG decoding
To match the pre-defined VA FOURCC in va.h
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Thu, 9 May 2013 08:53:07 +0000 (16:53 +0800)]
Add the config attribute of EncMaxRefFrames
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:53:50 +0000 (13:53 +0800)]
PAK encoding uses the reference list parsed from slice_param instead of hacked DPB
Of course it still can work if the slice_param doesn't contain the
valid REfPicList0/1(Hacked DPB mode). This is to be compatible with
the older version of avcenc tool.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:52:31 +0000 (13:52 +0800)]
Unify the AVC ref frame index setting on Snb/Ivy/HSW
This is to remove the duplicated code.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 9 May 2013 05:52:28 +0000 (13:52 +0800)]
VME uses reference frame parsed from slice_param instead of hacked DPB
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Wed, 24 Apr 2013 08:54:09 +0000 (16:54 +0800)]
Clean up gen7_vme_context_init()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:48:58 +0000 (09:48 +0800)]
Rework the VPP CSC shader from NV12 to RGB to eliminate corruption
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:48:12 +0000 (09:48 +0800)]
Fix the incorrect VPP parameter setting on Ivy/Haswell
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 3 Apr 2013 01:47:53 +0000 (09:47 +0800)]
Handle the pitch when using RGBX surface in VPP
Signed-off-by: Ung, Teng En <teng.en.ung@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Xiang, Haihao [Wed, 3 Apr 2013 00:58:13 +0000 (08:58 +0800)]
Merge branch 'master' into staging
Conflicts:
NEWS
configure.ac
src/Makefile.am
src/gen6_mfc.c
src/gen6_mfd.c
src/gen6_vme.c
src/gen6_vme.h
src/gen75_mfc.c
src/gen75_mfd.c
src/gen75_vme.c
src/gen75_vpp_vebox.c
src/gen75_vpp_vebox.h
src/gen7_mfd.c
src/i965_avc_bsd.c
src/i965_decoder.h
src/i965_decoder_utils.c
src/i965_defines.h
src/i965_drv_video.c
src/i965_drv_video.h
src/i965_encoder.c
src/i965_encoder.h
src/i965_output_dri.c
src/i965_post_processing.c
src/i965_post_processing.h
src/i965_render.c
src/i965_structs.h
src/intel_driver.c
src/object_heap.c
src/shaders/post_processing/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/Common/Init_All_Regs.asm
src/shaders/post_processing/Makefile.am
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/AYUV_Load_16x8.inc
src/shaders/post_processing/gen5_6/Common/Init_All_Regs.asm
src/shaders/post_processing/gen5_6/Common/NV12_Load_8x4.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.asm
src/shaders/post_processing/gen5_6/Common/RGBX_Load_16x8.inc
src/shaders/post_processing/gen5_6/Makefile.am
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_avs_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dn_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pa.g6b
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/nv12_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pa_load_save_pl3.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_nv12.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pa.g6b
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g4b.gen5
src/shaders/post_processing/gen5_6/pl3_load_save_pl3.g6b
src/shaders/post_processing/gen7/EOT.g4a
src/shaders/post_processing/gen7/Makefile.am
src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PA_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL2_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_1.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_2.g4a
src/shaders/post_processing/gen7/PL3_AVS_Buf_3.g4a
src/shaders/post_processing/gen7/Save_AVS_NV12.g4a
src/shaders/post_processing/gen7/Save_AVS_PA.g4a
src/shaders/post_processing/gen7/Save_AVS_PL3.g4a
src/shaders/post_processing/gen7/Save_AVS_RGB.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_BGRA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL2.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_PL3.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VUYA.g4a
src/shaders/post_processing/gen7/Set_AVS_Buf_0123_VYUA.g4a
src/shaders/post_processing/gen7/Set_Layer_0.g4a
src/shaders/post_processing/gen7/VP_Setup.g4a
src/shaders/vme/Makefile.am
src/shaders/vme/inter_frame_haswell.asm
src/shaders/vme/inter_frame_haswell.g75b
src/shaders/vme/intra_frame_haswell.asm
src/shaders/vme/intra_frame_haswell.g75b
src/shaders/vme/vme75.inc
src/shaders/vme/vme7_mpeg2.inc
Li Xiaowei [Tue, 26 Mar 2013 01:06:18 +0000 (09:06 +0800)]
Fix the obj_image error in i965_hw_putimage
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Tue, 19 Mar 2013 05:00:10 +0000 (13:00 +0800)]
Bump version for development.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 19 Mar 2013 02:19:23 +0000 (10:19 +0800)]
libva-intel-driver 1.0.20
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Armin K [Fri, 15 Mar 2013 17:22:10 +0000 (18:22 +0100)]
Automake 1.13 fixups
error: 'AM_CONFIG_HEADER': this macro is obsolete.
You should use the 'AC_CONFIG_HEADERS' macro instead.
warning: 'INCLUDES' is the old name for 'AM_CPPFLAGS' (or '*_CPPFLAGS')
Added NOCONFIGURE check to autogen.sh
Xiang, Haihao [Fri, 15 Mar 2013 07:39:35 +0000 (15:39 +0800)]
Fix the size to malloc()
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 07:19:49 +0000 (15:19 +0800)]
Check the pointer is NULL or not
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 07:32:01 +0000 (15:32 +0800)]
Fix potential buffer overflow for JPEG decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 07:04:12 +0000 (15:04 +0800)]
Remove the dead code in gen6_vme.c
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 05:44:23 +0000 (13:44 +0800)]
Check object for VA buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 04:51:33 +0000 (12:51 +0800)]
Check the object for VA buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 03:16:50 +0000 (11:16 +0800)]
Check the object instance of VAConfig
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 15 Mar 2013 02:50:58 +0000 (10:50 +0800)]
Check the object instance instead of the id for subpicture and image
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 14 Mar 2013 07:47:05 +0000 (15:47 +0800)]
VPP: check the backing store buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 13 Mar 2013 07:26:33 +0000 (15:26 +0800)]
Render: directly use the backing store buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 13 Mar 2013 05:59:18 +0000 (13:59 +0800)]
Decoder: use surface object for the workaround
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 13 Mar 2013 06:11:05 +0000 (14:11 +0800)]
Decoder: directly use surface object for decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 13 Mar 2013 02:43:17 +0000 (10:43 +0800)]
Decoder: Verify picture parameter before set up pipeline for decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 12 Mar 2013 07:12:07 +0000 (15:12 +0800)]
Decoder: check whether the surface for decoding output is valid
In addition, uses the corresponding surface object directly.
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 12 Mar 2013 07:34:21 +0000 (15:34 +0800)]
Encoder: directly use the objects for the reference pictures
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Mon, 11 Mar 2013 02:44:56 +0000 (10:44 +0800)]
Encoder: directly use the objects for the reconstructed picture and coded buffer
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Mar 2013 06:57:08 +0000 (14:57 +0800)]
Encoder: check whether the coded buffer and reconstructed surface are valid
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 12 Mar 2013 05:25:24 +0000 (13:25 +0800)]
Encoder: unify the initialization of the context
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Tue, 12 Mar 2013 05:23:03 +0000 (13:23 +0800)]
Encoder: directly use the surface object of the input surface
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Mar 2013 02:59:48 +0000 (10:59 +0800)]
Return the status when running the pipeline
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 8 Mar 2013 02:36:41 +0000 (10:36 +0800)]
Silence a bunch of warnings
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Mar 2013 07:55:59 +0000 (15:55 +0800)]
Avoid potential buffer overflow issue
Warning if the slice type is wrong for encoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Mar 2013 05:52:12 +0000 (13:52 +0800)]
Release resource if failed to initialize display attributes
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Mar 2013 05:48:02 +0000 (13:48 +0800)]
Fix the initilization path and the termination path in reverse
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Thu, 7 Mar 2013 02:04:10 +0000 (10:04 +0800)]
Fix object_heap_init() & object_heap_destroy()
Don't allocate resources if failed to initialize a heap
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Zhao Yakui [Wed, 13 Mar 2013 01:29:23 +0000 (09:29 +0800)]
Issue memory fence message to assure memory ordering on Ivb/Hsw
Otherwise the data inconsistency between different GPU threads
is observed although the GPU threads are spawned by using hardware
scoreboard. Then it causes that avcenc encoding gets the different
results.
Reported-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Li Xiaowei [Tue, 12 Mar 2013 05:25:39 +0000 (13:25 +0800)]
Fix H264 YUV400 surface render issue on IVB
All decoded frame are considered as NV12 format in driver,
for YUV400 stream format decoding senerios, we need set the
chroma component of NV12 to a constant value(0x80), otherwise
the converted ARGB from NV12 format is not correct and cause
blue screen when rending.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Xiang, Haihao [Mon, 4 Mar 2013 07:56:06 +0000 (15:56 +0800)]
Update PCI IDs for Haswell CRW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
82d6940694c7a650642ccb6d68bf01b70dba4dcc)
Xiang, Haihao [Mon, 4 Mar 2013 07:56:06 +0000 (15:56 +0800)]
Update PCI IDs for Haswell CRW
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 22 Feb 2013 05:56:04 +0000 (13:56 +0800)]
Update the size of DMV buffer for H.264 decoding on IVB
It is at least width_in_mbs * align(height_in_mbs, 2) * 64.
Use width_in_mbs * (height_in_mbs + 1) * 64 in the driver.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59050
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
00f65b78e6de520a4820702207ce098c6b073724)
Xiang, Haihao [Fri, 22 Feb 2013 05:56:04 +0000 (13:56 +0800)]
Update the size of DMV buffer for H.264 decoding on IVB
It is at least width_in_mbs * align(height_in_mbs, 2) * 64.
Use width_in_mbs * (height_in_mbs + 1) * 64 in the driver.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59050
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Fri, 22 Feb 2013 00:42:33 +0000 (08:42 +0800)]
Don't have flag register f2, use f1 instead
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
f6ec762eab4e602a0644e9f17ce97dab34bf512f)
Conflicts:
src/shaders/post_processing/gen7/PA_AVS_Buf_0.g4a
src/shaders/post_processing/gen7/rgbx_to_nv12.g75b
src/shaders/post_processing/gen7/rgbx_to_nv12.g7b
Xiang, Haihao [Fri, 22 Feb 2013 00:42:33 +0000 (08:42 +0800)]
Don't have flag register f2, use f1 instead
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Adrian Marius Negreanu [Mon, 18 Feb 2013 13:01:16 +0000 (15:01 +0200)]
gen6: MPEG2 is not supported by gen6 pipeline
Commit
65e10683 added MPEG2 encoding for IVB but also for gen6.
This causes a missmatch between the profile(MPEG) and the pipeline
used(AVC).
Signed-off-by: Adrian Marius Negreanu <adrian.m.negreanu@intel.com>
Adrian Marius Negreanu [Mon, 18 Feb 2013 08:58:19 +0000 (10:58 +0200)]
add replacement for log2f when not available
Signed-off-by: Adrian Marius Negreanu <adrian.m.negreanu@intel.com>
Adrian Marius Negreanu [Mon, 18 Feb 2013 08:51:54 +0000 (10:51 +0200)]
intel-driver, android: update src/Android.mk
Signed-off-by: Adrian Marius Negreanu <adrian.m.negreanu@intel.com>
Xiang, Haihao [Tue, 5 Feb 2013 08:39:37 +0000 (16:39 +0800)]
Update the binding table index on IVB
The index used by the shader is 33 instead of 5.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59693
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li Xiaowei [Mon, 28 Jan 2013 05:22:09 +0000 (13:22 +0800)]
Correct the mv offset for mpeg2 encoding on HSW
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li, Xiaowei A [Wed, 12 Dec 2012 01:16:25 +0000 (09:16 +0800)]
Fill the bitplane for VC1 skip picture decoding
This is a workaround for VC1 skip picture, the corresponding
bit value in bitplane should be 1 for skip picture, but sometimes
application pass down wrong value.
Signed-off-by: Li,Xiaowei <xiaowei.a.li@intel.com>
(cherry picked from commit
a76acf6441a414bb5dd601485ed8ed790218bb13)
Zhao Yakui [Fri, 18 Jan 2013 05:37:09 +0000 (13:37 +0800)]
Fix the issue of GPU hang when encoding picture with one macroblock width
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reported-by: Xiang Haihao <haihao.xiang@intel.com>
Xiang, Haihao [Wed, 23 Jan 2013 01:59:17 +0000 (09:59 +0800)]
Enlarge deblocking filter row store for VC-1 decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
(cherry picked from commit
e8d3f90fc18ca3726e6b34156ba56ee92c2a2524)
Xiang, Haihao [Wed, 23 Jan 2013 01:59:17 +0000 (09:59 +0800)]
Enlarge deblocking filter row store for VC-1 decoding
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Li Xiaowei [Tue, 15 Jan 2013 06:46:17 +0000 (14:46 +0800)]
Refine mpeg2 mfc pipeline code
move mpeg2 mfc code from gen6_mfc.c to gen7_mfc.c,
because mpeg2 paking is not supported on gen6.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Tue, 15 Jan 2013 07:26:14 +0000 (15:26 +0800)]
apply new mv offset for mpeg2 encoding on HSW
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Zhao Yakui [Mon, 14 Jan 2013 02:45:14 +0000 (10:45 +0800)]
Use the common scoreboard code on Ivy/Haswell to remove the duplicated code
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Mon, 14 Jan 2013 02:45:09 +0000 (10:45 +0800)]
Keep the old indent style in file of gen7_vme/gen75_vme
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Asked-by: Xiang Haihao <haihao.xiang@intel.com>
Zhao Yakui [Mon, 14 Jan 2013 02:45:03 +0000 (10:45 +0800)]
Fix one error of calculating VME parameter for inter-frame on Haswell
At the same time it fixes the typo in comments.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 10 Jan 2013 09:16:35 +0000 (17:16 +0800)]
Update the binary code for MPEG2 VME on haswell
The same source code is used by AVC and MPEG2 VME. But the binary shader
for MPEG2 is not updated after adding the MVP for AVC.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Yakui Zhao [Thu, 10 Jan 2013 09:10:39 +0000 (17:10 +0800)]
Remove the intermedia file of mpeg2_inter_frame_haswell.gen75.asm
Zhao Yakui [Thu, 10 Jan 2013 07:25:24 +0000 (15:25 +0800)]
Add the bidirectional MVP to optimize the VME parameter on Ivb
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 10 Jan 2013 07:25:24 +0000 (15:25 +0800)]
Use the scoreboard for AVC encoding on Ivy
This is backported from the Haswell and it is required in order to
add the MVP prediction as it is based on the neighbour macroblocks.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 10 Jan 2013 07:25:24 +0000 (15:25 +0800)]
Backport the mode/mv cost table on Ivy
Add the implement on Haswell for Ivy. Then it can select the different
predition mode based on the quality requirement.
Signedo-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 10 Jan 2013 07:25:24 +0000 (15:25 +0800)]
Add the VME shader for Ivy that supports MVP
This is to optimize the VME parameter for Ivy, which is backported
from Haswell.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Thu, 10 Jan 2013 07:25:24 +0000 (15:25 +0800)]
Add the separated encoding files for Ivy
This is to do the prepration of backing port the Haswell VME motion vector
prediction for Ivy.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Yakui Zhao [Thu, 10 Jan 2013 01:22:23 +0000 (09:22 +0800)]
Remove the intermediate file of mpeg2_inter_frame.gen7.asm as it is generated from compiling the shader.
Zhao Yakui [Wed, 9 Jan 2013 04:30:04 +0000 (12:30 +0800)]
Fix one compiling warning of floor implicit definition
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Zhao Yakui [Wed, 9 Jan 2013 04:29:59 +0000 (12:29 +0800)]
Fix the error of reading neighbour macroblock pixels during VME prediction on Snb/Ivy
Otherwise the incorrect result of VME prediction is used.
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Li Xiaowei [Sun, 6 Jan 2013 07:17:59 +0000 (15:17 +0800)]
VPP: Support multi filters for vebox pipeline
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
Li Xiaowei [Sat, 5 Jan 2013 03:02:18 +0000 (11:02 +0800)]
VEBOX: clean supported fourcc format in VPP pipeline
clean up the supported surface format at the begining
and the ending of post processing pipepile, these formats
will be convertd to/from vebox supported formats.
Signed-off-by: Li Xiaowei <xiaowei.a.li@intel.com>
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