OSDN Git Service
Luc Michel [Tue, 17 Oct 2023 19:44:16 +0000 (21:44 +0200)]
hw/net/cadence_gem: use FIELD to describe DMACFG register fields
Use de FIELD macro to describe the DMACFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id:
20231017194422.
4124691-6-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Luc Michel [Tue, 17 Oct 2023 19:44:15 +0000 (21:44 +0200)]
hw/net/cadence_gem: use FIELD to describe NWCFG register fields
Use de FIELD macro to describe the NWCFG register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id:
20231017194422.
4124691-5-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Luc Michel [Tue, 17 Oct 2023 19:44:14 +0000 (21:44 +0200)]
hw/net/cadence_gem: use FIELD to describe NWCTRL register fields
Use the FIELD macro to describe the NWCTRL register fields.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id:
20231017194422.
4124691-4-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Luc Michel [Tue, 17 Oct 2023 19:44:13 +0000 (21:44 +0200)]
hw/net/cadence_gem: use FIELD for screening registers
Describe screening registers fields using the FIELD macros.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id:
20231017194422.
4124691-3-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Luc Michel [Tue, 17 Oct 2023 19:44:12 +0000 (21:44 +0200)]
hw/net/cadence_gem: use REG32 macro for register definitions
Replace register defines with the REG32 macro from registerfields.h in
the Cadence GEM device.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: sai.pavan.boddu@amd.com
Message-id:
20231017194422.
4124691-2-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Glenn Miles [Tue, 24 Oct 2023 19:19:45 +0000 (14:19 -0500)]
misc/led: LED state is set opposite of what is expected
Testing of the LED state showed that when the LED polarity was
set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
the input GPIO of the LED, the LED was being turn off when it was
expected to be turned on.
Fixes:
ddb67f6402 ("hw/misc/led: Allow connecting from GPIO output")
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Message-id:
20231024191945.
4135036-1-milesg@linux.vnet.ibm.com
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:59:09 +0000 (08:59 +0200)]
hw/arm: Avoid using 'first_cpu' when first ARM CPU is reachable
Prefer using a well known local first CPU rather than a global one.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231025065909.57344-1-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:30 +0000 (15:03 +0200)]
hw/arm/pxa2xx: Realize PXA2XX_I2C device before accessing it
qbus_new(), called in i2c_init_bus(), should not be called
on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id:
20231020130331.50048-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:29 +0000 (15:03 +0200)]
hw/intc/pxa2xx: Factor pxa2xx_pic_realize() out of pxa2xx_pic_init()
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id:
20231020130331.50048-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:28 +0000 (15:03 +0200)]
hw/intc/pxa2xx: Pass CPU reference using QOM link property
QOM objects shouldn't access each other internals fields
except using the QOM API.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id:
20231020130331.50048-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:27 +0000 (15:03 +0200)]
hw/intc/pxa2xx: Convert to Resettable interface
Factor reset code out of the DeviceRealize() handler.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id:
20231020130331.50048-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:26 +0000 (15:03 +0200)]
hw/pcmcia/pxa2xx: Inline pxa2xx_pcmcia_init()
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231020130331.50048-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:25 +0000 (15:03 +0200)]
hw/pcmcia/pxa2xx: Do not open-code sysbus_create_simple()
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231020130331.50048-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:24 +0000 (15:03 +0200)]
hw/pcmcia/pxa2xx: Realize sysbus device before accessing it
sysbus_mmio_map() should not be called on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231020130331.50048-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:23 +0000 (15:03 +0200)]
hw/sd/pxa2xx: Do not open-code sysbus_create_simple()
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231020130331.50048-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Fri, 20 Oct 2023 13:03:22 +0000 (15:03 +0200)]
hw/sd/pxa2xx: Realize sysbus device before accessing it
sysbus_mmio_map() and sysbus_connect_irq() should not be
called on unrealized device.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231020130331.50048-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:16 +0000 (08:53 +0200)]
hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:15 +0000 (08:53 +0200)]
hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-10-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:14 +0000 (08:53 +0200)]
hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-9-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:13 +0000 (08:53 +0200)]
hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-8-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:12 +0000 (08:53 +0200)]
hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-7-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:11 +0000 (08:53 +0200)]
hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:10 +0000 (08:53 +0200)]
hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-5-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:09 +0000 (08:53 +0200)]
hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-4-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:08 +0000 (08:53 +0200)]
hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 25 Oct 2023 06:53:07 +0000 (08:53 +0200)]
hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from header
"hw/arm/boot.h" is only required on the source file.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Luc Michel <luc.michel@amd.com>
Message-id:
20231025065316.56817-2-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 24 Oct 2023 17:24:38 +0000 (18:24 +0100)]
target/arm: Fix syndrome for FGT traps on ERET
In commit
442c9d682c94fc2 when we converted the ERET, ERETAA, ERETAB
instructions to decodetree, the conversion accidentally lost the
correct setting of the syndrome register when taking a trap because
of the FEAT_FGT HFGITR_EL1.ERET bit. Instead of reporting a correct
full syndrome value with the EC and IL bits, we only reported the low
two bits of the syndrome, because the call to syn_erettrap() got
dropped.
Fix the syndrome values for these traps by reinstating the
syn_erettrap() calls.
Fixes:
442c9d682c94fc2 ("target/arm: Convert ERET, ERETAA, ERETAB to decodetree")
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231024172438.
2990945-1-peter.maydell@linaro.org
Peter Maydell [Tue, 24 Oct 2023 16:35:10 +0000 (17:35 +0100)]
target/arm: Move ID_AA64DFR* feature tests together
Move all the ID_AA64DFR* feature test functions together.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231024163510.
2972081-7-peter.maydell@linaro.org
Peter Maydell [Tue, 24 Oct 2023 16:35:09 +0000 (17:35 +0100)]
target/arm: Move ID_AA64PFR* tests together
Move all the ID_AA64PFR* feature test functions together.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231024163510.
2972081-6-peter.maydell@linaro.org
Peter Maydell [Tue, 24 Oct 2023 16:35:08 +0000 (17:35 +0100)]
target/arm: Move ID_AA64ISAR* test functions together
Move the feature test functions that test ID_AA64ISAR* fields
together.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231024163510.
2972081-5-peter.maydell@linaro.org
Peter Maydell [Tue, 24 Oct 2023 16:35:07 +0000 (17:35 +0100)]
target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2
Move the ID_AA64MMFR0 feature test functions up so they are
before the ones for ID_AA64MMFR1 and ID_AA64MMFR2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231024163510.
2972081-4-peter.maydell@linaro.org
Peter Maydell [Tue, 24 Oct 2023 16:35:06 +0000 (17:35 +0100)]
target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests together
Our list of isar_feature functions is not in any particular order,
but tests on fields of the same ID register tend to be grouped
together. A few functions that are tests of fields in ID_AA64MMFR1
and ID_AA64MMFR2 are not in the same place as the rest; move them
into their groups.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231024163510.
2972081-3-peter.maydell@linaro.org
Peter Maydell [Tue, 24 Oct 2023 16:35:05 +0000 (17:35 +0100)]
target/arm: Move feature test functions to their own header
The feature test functions isar_feature_*() now take up nearly
a thousand lines in target/arm/cpu.h. This header file is included
by a lot of source files, most of which don't need these functions.
Move the feature test functions to their own header file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20231024163510.
2972081-2-peter.maydell@linaro.org
Peter Maydell [Fri, 15 Sep 2023 18:54:53 +0000 (19:54 +0100)]
target/arm: Implement Neoverse N2 CPU model
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A
processor very similar to the Cortex-A710. The differences are:
* no FEAT_EVT
* FEAT_DGH (data gathering hint)
* FEAT_NV (not yet implemented in QEMU)
* Statistical Profiling Extension (not implemented in QEMU)
* 48 bit physical address range, not 40
* CTR_EL0.DIC = 1 (no explicit icache cleaning needed)
* PMCR_EL0.N = 6 (always 6 PMU counters, not 20)
Because it has 48-bit physical address support, we can use
this CPU in the sbsa-ref board as well as the virt board.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20230915185453.
1871167-3-peter.maydell@linaro.org
Peter Maydell [Fri, 15 Sep 2023 18:54:52 +0000 (19:54 +0100)]
target/arm: Correct minor errors in Cortex-A710 definition
Correct a couple of minor errors in the Cortex-A710 definition:
* ID_AA64DFR0_EL1.DebugVer is 9 (indicating Armv8.4 debug architecture)
* ID_AA64ISAR1_EL1.APA is 5 (indicating more PAuth support)
* there is an IMPDEF CPUCFR_EL1, like that on the Neoverse-N1
Fixes:
e3d45c0a89576 ("target/arm: Implement cortex-a710")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20230915185453.
1871167-2-peter.maydell@linaro.org
Stefan Hajnoczi [Fri, 27 Oct 2023 00:43:53 +0000 (09:43 +0900)]
Merge tag 'pull-sp-
20231025' of https://gitlab.com/rth7680/qemu into staging
Convert target/sparc to decodetree.
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# gpg: Signature made Thu 26 Oct 2023 09:12:16 JST
# gpg: using RSA key
7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-sp-
20231025' of https://gitlab.com/rth7680/qemu: (94 commits)
target/sparc: Remove disas_sparc_legacy
target/sparc: Convert FZERO, FONE to decodetree
target/sparc: Move FPACK16, FPACKFIX to decodetree
target/sparc: Move FPCMP* to decodetree
target/sparc: Convert FCMP, FCMPE to decodetree
target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
target/sparc: Move FdTOq, FxTOq to decodetree
target/sparc: Move FiTOq, FsTOq to decodetree
target/sparc: Move FqTOd, FqTOx to decodetree
target/sparc: Move FqTOs, FqTOi to decodetree
target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
target/sparc: Move gen_fop_FD insns to decodetree
target/sparc: Move FDMULQ to decodetree
target/sparc: Move FSMULD to decodetree
target/sparc: Move gen_fop_QQQ insns to decodetree
target/sparc: Move gen_fop_DDD insns to decodetree
target/sparc: Move gen_fop_FFF insns to decodetree
target/sparc: Move FSQRTq to decodetree
target/sparc: Move gen_fop_DD insns to decodetree
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Fri, 27 Oct 2023 00:43:07 +0000 (09:43 +0900)]
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: implement SHA instructions
* target/i386: check CPUID_PAE to determine 36 bit processor address space
* target/i386: improve validation of AVX instructions
* require Linux 4.4 for KVM
# -----BEGIN PGP SIGNATURE-----
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# QHJlZGhhdC5jb20ACgkQv/vSX3jHroNVbwf9HCx+C0MITWjQ+rEkmtiy/Cn+ZsF1
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# =WYTo
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 26 Oct 2023 02:53:50 JST
# gpg: using RSA key
F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (24 commits)
kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2
kvm: i386: require KVM_CAP_SET_IDENTITY_MAP_ADDR
kvm: i386: require KVM_CAP_ADJUST_CLOCK
kvm: i386: require KVM_CAP_MCE
kvm: i386: require KVM_CAP_SET_VCPU_EVENTS and KVM_CAP_X86_ROBUST_SINGLESTEP
kvm: i386: require KVM_CAP_XSAVE
kvm: i386: require KVM_CAP_DEBUGREGS
kvm: i386: move KVM_CAP_IRQ_ROUTING detection to kvm_arch_required_capabilities
kvm: unify listeners for PIO address space
kvm: require KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH
kvm: assume that many ioeventfds can be created
kvm: drop reference to KVM_CAP_PCI_2_3
kvm: require KVM_IRQFD for kernel irqchip
kvm: require KVM_IRQFD for kernel irqchip
kvm: require KVM_CAP_SIGNAL_MSI
kvm: require KVM_CAP_INTERNAL_ERROR_DATA
kvm: remove unnecessary stub
target/i386: check CPUID_PAE to determine 36 bit processor address space
target/i386: validate VEX.W for AVX instructions
target/i386: group common checks in the decoding phase
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Fri, 27 Oct 2023 00:42:21 +0000 (09:42 +0900)]
Merge tag 'pull-aspeed-
20231025' of https://github.com/legoater/qemu into staging
aspeed queue:
* Update of Andrew's email
* Split of AspeedSoCState per 2400/2600/10x0
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# jWQbbcapdaHW2ITWGhox9P4lBEgu6UT2X+rHt5yob1DPLPw7L60=
# =NICz
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 25 Oct 2023 17:54:45 JST
# gpg: using RSA key
A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [unknown]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-
20231025' of https://github.com/legoater/qemu:
hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState
hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState
hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState
hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize
hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC
hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC
hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC
hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field
hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific
hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific
hw/arm/aspeed: Extract code common to all boards to a common file
MAINTAINERS: aspeed: Update Andrew's email address
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 12:29:03 +0000 (14:29 +0200)]
kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 12:30:44 +0000 (14:30 +0200)]
kvm: i386: require KVM_CAP_SET_IDENTITY_MAP_ADDR
This was introduced in KVM in Linux 2.6.32, we can require it unconditionally.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 12:30:44 +0000 (14:30 +0200)]
kvm: i386: require KVM_CAP_ADJUST_CLOCK
This was introduced in KVM in Linux 2.6.33, we can require it
unconditionally. KVM_CLOCK_TSC_STABLE was only added in Linux 4.9,
for now do not require it (though it would allow the removal of some
pretty yucky code).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 12:30:44 +0000 (14:30 +0200)]
kvm: i386: require KVM_CAP_MCE
This was introduced in KVM in Linux 2.6.34, we can require it unconditionally.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 12:16:58 +0000 (14:16 +0200)]
kvm: i386: require KVM_CAP_SET_VCPU_EVENTS and KVM_CAP_X86_ROBUST_SINGLESTEP
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 11:18:15 +0000 (13:18 +0200)]
kvm: i386: require KVM_CAP_XSAVE
This was introduced in KVM in Linux 2.6.36, and could already be used at
the time to save/restore FPU data even on older processor. We can require
it unconditionally and stop using KVM_GET/SET_FPU.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 11:15:11 +0000 (13:15 +0200)]
kvm: i386: require KVM_CAP_DEBUGREGS
This was introduced in KVM in Linux 2.6.35, we can require it unconditionally.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 12:15:29 +0000 (14:15 +0200)]
kvm: i386: move KVM_CAP_IRQ_ROUTING detection to kvm_arch_required_capabilities
Simple code cleanup.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 11:47:21 +0000 (13:47 +0200)]
kvm: unify listeners for PIO address space
Since we now assume that ioeventfds are present, kvm_io_listener is always
registered. Merge it with kvm_coalesced_pio_listener in a single
listener. Since PIO space does not have KVM memslots attached to it,
the priority is irrelevant.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 12:13:04 +0000 (14:13 +0200)]
kvm: require KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH
KVM_CAP_IOEVENTFD_ANY_LENGTH was added in Linux 4.4, released in 2016.
Assume that it is present.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 12:08:22 +0000 (14:08 +0200)]
kvm: assume that many ioeventfds can be created
NR_IOBUS_DEVS was increased to 200 in Linux 2.6.34. By Linux 3.5 it had
increased to 1000 and later ioeventfds were changed to not count against
the limit. But the earlier limit of 200 would already be enough for
kvm_check_many_ioeventfds() to be true, so remove the check.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Wed, 18 Oct 2023 10:11:34 +0000 (12:11 +0200)]
kvm: drop reference to KVM_CAP_PCI_2_3
This is a remnant of pre-VFIO device assignment; it is not defined
anymore by Linux and not used by QEMU.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Sat, 21 Oct 2023 15:09:46 +0000 (17:09 +0200)]
kvm: require KVM_IRQFD for kernel irqchip
KVM_IRQFD was introduced in Linux 2.6.32, and since then it has always been
available on architectures that support an in-kernel interrupt controller.
We can require it unconditionally.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 11:34:50 +0000 (13:34 +0200)]
kvm: require KVM_IRQFD for kernel irqchip
KVM_IRQFD was introduced in Linux 2.6.32, and since then it has always been
available on architectures that support an in-kernel interrupt controller.
We can require it unconditionally.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 11:24:33 +0000 (13:24 +0200)]
kvm: require KVM_CAP_SIGNAL_MSI
This was introduced in KVM in Linux 3.5, we can require it unconditionally
in kvm_irqchip_send_msi(). However, not all architectures have to implement
it so check it only in x86, the only architecture that ever had MSI injection
but not KVM_CAP_SIGNAL_MSI.
ARM uses it to detect the presence of the ITS emulation in the kernel,
introduced in Linux 4.8. Assume that it's there and possibly fail when
realizing the arm-its-kvm device.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 17 Oct 2023 11:51:30 +0000 (13:51 +0200)]
kvm: require KVM_CAP_INTERNAL_ERROR_DATA
This was introduced in KVM in Linux 2.6.33, we can require it unconditionally.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Wed, 18 Oct 2023 09:15:09 +0000 (11:15 +0200)]
kvm: remove unnecessary stub
This function is only invoked from hw/intc/s390_flic_kvm.c, and therefore
only if CONFIG_KVM is defined.
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Ani Sinha [Tue, 12 Sep 2023 12:06:50 +0000 (17:36 +0530)]
target/i386: check CPUID_PAE to determine 36 bit processor address space
PAE mode in x86 supports 36 bit address space. Check the PAE CPUID on the
guest processor and set phys_bits to 36 if PAE feature is set. This is in
addition to checking the presence of PSE36 CPUID feature for setting 36 bit
phys_bits.
Signed-off-by: Ani Sinha <anisinha@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-ID: <
20230912120650.371781-1-anisinha@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Mon, 9 Oct 2023 16:16:27 +0000 (18:16 +0200)]
target/i386: validate VEX.W for AVX instructions
Instructions in VEX exception class 6 generally look at the value of
VEX.W. Note that the manual places some instructions incorrectly in
class 4, for example VPERMQ which has no non-VEX encoding and no legacy
SSE analogue. AMD does a mess of its own, as documented in the comment
that this patch adds.
Most of them are checked for VEX.W=0, and are listed in the manual
(though with an omission) in table 2-16; VPERMQ and VPERMPD check for
VEX.W=1, which is only listed in the instruction description. Others,
such as VPSRLV, VPSLLV and the FMA3 instructions, use VEX.W to switch
between a 32-bit and 64-bit operation.
Fix more of the class 4/class 6 mismatches, and implement the check for
VEX.W in TCG.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Mon, 9 Oct 2023 15:43:12 +0000 (17:43 +0200)]
target/i386: group common checks in the decoding phase
In preparation for adding more similar checks, move the VEX.L=0 check
and several X86_SPECIAL_* checks to a new field, where each bit represent
a common check on unused bits, or a restriction on the processor mode.
Likewise, many SVM intercepts can be checked during the decoding phase,
the main exception being the selective CR0 write, MSR and IOIO intercepts.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 10 Oct 2023 08:35:45 +0000 (10:35 +0200)]
tests/tcg/i386: test-avx: add test cases for SHA new instructions
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Wed, 11 Oct 2023 08:07:27 +0000 (10:07 +0200)]
tests/tcg/i386: initialize more registers in test-avx
Some instructions use YMM0 implicitly, or use YMM9 as a read-modify-write
register destination. Initialize those registers as well.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Tue, 10 Oct 2023 08:31:17 +0000 (10:31 +0200)]
target/i386: implement SHA instructions
The implementation was validated with OpenSSL and with the test vectors in
https://github.com/rust-lang/stdarch/blob/master/crates/core_arch/src/x86/sha.rs.
The instructions provide a ~25% improvement on hashing a 64 MiB file:
runtime goes down from 1.8 seconds to 1.4 seconds; instruction count on
the host goes down from 5.8 billion to 4.8 billion with slightly better
IPC too. Good job Intel. ;)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Paolo Bonzini [Thu, 19 Oct 2023 22:51:34 +0000 (00:51 +0200)]
tests/tcg: fix out-of-bounds access in test-avx
This can cause differences between native and QEMU execution, due
to ASLR.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Richard Henderson [Thu, 12 Oct 2023 04:52:20 +0000 (21:52 -0700)]
target/sparc: Remove disas_sparc_legacy
All instructions are now converted.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 04:50:11 +0000 (21:50 -0700)]
target/sparc: Convert FZERO, FONE to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 04:36:35 +0000 (21:36 -0700)]
target/sparc: Move FPACK16, FPACKFIX to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 04:26:06 +0000 (21:26 -0700)]
target/sparc: Move FPCMP* to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 04:11:49 +0000 (21:11 -0700)]
target/sparc: Convert FCMP, FCMPE to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 01:04:56 +0000 (18:04 -0700)]
target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 00:32:24 +0000 (17:32 -0700)]
target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 00:20:04 +0000 (17:20 -0700)]
target/sparc: Move FdTOq, FxTOq to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 00:12:24 +0000 (17:12 -0700)]
target/sparc: Move FiTOq, FsTOq to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 12 Oct 2023 00:00:34 +0000 (17:00 -0700)]
target/sparc: Move FqTOd, FqTOx to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 11 Oct 2023 23:47:14 +0000 (16:47 -0700)]
target/sparc: Move FqTOs, FqTOi to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 11 Oct 2023 23:40:16 +0000 (16:40 -0700)]
target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
Note that gen_ne_fop_DF was incorrectly named and does pass env.
The two sets of helpers should have been unified.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 11 Oct 2023 23:29:46 +0000 (16:29 -0700)]
target/sparc: Move gen_fop_FD insns to decodetree
Move FdTOs, FdTOi, FxTOs.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 11 Oct 2023 23:16:54 +0000 (16:16 -0700)]
target/sparc: Move FDMULQ to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 11 Oct 2023 23:05:13 +0000 (16:05 -0700)]
target/sparc: Move FSMULD to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 11 Oct 2023 22:59:28 +0000 (15:59 -0700)]
target/sparc: Move gen_fop_QQQ insns to decodetree
Move FADDq, FSUBq, FMULq, FDIVq.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 11 Oct 2023 22:51:13 +0000 (15:51 -0700)]
target/sparc: Move gen_fop_DDD insns to decodetree
Move FADDd, FSUBd, FMULd, FDIVd.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Wed, 11 Oct 2023 22:43:18 +0000 (15:43 -0700)]
target/sparc: Move gen_fop_FFF insns to decodetree
Move FADDs, FSUBs, FMULs, FDIVs.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 10 Oct 2023 22:07:48 +0000 (15:07 -0700)]
target/sparc: Move FSQRTq to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 10 Oct 2023 21:56:49 +0000 (14:56 -0700)]
target/sparc: Move gen_fop_DD insns to decodetree
Move FSQRTd, FxTOd, FdTOx.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 10 Oct 2023 21:44:32 +0000 (14:44 -0700)]
target/sparc: Move gen_fop_FF insns to decodetree
Move FSQRTs, FiTOs, FsTOi.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 10 Oct 2023 21:25:47 +0000 (14:25 -0700)]
target/sparc: Move gen_gsr_fop_DDD insns to decodetree
Move FPACK32, FALIGNDATA, BSHUFFLE.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 10 Oct 2023 21:05:16 +0000 (14:05 -0700)]
target/sparc: Move PDIST to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 10 Oct 2023 20:50:38 +0000 (13:50 -0700)]
target/sparc: Move gen_ne_fop_DDD insns to decodetree
Move FMUL8x16, FMUL8x16AU, FMUL8x16AL, FMUL8SUx16, FMUL8ULx16,
FMULD8SUx16, FMULD8ULx16, FPMERGE, FEXPAND, FANDNOT1d, FANDNOT2d,
FANDd, FNANDd, FNORd, FORNOT1d, FORNOT2d, FORd, FPADD16d, FPADD32d,
FPSUB16d, FPSUB32d, FXNORd, FXORd.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 10 Oct 2023 19:58:14 +0000 (12:58 -0700)]
target/sparc: Move gen_ne_fop_FFF insns to decodetree
Move FANDNOT1s, FANDNOT2s, FANDs, FNANDs, FNORs, FORNOT1s, FORNOT2s,
FORs, FPADD16s, FPADD32s, FPSUB16s, FPSUB32s, FXNORs, FXORs.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 10 Oct 2023 17:48:56 +0000 (10:48 -0700)]
target/sparc: Use tcg_gen_vec_{add,sub}*
Replace the local helpers for the same integer operations.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 17:53:30 +0000 (10:53 -0700)]
target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 16:41:05 +0000 (09:41 -0700)]
target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 16:01:34 +0000 (09:01 -0700)]
target/sparc: Move BMASK to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 15:55:50 +0000 (08:55 -0700)]
target/sparc: Move ADDRALIGN* to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 10:26:54 +0000 (03:26 -0700)]
target/sparc: Move ARRAY* to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 10:12:12 +0000 (03:12 -0700)]
target/sparc: Move EDGE* to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 09:31:25 +0000 (02:31 -0700)]
target/sparc: Merge LDFSR, LDXFSR implementations
Combine the helper to a single set_fsr().
Perform the mask and merge inline.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 09:12:59 +0000 (02:12 -0700)]
target/sparc: Move LDFSR, STFSR to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 08:56:02 +0000 (01:56 -0700)]
target/sparc: Move asi fp load/store to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 08:38:50 +0000 (01:38 -0700)]
target/sparc: Move simple fp load/store to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 08:37:06 +0000 (01:37 -0700)]
target/sparc: Split out fp ldst functions with asi precomputed
Take the operation size from the MemOp instead of a
separate parameter.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 5 Oct 2023 07:20:37 +0000 (00:20 -0700)]
target/sparc: Move PREFETCH, PREFETCHA to decodetree
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>