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Juergen Ributzka [Wed, 11 Jun 2014 23:11:02 +0000 (23:11 +0000)]
[FastISel][X86] Add support for the sqrt intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210720
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Juergen Ributzka [Wed, 11 Jun 2014 23:10:58 +0000 (23:10 +0000)]
[FastIsel][X86] Add support for lowering the first 8 floating-point arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210719
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Zachary Turner [Wed, 11 Jun 2014 23:03:31 +0000 (23:03 +0000)]
Don't acquire the mutex during the destructor of PassRegistry.
This destructor is run as part of static program termination, and
so all ManagedStatics (including this lock) will have been
destroyed by llvm_shutdown. Furthermore, if there is actually
a race condition during static program termination, then we are
just hiding a bug somewhere else, because other threads should
not be running at this point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210717
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Rafael Espindola [Wed, 11 Jun 2014 22:53:00 +0000 (22:53 +0000)]
Implement get_magic with generic tools and inline it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210716
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Rafael Espindola [Wed, 11 Jun 2014 21:53:22 +0000 (21:53 +0000)]
Remove unused has_magic.
This will allow inlining get_magic, which should in turn fix one of the mingw
build problems after the switch to std::error_code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210712
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Juergen Ributzka [Wed, 11 Jun 2014 21:44:44 +0000 (21:44 +0000)]
[FastISel][X86] Add support for the frameaddress intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210709
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Chad Rosier [Wed, 11 Jun 2014 21:06:56 +0000 (21:06 +0000)]
[AArch64] Basic Sched Model for Cortex-A57.
Patch by Dave Estes<cestes@codeaurora.org>
Differential Revision: http://reviews.llvm.org/D4008
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210705
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Tom Stellard [Wed, 11 Jun 2014 20:51:42 +0000 (20:51 +0000)]
R600: Set correct InstrItinClass for instructions using *Helper classes
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.
This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210703
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Tom Stellard [Wed, 11 Jun 2014 20:51:39 +0000 (20:51 +0000)]
R600: BCNT_INT is a vector only instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210702
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Jim Grosbach [Wed, 11 Jun 2014 20:26:45 +0000 (20:26 +0000)]
ARM: honor hex immediate formatting for ldr/str i12 offsets.
Previously we would always print the offset as decimal, regardless of
the formatting requested. Now we use the formatImm() helper so the value
is printed as the client (LLDB in the motivating example) requested.
Before:
ldr.w r8, [sp, #180] @ always
After:
ldr.w r8, [sp, #0xb4] @ when printing hex immediates
ldr.w r8, [sp, #0180] @ when printing decimal immediates
rdar://
17237103
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210701
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Jim Grosbach [Wed, 11 Jun 2014 20:26:40 +0000 (20:26 +0000)]
llvm-mc: Add option for prefering hex format disassembly.
Previously there was a separate mode entirely (--hdis vs.
--disassemble). It makes a bit more sense for the immediate printing
style to be a flag for --disassmeble rather than an entirely different
thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210700
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Matt Arsenault [Wed, 11 Jun 2014 19:31:13 +0000 (19:31 +0000)]
R600/SI: Fix bitcast between v2i32 and f64
This is the same problem fixed in r210664 for more types.
The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210692
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Rafael Espindola [Wed, 11 Jun 2014 19:05:50 +0000 (19:05 +0000)]
Use std::error_code instead of llvm::error_code.
The idea of this patch is to turn llvm/Support/system_error.h into a
transitional header that just brings in the erorr_code api to the llvm
namespace. I will remove it shortly afterwards.
The cases where the general idea needed some tweaking:
* std::errc is a namespace in msvc, so we cannot use "using std::errc". I could
add an #ifdef, but there were not that many uses, so I just added std:: to
them in this patch.
* Template specialization had to be moved to the std namespace in this
patch set already.
* The msvc implementation of default_error_condition doesn't seem to
provide the same transformations as we need. Not too surprising since
the standard doesn't actually say what "equivalent" means. I fixed the
problem by keeping our old mapping and using it at error_code
construction time.
Despite these shortcomings I think this is still a good thing. Some reasons:
* The different implementations of system_error might improve over time.
* It removes 925 lines of code from llvm already.
* It removes 6313 bytes from the text segment of the clang binary when
it is built with gcc and 2816 bytes when building with clang and
libstdc++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210687
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Chad Rosier [Wed, 11 Jun 2014 18:28:45 +0000 (18:28 +0000)]
[Reassociate] FileCheckize and cleanup a few testcases. No functional change
intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210685
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Chad Rosier [Wed, 11 Jun 2014 18:26:29 +0000 (18:26 +0000)]
Fix assert comments in Instruction.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210684
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Matt Arsenault [Wed, 11 Jun 2014 18:11:34 +0000 (18:11 +0000)]
R600/SI: Update place using old subtarget predicate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210683
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Matt Arsenault [Wed, 11 Jun 2014 18:08:54 +0000 (18:08 +0000)]
R600/SI: Add common 64-bit LDS atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210680
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Matt Arsenault [Wed, 11 Jun 2014 18:08:50 +0000 (18:08 +0000)]
R600/SI: Add instruction definitions for 64-bit LDS atomics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210679
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Matt Arsenault [Wed, 11 Jun 2014 18:08:48 +0000 (18:08 +0000)]
R600/SI: Add 32-bit LDS atomic cmpxchg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210678
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Matt Arsenault [Wed, 11 Jun 2014 18:08:45 +0000 (18:08 +0000)]
R600/SI: Use LDS atomic inc / dec
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210677
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Matt Arsenault [Wed, 11 Jun 2014 18:08:42 +0000 (18:08 +0000)]
R600/SI: Add other LDS atomic operations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210676
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Matt Arsenault [Wed, 11 Jun 2014 18:08:39 +0000 (18:08 +0000)]
R600/SI: Add instruction definitions for more LDS ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210675
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Matt Arsenault [Wed, 11 Jun 2014 18:08:37 +0000 (18:08 +0000)]
R600/SI: Fix backwards names for local atomic instructions.
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210674
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Matt Arsenault [Wed, 11 Jun 2014 18:08:34 +0000 (18:08 +0000)]
R600/SI: Refactor local atomics.
Use patterns that will also match the immediate offset to
match the normal read / writes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210673
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Matt Arsenault [Wed, 11 Jun 2014 17:50:44 +0000 (17:50 +0000)]
R600/SI: Use v_cvt_f32_ubyte* instructions
This eliminates extra extract instructions when loading an i8 vector to
a float vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210666
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David Blaikie [Wed, 11 Jun 2014 17:50:14 +0000 (17:50 +0000)]
SmallVectorTest: Make the deleted member functions private to help MSVC users.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210665
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Matt Arsenault [Wed, 11 Jun 2014 17:40:32 +0000 (17:40 +0000)]
R600/SI: Fix selection failure on scalar_to_vector
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.
Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210664
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Tim Northover [Wed, 11 Jun 2014 17:04:08 +0000 (17:04 +0000)]
X86: add stringy name for X86ISD::LCMPXCHG16_DAG
I don't know what "target specific node #383" is, and I don't want to
have to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210663
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Eric Christopher [Wed, 11 Jun 2014 16:59:33 +0000 (16:59 +0000)]
Revert r210613 to conform to coding standards.
Thanks Duncan for noticing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210662
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Daniel Sanders [Wed, 11 Jun 2014 15:48:00 +0000 (15:48 +0000)]
[mips][mips64r6] Improve tests affected by the changes to multiplies and divides
Summary:
MIPS32r6/MIPS64r6 support has not been added yet.
inlineasm-cnstrnt-reg.ll:
Explicitly specify the CPU since it will not work on MIPS32r6/MIPS64r6
when -integrated-as is the default. We can't change the mnemonic since the
LO register is an implicit def of mtlo and MIPS32r6/MIPS64r6 has no
instructions that use LO.
2008-08-01-AsmInline.ll:
Explicitly specify the CPU since MIPS32r6/MIPS64r6 will correctly emit
different code and this is a regression test.
mips64instrs.ll and mips64muldiv.ll
Check registers and the way the multiply is used in m1
divrem.ll
Check registers and use multiple filecheck prefixes to limit redundancy
Reviewers: vmedic, jkolek, zoran.jovanovic, matheusalmeida
Reviewed By: matheusalmeida
Subscribers: matheusalmeida
Differential Revision: http://reviews.llvm.org/D3894
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210656
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Matheus Almeida [Wed, 11 Jun 2014 15:05:56 +0000 (15:05 +0000)]
[mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier).
Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format.
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D4019
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210654
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Cameron McInally [Wed, 11 Jun 2014 12:54:45 +0000 (12:54 +0000)]
Add AVX512 masked leadz instrinsic support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210652
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Evgeniy Stepanov [Wed, 11 Jun 2014 08:46:45 +0000 (08:46 +0000)]
Improve the test for inlining of __no_debug__ functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210645
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Andrea Di Biagio [Wed, 11 Jun 2014 07:57:50 +0000 (07:57 +0000)]
[X86] Refactor the logic to select horizontal adds/subs to a helper function.
This patch moves part of the logic implemented by the target specific
combine rules added at r210477 to a separate helper function.
This should make easier to add more rules for matching AVX/AVX2 horizontal
adds/subs.
This patch also fixes a problem caused by a wrong check performed on indices
of extract_vector_elt dag nodes in input to the scalar adds/subs.
New tests have been added to verify that we correctly check indices of
extract_vector_elt dag nodes when selecting a horizontal operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210644
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Jiangning Liu [Wed, 11 Jun 2014 07:04:37 +0000 (07:04 +0000)]
Create macro INITIALIZE_TM_PASS.
Pass initialization requires to initialize TargetMachine for back-end
specific passes. This commit creates a new macro INITIALIZE_TM_PASS to
simplify this kind of initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210641
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Jiangning Liu [Wed, 11 Jun 2014 06:44:53 +0000 (06:44 +0000)]
Global merge for global symbols.
This commit is to improve global merge pass and support global symbol merge.
The global symbol merge is not enabled by default. For aarch64, we need some
more back-end fix to make it really benifit ADRP CSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210640
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Jiangning Liu [Wed, 11 Jun 2014 06:35:26 +0000 (06:35 +0000)]
Rename global-merge to enable-global-merge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210639
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Craig Topper [Wed, 11 Jun 2014 05:35:56 +0000 (05:35 +0000)]
Convert StringMapEntry::Create to use StringRef instead of start/end pointers. Simpliies all in tree call sites. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210638
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Rafael Espindola [Wed, 11 Jun 2014 04:41:37 +0000 (04:41 +0000)]
Try to fix the msvc build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210636
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Rafael Espindola [Wed, 11 Jun 2014 04:34:41 +0000 (04:34 +0000)]
Uses generic_category instead of system_category.
Some c++ libraries (libstdc++ at least) don't seem to map to the generic
category in in the system_category's default_error_condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210635
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Saleem Abdulrasool [Wed, 11 Jun 2014 04:19:25 +0000 (04:19 +0000)]
MC: add enumeration of WinEH data encoding
Most Windows platforms use auxiliary data for unwinding. This information is
stored in the .pdata section. The encoding format for the data differs between
architectures and Windows variants. Windows MIPS and Alpha use identical
formats; Alpha64 is the same with different widths. Windows x86_64 and Itanium
share the representation. All Windows CE entries are identical irrespective of
the architecture. ARMv7 (Windows [NT] on ARM) has its own format.
This enumeration will become the differentiator once the windows EH emission
infrastructure is generalised, allowing us to emit the necessary unwinding
information for Windows on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210634
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Saleem Abdulrasool [Wed, 11 Jun 2014 04:19:19 +0000 (04:19 +0000)]
MC: clang-format MCAsmInfo
Apply clang-format over the header. Reformat the docs to current LLVM style.
NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210633
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Rafael Espindola [Wed, 11 Jun 2014 03:58:34 +0000 (03:58 +0000)]
Remove windows_error.
MSVC doesn't seem to provide any is_error_code_enum enumeration for the
windows errors.
Fortunately very few places in llvm have to handle raw windows errors, so
we can just construct the corresponding error_code directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210631
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Rafael Espindola [Wed, 11 Jun 2014 03:49:13 +0000 (03:49 +0000)]
There is no posix_category in std, use generic_category.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210630
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Matt Arsenault [Wed, 11 Jun 2014 03:30:06 +0000 (03:30 +0000)]
Use cast instead of assert + dyn_cast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210628
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Matt Arsenault [Wed, 11 Jun 2014 03:29:54 +0000 (03:29 +0000)]
R600: Add helper functions.
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210627
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Rafael Espindola [Wed, 11 Jun 2014 01:22:20 +0000 (01:22 +0000)]
Use an enum class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210623
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Saleem Abdulrasool [Wed, 11 Jun 2014 01:19:03 +0000 (01:19 +0000)]
CodeGen: refactor DwarfException
DwarfException served as a base class for exception handling directive emission.
However, this is also used by other exception models (e.g. Win64EH). Rename
this class to EHStreamer and split it out of DwarfException.h. NFC.
Use the opportunity to fix up some of the documentation comments to match
current LLVM style. Also rename some functions to conform better with current
LLVM coding style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210622
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Rafael Espindola [Wed, 11 Jun 2014 01:09:09 +0000 (01:09 +0000)]
Use an enum class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210620
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Eric Christopher [Wed, 11 Jun 2014 00:53:17 +0000 (00:53 +0000)]
Remove duplicate copy of InstrItineraryData from the TargetMachine,
it's already on the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210619
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Eric Christopher [Wed, 11 Jun 2014 00:46:34 +0000 (00:46 +0000)]
Move to a private function to initialize the subtarget dependencies
so that we can use initializer lists for the AArch64 Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210616
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Eric Christopher [Wed, 11 Jun 2014 00:25:19 +0000 (00:25 +0000)]
Move to a private function to initialize the subtarget dependencies
so that we can use initializer lists for the X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210614
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Eric Christopher [Wed, 11 Jun 2014 00:25:16 +0000 (00:25 +0000)]
Sort includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210613
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Juergen Ributzka [Tue, 10 Jun 2014 23:52:44 +0000 (23:52 +0000)]
[FastISel][X86] Extend support for {s|u}{add|sub|mul}.with.overflow intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210610
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Eric Christopher [Tue, 10 Jun 2014 23:26:47 +0000 (23:26 +0000)]
Use unique_ptr for X86Subtarget pointer members.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210606
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Eric Christopher [Tue, 10 Jun 2014 23:26:45 +0000 (23:26 +0000)]
Move AArch64TargetLowering to AArch64Subtarget.
This currently necessitates a TargetMachine for the TargetLowering
constructor and TLOF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210605
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Zachary Turner [Tue, 10 Jun 2014 23:15:43 +0000 (23:15 +0000)]
Revert "Remove support for runtime multi-threading."
This reverts revision r210600.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210603
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Zachary Turner [Tue, 10 Jun 2014 23:01:20 +0000 (23:01 +0000)]
Remove support for runtime multi-threading.
This patch removes the functions llvm_start_multithreaded() and
llvm_stop_multithreaded(), and changes llvm_is_multithreaded()
to return a constant value based on the value of the compile-time
definition LLVM_ENABLE_THREADS.
Previously, it was possible to have compile-time support for
threads on, and runtime support for threads off, in which case
certain mutexes were not allocated or ever acquired. Now, if the
build is created with threads enabled, mutexes are always acquired.
A test before/after patch of compiling a very large TU showed no
noticeable performance impact of this change.
Reviewers: rnk
Differential Revision: http://reviews.llvm.org/D4076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210600
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Eric Christopher [Tue, 10 Jun 2014 22:57:25 +0000 (22:57 +0000)]
Move AArch64InstrInfo to AArch64Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210599
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Eric Christopher [Tue, 10 Jun 2014 22:57:21 +0000 (22:57 +0000)]
Remove a method that was just replacing direct access to a member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210598
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Hans Wennborg [Tue, 10 Jun 2014 22:51:58 +0000 (22:51 +0000)]
lit: warn when passed invalid pathname
It would previously say things like
warning: input 'test/Frontend/foo.c' contained no tests
and have the user pull their hair trying to figure out what's wrong with that
file. This patch changes the message to the much clearer:
warning: no such file or directory: 'test/Frontend/foo.c'
Differential Revision: http://reviews.llvm.org/D4097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210597
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Eric Christopher [Tue, 10 Jun 2014 22:34:31 +0000 (22:34 +0000)]
Remove the use of TargetMachine from X86InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210596
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Eric Christopher [Tue, 10 Jun 2014 22:34:28 +0000 (22:34 +0000)]
Move X86RegisterInfo away from using the TargetMachine and only
using the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210595
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Rafael Espindola [Tue, 10 Jun 2014 21:26:47 +0000 (21:26 +0000)]
Mark a few functions noexcept.
This reduces the difference between std::error_code and llvm::error_code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210591
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Eric Christopher [Tue, 10 Jun 2014 21:25:13 +0000 (21:25 +0000)]
Use the TargetMachine on the DAG or the MachineFunction instead
of using the cached TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210589
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Tom Stellard [Tue, 10 Jun 2014 21:20:41 +0000 (21:20 +0000)]
R600/SI: Emit an error when attempting to spill VGPRs v4
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.
v2:
- Fix build
v3:
- Added crash fix when spilling SPGRs
v4:
- Use V_MOV_B32 as a dummy instruction instead of S_NOP
Patch by: Darren Powell
https://bugs.freedesktop.org/show_bug.cgi?id=75276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210588
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Tom Stellard [Tue, 10 Jun 2014 21:20:38 +0000 (21:20 +0000)]
R600/SI: Fix a crash when spilling SGPRs
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.
This fixes a crash in the game Antichamber.
https://bugs.freedesktop.org/show_bug.cgi?id=75276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587
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Rafael Espindola [Tue, 10 Jun 2014 20:45:52 +0000 (20:45 +0000)]
Add a LLVM_NOEXCEPT to Compiler.h.
This will be needed for the switch to std::error_code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210581
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Eric Christopher [Tue, 10 Jun 2014 20:39:39 +0000 (20:39 +0000)]
We already have a reference to the TargetMachine, use that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210580
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Eric Christopher [Tue, 10 Jun 2014 20:39:38 +0000 (20:39 +0000)]
Have isInTailCallPosition take the DAG so that we can use the
version of TargetLowering/Machine from there on the way to avoiding
TargetMachine in TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210579
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Eric Christopher [Tue, 10 Jun 2014 20:39:35 +0000 (20:39 +0000)]
Reorder includes to be sorted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210578
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Reid Kleckner [Tue, 10 Jun 2014 20:16:47 +0000 (20:16 +0000)]
Rearrange the CHECK lines in this test to make failure more obvious.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210575
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Reid Kleckner [Tue, 10 Jun 2014 20:16:36 +0000 (20:16 +0000)]
Revert "Patch by Ray Donnelly to print register names instead of numbers."
This reverts commit r206683.
The code was confusing SEH register numbers with DWARF register numbers.
The test case it was committed with was obviously incorrect. The
disassembler was roundtripping '.seh_pushreg %rsi' as '.seh_pushreg
%rbp', and other exciting things.
Noticed by Vadim Chugunov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210574
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Matt Arsenault [Tue, 10 Jun 2014 20:10:08 +0000 (20:10 +0000)]
Fix error in tablegen when either operand of !if is an empty list.
!if([Something], []) would error with "No type for list".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210572
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Eric Christopher [Tue, 10 Jun 2014 20:07:29 +0000 (20:07 +0000)]
Fix typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210571
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Matt Arsenault [Tue, 10 Jun 2014 19:18:28 +0000 (19:18 +0000)]
R600: Use BCNT_INT for evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569
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Matt Arsenault [Tue, 10 Jun 2014 19:18:24 +0000 (19:18 +0000)]
R600/SI: Implement i64 ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568
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Matt Arsenault [Tue, 10 Jun 2014 19:18:21 +0000 (19:18 +0000)]
R600/SI: Use bcnt instruction for ctpop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567
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Rafael Espindola [Tue, 10 Jun 2014 19:08:21 +0000 (19:08 +0000)]
Use an enum class now that they are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210566
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Matt Arsenault [Tue, 10 Jun 2014 19:00:20 +0000 (19:00 +0000)]
R600: Handle fcopysign
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564
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Matt Arsenault [Tue, 10 Jun 2014 18:54:59 +0000 (18:54 +0000)]
R600/SI: Handle sign_extend and zero_extend to i64 with patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563
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Eric Christopher [Tue, 10 Jun 2014 18:31:18 +0000 (18:31 +0000)]
Add a FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210559
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Eric Christopher [Tue, 10 Jun 2014 18:21:53 +0000 (18:21 +0000)]
Move AArch64SelectionDAGInfo down to the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210557
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Juergen Ributzka [Tue, 10 Jun 2014 18:17:00 +0000 (18:17 +0000)]
[FastISel] Collect statistics about failing intrinsic calls.
Add more instruction-specific statistics about failing intrinsic calls during
FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210556
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Eric Christopher [Tue, 10 Jun 2014 18:11:20 +0000 (18:11 +0000)]
Remove the cached little endian variable. We can get it easily off
of the DataLayout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210555
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Eric Christopher [Tue, 10 Jun 2014 18:06:28 +0000 (18:06 +0000)]
Have AArch64SelectionDAGInfo take a DataLayout parameter rather
than a TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210554
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Eric Christopher [Tue, 10 Jun 2014 18:06:25 +0000 (18:06 +0000)]
Remove caching of the subtarget for AArch64SelectionDAGInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210553
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Eric Christopher [Tue, 10 Jun 2014 18:06:23 +0000 (18:06 +0000)]
Move DataLayout onto the AArch64 subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210552
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Zachary Turner [Tue, 10 Jun 2014 18:03:04 +0000 (18:03 +0000)]
Test commit, wraps some lines to fit in 80 columns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210551
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Eric Christopher [Tue, 10 Jun 2014 17:44:12 +0000 (17:44 +0000)]
Move AArch64FrameLowering into the subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210549
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Eric Christopher [Tue, 10 Jun 2014 17:33:39 +0000 (17:33 +0000)]
Remove the uses of AArch64TargetMachine and AArch64Subtarget from
AArch64FrameLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210548
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Reed Kotler [Tue, 10 Jun 2014 16:45:44 +0000 (16:45 +0000)]
Do Materialize Floating Point in Mips Fast-Isel
Summary:
Implement materialize of floating point literals in Mips Fast-Isel
Reopened version of D3659
Test Plan: simplestorefp1.ll
Reviewers: dsanders
Reviewed By: dsanders
Differential Revision: http://reviews.llvm.org/D4071
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210546
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Andrea Di Biagio [Tue, 10 Jun 2014 16:42:57 +0000 (16:42 +0000)]
[X86] Improved target combine rules for selecting horizontal add/sub.
This patch slightly changes the algorithm introduced at revision 210477
to fix a problem where the algorithm was producing incorrect code for
the VEX.256 encoded versions of horizontal add/sub.
For these cases, we now try to split the two 256-bit vectors into
128-bit chunks before emitting horizontal add/sub dag nodes.
Added a new test case into haddsub-2.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210545
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Tom Stellard [Tue, 10 Jun 2014 16:42:41 +0000 (16:42 +0000)]
Hexagon: Expand i1 SELECT_CC
il is legal for Hexagon, so I should have marked this as Expand for
SELECT_CC when I removed setOperationAction(ISD::SELECT_CC, MVT::Other,
Expand); in r210541.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210544
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Adam Nemet [Tue, 10 Jun 2014 16:39:53 +0000 (16:39 +0000)]
[X86] AVX512: Add vmovntdqa
Along with the corresponding intrinsic and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210543
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Renato Golin [Tue, 10 Jun 2014 16:39:21 +0000 (16:39 +0000)]
Fix a bug in the Thumb1 ARM Load/Store optimizer
Previously, the basic block was searched for future uses of the base register,
and if necessary any writeback to the base register was reset using a SUB
instruction (e.g. before calling a function) just before such a use. However,
this step happened *before* the merged LDM/STM instruction was built. So if
there was (e.g.) a function call directly after the not-yet-formed LDM/STM,
the pass would first insert a SUB instruction to reset the base register,
and then (at the same location, incorrectly) insert the LDM/STM itself.
This patch fixes PR19972. Patch by Moritz Roth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210542
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Tom Stellard [Tue, 10 Jun 2014 16:01:29 +0000 (16:01 +0000)]
SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC
The SelectionDAG bad a special case for ISD::SELECT_CC, where it would
allow targets to specify:
setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
to indicate that they wanted to expand ISD::SELECT_CC for all types.
This wasn't applied correctly everywhere, and it makes writing new
DAG patterns with ISD::SELECT_CC difficult.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210541
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Tom Stellard [Tue, 10 Jun 2014 16:01:25 +0000 (16:01 +0000)]
SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors
This prevents a future commit from regressing:
test/CodeGen/R600/setcc-equivalent.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210540
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Tom Stellard [Tue, 10 Jun 2014 16:01:22 +0000 (16:01 +0000)]
SelectionDAG: Expand SELECT_CC to SELECT + SETCC
This consolidates code from the Hexagon, R600, and XCore targets.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210539
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Bill Schmidt [Tue, 10 Jun 2014 14:35:01 +0000 (14:35 +0000)]
[PPC64LE] Recognize shufflevector patterns for little endian
Various masks on shufflevector instructions are recognizable as
specific PowerPC instructions (vector pack, vector merge, etc.).
There is existing code in PPCISelLowering.cpp to recognize the correct
patterns for big endian code. The masks for these instructions are
different for little endian code due to the big-endian numbering
employed by these instructions. This patch adds the recognition code
for little endian.
I've added a new test case test/CodeGen/PowerPC/vec_shuffle_le.ll for
this. The existing recognizer test (vec_shuffle.ll) is unnecessarily
verbose and difficult to read, so I felt it was better to add a new
test rather than modify the old one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210536
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