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Dean Michael Berris [Mon, 9 Apr 2018 04:02:09 +0000 (04:02 +0000)]
[XRay][llvm+clang] Consolidate attribute list files
Summary:
This change consolidates the always/never lists that may be provided to
clang to externally control which functions should be XRay instrumented
by imbuing attributes. The files follow the same format as defined in
https://clang.llvm.org/docs/SanitizerSpecialCaseList.html for the
sanitizer blacklist.
We also deprecate the existing `-fxray-instrument-always=` and
`-fxray-instrument-never=` flags, in favour of `-fxray-attr-list=`.
This fixes http://llvm.org/PR34721.
Reviewers: echristo, vlad.tsyrklevich, eugenis
Reviewed By: vlad.tsyrklevich
Subscribers: llvm-commits, cfe-commits
Differential Revision: https://reviews.llvm.org/D45357
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329543
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Michael Zolotukhin [Mon, 9 Apr 2018 00:54:47 +0000 (00:54 +0000)]
Remove MachineLoopInfo dependency from AsmPrinter.
Summary:
Currently MachineLoopInfo is used in only two places:
1) for computing IsBasicBlockInsideInnermostLoop field of MCCodePaddingContext, and it is never used.
2) in emitBasicBlockLoopComments, which is called only if `isVerbose()` is true.
Despite that, we currently have a dependency on MachineLoopInfo, which makes
pass manager to compute it and MachineDominator Tree. This patch removes the
use (1) and makes the use (2) lazy, thus avoiding some redundant
recomputations.
Reviewers: opaparo, gadi.haber, rafael, craig.topper, zvi
Subscribers: rengolin, javed.absar, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D44812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329542
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Sanjay Patel [Sun, 8 Apr 2018 19:56:04 +0000 (19:56 +0000)]
[TargetSchedule] shrink interface for init(); NFCI
The TargetSchedModel is always initialized using the TargetSubtargetInfo's
MCSchedModel and TargetInstrInfo, so we don't need to extract those and
pass 3 parameters to init().
Differential Revision: https://reviews.llvm.org/D44789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329540
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Craig Topper [Sun, 8 Apr 2018 17:53:18 +0000 (17:53 +0000)]
[X86] Add SchedWrites for CMOV and SETCC. Use them to remove InstRWs.
Summary:
Cmov and setcc previously used WriteALU, but on Intel processors at least they are more restricted than basic ALU ops.
This patch adds new SchedWrites for them and removes the InstRWs. I had to leave some InstRWs for CMOVA/CMOVBE and SETA/SETBE because those have an extra uop relative to the other condition codes on Intel CPUs.
The test changes are due to fixing a missing ZnAGU dependency on the memory form of setcc.
Reviewers: RKSimon, andreadb, GGanesh
Reviewed By: RKSimon
Subscribers: GGanesh, llvm-commits
Differential Revision: https://reviews.llvm.org/D45380
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329539
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Craig Topper [Sun, 8 Apr 2018 17:53:15 +0000 (17:53 +0000)]
[X86][Znver1] Remove InstRWs for BLENDVPS/PD
Summary:
This removes the InstRWs for BLENDVPS/PD in favor of WriteFVarBlend. The latency listed was 3 cycles but WriteFVarBlend is defined as 1 cycle latency. The 1 cycle latency matches Agner Fog's data.
The patterns were missing the VEX forms which is why there are no test changes. We don't test "-mcpu=znver1 -mattr=-avx"
Reviewers: RKSimon, GGanesh
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329538
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Jonas Devlieghere [Sun, 8 Apr 2018 17:35:17 +0000 (17:35 +0000)]
[dsymutil] Don't crash on empty CU
Add some additional checks so we don't crash on empty compile units.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329537
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Mandeep Singh Grang [Sun, 8 Apr 2018 16:46:22 +0000 (16:46 +0000)]
[Support] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: chandlerc, jordan_rose, bkramer
Reviewed By: bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329536
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Mandeep Singh Grang [Sun, 8 Apr 2018 16:45:04 +0000 (16:45 +0000)]
[PowerPC] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: hfinkel, RKSimon
Reviewed By: RKSimon
Subscribers: nemanjai, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D44870
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329535
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Mandeep Singh Grang [Sun, 8 Apr 2018 16:42:52 +0000 (16:42 +0000)]
[X86] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: chandlerc, craig.topper, RKSimon
Reviewed By: chandlerc, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329534
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Piotr Padlewski [Sun, 8 Apr 2018 16:04:09 +0000 (16:04 +0000)]
NFC: Update NewGVN invariant.group test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329533
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Andrea Di Biagio [Sun, 8 Apr 2018 15:10:19 +0000 (15:10 +0000)]
[llvm-mca] Simplify code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329532
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Piotr Padlewski [Sun, 8 Apr 2018 13:53:04 +0000 (13:53 +0000)]
Mark invariant.group as experimental
Differential Revision: https://reviews.llvm.org/D33235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329531
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Xin Tong [Sun, 8 Apr 2018 13:19:53 +0000 (13:19 +0000)]
[LIR] Reorder header. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329530
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Simon Pilgrim [Sun, 8 Apr 2018 12:31:52 +0000 (12:31 +0000)]
[X86] Regenerate and + immediate mask tests
Added i686 checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329529
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Simon Pilgrim [Sun, 8 Apr 2018 12:30:30 +0000 (12:30 +0000)]
[X86][PKU] Regenerate rdpkru/wrpkru intrinsic tests
Added i686 checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329528
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Simon Pilgrim [Sun, 8 Apr 2018 12:29:11 +0000 (12:29 +0000)]
[X86][SSE3] Regenerate mwait/monitor intrinsic tests
Added i686 checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329527
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Piotr Padlewski [Sun, 8 Apr 2018 12:23:58 +0000 (12:23 +0000)]
NFC: delete ValueMap move ctor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329526
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Zvi Rackover [Sun, 8 Apr 2018 11:35:20 +0000 (11:35 +0000)]
DAGCombiner: Combine SDIV with non-splat vector pow2 divisor
Summary:
Extend existing SDIV combine for pow2 constant divider to handle
non-splat vectors of pow2 constants.
Reviewers: RKSimon, craig.topper, spatel, hfinkel, efriedma
Reviewed By: RKSimon
Subscribers: magabari, llvm-commits
Differential Revision: https://reviews.llvm.org/D42479
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329525
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Simon Pilgrim [Sun, 8 Apr 2018 11:26:26 +0000 (11:26 +0000)]
[X86][Btver2] Add vector extract costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329524
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Eric Fiselier [Sun, 8 Apr 2018 08:48:58 +0000 (08:48 +0000)]
[ADT] Fix MapVector when 'Map::mapped_type != unsigned'.
Previously MapVector assumed `Map::mapped_type` was `unsigned`.
This caused problems when using MapVector with a user-specified
map where this didn't hold (For example StringMap<unsigned>).
This patch adjusts MapVector to use the same type as the underlying
map, avoiding reference binding errors in functions like `insert`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329523
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Michal Gorny [Sun, 8 Apr 2018 06:49:17 +0000 (06:49 +0000)]
[LLVMTestingSupport] Add explicit linkage to LLVMSupport
Explicitly link LLVMTestingSupport library against LLVMSupport. This
is necessary to fix linking errors when LLVMTestingSupport is built
as a shared library (with BUILD_SHARED_LIBS=ON) and -Wl,-z,defs is used.
Differential Revision: https://reviews.llvm.org/D45408
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329522
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Guozhi Wei [Sat, 7 Apr 2018 23:36:10 +0000 (23:36 +0000)]
[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))
In our real world application, we found the following optimization is missed in DAGCombiner
(zext (and/or/xor (shl/shr (load x), cst), cst)) -> (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst))
If the user of original zext is an add, it may enable further lea optimization on x86.
This patch add a new function CombineZExtLogicopShiftLoad to do this optimization.
Differential Revision: https://reviews.llvm.org/D44402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329516
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Philip Pfaffe [Sat, 7 Apr 2018 20:22:38 +0000 (20:22 +0000)]
Revert "Followup for r329293: Temporarily disable the breaking test on windows."
This reverts commit r329393 /
b52ba35e7759cd4002221be1dbb63ec80fde21ec.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329514
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Simon Pilgrim [Sat, 7 Apr 2018 19:50:09 +0000 (19:50 +0000)]
[X86] Regenerate atom pshufb test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329511
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Craig Topper [Sat, 7 Apr 2018 19:09:52 +0000 (19:09 +0000)]
[X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG combine instead of lowering.
Previously we used a custom lowering for this because of the AVX1 splitting requirement. But we can do the split during DAG combine if we check the types and subtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329510
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Craig Topper [Sat, 7 Apr 2018 19:09:50 +0000 (19:09 +0000)]
[DAGCombiner] Add a combine to turn a build vector of zero extends of extract vector elts into a vector zero extend and possibly an extract subvector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329509
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Robert Widmann [Sat, 7 Apr 2018 16:26:59 +0000 (16:26 +0000)]
[llgo] Move SetSubprogram
Summary: Fixes the bots - I moved LLVMSetSubprogram into the DIBuilder bindings, so the Go bindings need to move as well.
Reviewers: whitequark
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45402
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329505
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Simon Pilgrim [Sat, 7 Apr 2018 14:20:10 +0000 (14:20 +0000)]
[CostModel][X86] Regenerate vector reduction cost tests with update_analyze_test_checks.py
NOTE: We're only really interested in the extractelement cost (which represents the entire reduction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329504
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Sanjay Patel [Sat, 7 Apr 2018 14:14:23 +0000 (14:14 +0000)]
[InstCombine] simplify code that propagates FMF; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329503
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Simon Pilgrim [Sat, 7 Apr 2018 14:09:54 +0000 (14:09 +0000)]
[CostModel][X86] Regenerate vector select cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329502
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Sanjay Patel [Sat, 7 Apr 2018 14:07:58 +0000 (14:07 +0000)]
[InstCombine] add/move tests for fsub folds; NFC
There are a pair of folds that try to merge fneg into fsub
with an intervening cast, but as shown in the FIXME tests,
they can create extra instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329501
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Simon Pilgrim [Sat, 7 Apr 2018 14:05:35 +0000 (14:05 +0000)]
[CostModel][X86] Regenerate vector integer truncation cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329500
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Simon Pilgrim [Sat, 7 Apr 2018 14:02:14 +0000 (14:02 +0000)]
[CostModel][X86] Regenerate silvermont (and added goldmont) cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329499
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Simon Pilgrim [Sat, 7 Apr 2018 13:24:33 +0000 (13:24 +0000)]
[CostModel][X86] Fix v32i16/v64i8 SETCC costs on AVX512BW targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329498
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Simon Pilgrim [Sat, 7 Apr 2018 12:47:35 +0000 (12:47 +0000)]
[CostModel][X86] Regenerate vector comparison cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329497
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Simon Pilgrim [Sat, 7 Apr 2018 11:37:21 +0000 (11:37 +0000)]
[llvm-exegesis] Fix unused return value warning and add a useful error message for event counter reads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329496
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Tim Northover [Sat, 7 Apr 2018 10:57:03 +0000 (10:57 +0000)]
Reapply ARM: Do not spill CSR to stack on entry to noreturn functions
Should fix UBSan bot by also checking there's no "uwtable" attribute
before skipping. Otherwise the unwind table will be useless since its
moves expect CSRs to actually be preserved.
A noreturn nounwind function can be expected to never return in any way, and by
never returning it will also never have to restore any callee-saved registers
for its caller. This makes it possible to skip spills of those registers during
function entry, saving some stack space and time in the process. This is rather
useful for embedded targets with limited stack space.
Should fix PR9970.
Patch mostly by myeisha (pmb).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329494
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Roman Lebedev [Sat, 7 Apr 2018 10:37:24 +0000 (10:37 +0000)]
[InstCombine] Get rid of select of bittest (PR36950 / PR17564)
Summary:
See [[ https://bugs.llvm.org/show_bug.cgi?id=36950 | PR36950 ]], [[ https://bugs.llvm.org/show_bug.cgi?id=17564 | PR17564 ]], D45065, D45107
https://godbolt.org/g/iAYRup
Alive proof: https://rise4fun.com/Alive/uiH
Testing: `ninja check-llvm`
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329492
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Roman Lebedev [Sat, 7 Apr 2018 10:37:18 +0000 (10:37 +0000)]
[unittests] ADT: silence -Wself-assign diagnostics
Summary:
D44883 extends -Wself-assign to also work on C++ classes.
In it's current state (as suggested by @rjmccall), it is not under it's own sub-group.
Since that diag is enabled by `-Wall`, stage2 testing showed that:
* It does not fire on any llvm code
* It does fire for these 3 unittests
* It does fire for libc++ tests
This diff simply silences those new warnings in llvm's unittests.
A similar diff will be needed for libcxx. (`libcxx/test/std/language.support/support.types/byteops/`, maybe something else)
Since i don't think we want to repeat rL322901, let's talk about it.
I've subscribed everyone who i think might be interested...
There are several ways forward:
* Not extend -Wself-assign, close D44883. Not very productive outcome i'd say.
* Keep D44883 in it's current state.
Unless your custom overloaded operators do something unusual for when self-assigning,
the warning is no less of a false-positive than the current -Wself-assign.
Except for tests of course, there you'd want to silence it. The current suggestion is:
```
S a;
a = (S &)a;
```
* Split the diagnostic in two - `-Wself-assign-builtin` (i.e. what is `-Wself-assign` in trunk),
and `-Wself-assign-overloaded` - the new part in D44883.
Since, as i said, i'm not really sure why it would be less of a error than the current `-Wself-assign`,
both would still be in `-Wall`. That way one could simply pass `-Wno-self-assign-overloaded` for all the tests.
Pretty simple to do, and will surely work.
* Split the diagnostic in two - `-Wself-assign-trivial`, and `-Wself-assign-nontrivial`.
The choice of which diag to emit would depend on trivial-ness of that particular operator.
The current `-Wself-assign` would be `-Wself-assign-trivial`.
https://godbolt.org/g/gwDASe - `A`, `B` and `C` case would be treated as trivial, and `D`, `E` and `F` as non-trivial.
Will be the most complicated to implement.
Thoughts?
Reviewers: aaron.ballman, rsmith, rtrieu, rjmccall, dblaikie, atrick, gottesmm
Reviewed By: dblaikie
Subscribers: lebedev.ri, phosek, vsk, rnk, thakis, sammccall, mclow.lists, llvm-commits, rjmccall
Differential Revision: https://reviews.llvm.org/D45082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329491
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Vitaly Buka [Sat, 7 Apr 2018 09:46:00 +0000 (09:46 +0000)]
Fix stack-use-after-scope in test previously hidden by -fmerge-all-constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329489
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Robert Widmann [Sat, 7 Apr 2018 06:07:55 +0000 (06:07 +0000)]
[LLVM-C] Move DIBuilder Bindings For Block Scopes
Summary: Move LLVMDIBuilderCreateFunction , LLVMDIBuilderCreateLexicalBlock, and LLVMDIBuilderCreateLexicalBlockFile from Go to LLVM-C.
Reviewers: whitequark, harlanhaskins, deadalnix
Reviewed By: whitequark, harlanhaskins
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45352
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329488
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Vitaly Buka [Sat, 7 Apr 2018 05:36:44 +0000 (05:36 +0000)]
Revert "ARM: Do not spill CSR to stack on entry to noreturn functions"
Breaks ubsan test TestCases/Misc/missing_return.cpp on ARM
This reverts commit r329287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329486
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Nico Weber [Sat, 7 Apr 2018 04:28:08 +0000 (04:28 +0000)]
Convert line endings of lib/WindowsManifest/CMakeLists.txt to unix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329483
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Nico Weber [Sat, 7 Apr 2018 03:30:28 +0000 (03:30 +0000)]
Remove trailing space in build file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329479
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Mandeep Singh Grang [Sat, 7 Apr 2018 01:29:45 +0000 (01:29 +0000)]
[unittests] Change std::sort to llvm::sort in response to r327219
r327219 added wrappers to std::sort which randomly shuffle the container before
sorting. This will help in uncovering non-determinism caused due to undefined
sorting order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of
std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to
llvm::sort. Refer the comments section in D44363 for a list of all the
required patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329475
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Graydon Hoare [Sat, 7 Apr 2018 00:44:02 +0000 (00:44 +0000)]
[Support] Make line-number cache robust against access patterns.
Summary:
The LLVM SourceMgr class (which is used indirectly by Swift, though not Clang)
has a routine for looking up line numbers of SMLocs. This routine uses a
shared, special-purpose cache that handles exactly one access pattern
efficiently: looking up the line number of an SMLoc that points into the same
buffer as the last query made to the SourceMgr, at a location in the buffer at
or ahead of the last query.
When this works it's fine, but when it fails it's catastrophic for performancer:
one recent out-of-order access from a Swift utility routine ran for tens of
seconds, spending 99% of its time repeatedly scanning buffers for '\n'.
This change removes the shared cache from the SourceMgr and installs a new
cache in each SrcBuffer. The per-SrcBuffer caches are also "full", in the sense
that rather than caching a single last-query pointer, they cache _all_ the
line-ending offsets, in a binary-searchable array, such that once it's
populated (on first access), all subsequent access patterns run at the same
speed.
Performance measurements I've done show this is actually a little bit faster on
real codebases (though only a couple fractions of a percent). Memory usage is
up by a few tens to hundreds of bytes per SrcBuffer that has a line lookup done
on it; I've attempted to minimize this by using dynamic selection of integer
sized when storing offset arrays. But the main motive here is to
make-impossible the cases we don't always see, that show up by surprise when
there is an out-of-order access pattern.
Reviewers: jordan_rose
Reviewed By: jordan_rose
Subscribers: probinson, llvm-commits
Differential Revision: https://reviews.llvm.org/D45003
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329470
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Aaron Smith [Sat, 7 Apr 2018 00:32:59 +0000 (00:32 +0000)]
Windows needs the current codepage instead of utf8 sometimes
Llvm-mc (and tools that use Path.inc on Windows) assume that strings are utf-8
encoded, however, this is not always the case. On Windows the default codepage
is not utf-8, so most of the time the strings are not utf-8 encoded.
The lld test 'format-binary-non-ascii' uses llvm-mc with a file with non-ascii
characters in the name which is how this bug was found. The test fails when run
using Python 3 because it uses properly encoded unicode strings (Python 2 actually
ends up using a byte string which is not utf-8 encoded, so the test passes, but
that's separate issue).
Patch by Stella Stamenova!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329468
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Aaron Smith [Sat, 7 Apr 2018 00:21:28 +0000 (00:21 +0000)]
[lit] Fix several Python 2/3 compatibility issues and tests
- In Python 2.x, basestring is the base string type, but in
Python 3.x basestring is not defined and instead str includes
unicode strings.
- When Python is in a path that includes spaces, it needs to
be specified with quotes in the test files for it to run.
- The cache.ll test relies on files of a specific size being
created by Python, but on some versions of Windows the
files that are created by the current code are one byte
larger than expected. To fix the test, update file creation
to always make files of the expected size.
Patch by Stella Stamenova!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329466
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Artem Belevich [Fri, 6 Apr 2018 22:25:08 +0000 (22:25 +0000)]
[NVPTX] add support for initializing fp16 arrays.
Previously HalfTy was not handled which would either trigger an assertion,
or result in array initialized with garbage.
Differential Revision: https://reviews.llvm.org/D45391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329463
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Vitaly Buka [Fri, 6 Apr 2018 21:41:17 +0000 (21:41 +0000)]
Fix warning by cl::opt<int> -> cl::opt<unsigned>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329461
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Vitaly Buka [Fri, 6 Apr 2018 21:32:36 +0000 (21:32 +0000)]
Runtime flag to control branch funnel threshold
Reviewers: pcc
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329459
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Peter Collingbourne [Fri, 6 Apr 2018 21:14:33 +0000 (21:14 +0000)]
Revert r324557, "gold-plugin: Do not set codegen opt level based on LTO opt level."
It was reported that this change measurably regressed -plugin-opt=O3
performance.
There is an ongoing discussion on llvm-dev about the correct way to
set the CG opt level, see thread "[llvm-dev] [RFC] Adding function
attributes to represent codegen optimization level".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329458
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Manoj Gupta [Fri, 6 Apr 2018 21:11:09 +0000 (21:11 +0000)]
[Release Notes] Add release note for "-fmerge-all-constants"
Summary:
Add note that "-fmerge-all-constants" is not applied as default
anymore.
Reviewers: rjmccall, rsmith, chandlerc
Subscribers: llvm-commits, thakis
Differential Revision: https://reviews.llvm.org/D45388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329457
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Artem Belevich [Fri, 6 Apr 2018 21:10:24 +0000 (21:10 +0000)]
[NVPTX] Fixed vectorized LDG for f16.
v2f16 is a special case in NVPTX. v4f16 may be loaded as a pair of v2f16
and that was not previously handled correctly by tryLDGLDU()
Differential Revision: https://reviews.llvm.org/D45339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329456
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Sameer AbuAsal [Fri, 6 Apr 2018 21:07:05 +0000 (21:07 +0000)]
[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329455
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Mandeep Singh Grang [Fri, 6 Apr 2018 20:18:05 +0000 (20:18 +0000)]
[TableGen] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: stoklund, kparzysz, dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329451
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Matt Davis [Fri, 6 Apr 2018 20:14:13 +0000 (20:14 +0000)]
[StackProtector] Ignore certain intrinsics when calculating sspstrong heuristic.
Summary:
The 'strong' StackProtector heuristic takes into consideration call instructions.
Certain intrinsics, such as lifetime.start, can cause the
StackProtector to protect functions that do not need to be protected.
Specifically, a volatile variable, (not optimized away), but belonging to a stack
allocation will encourage a llvm.lifetime.start to be inserted during
compilation. Because that intrinsic is a 'call' the strong StackProtector
will see that the alloca'd variable is being passed to a call instruction, and
insert a stack protector. In this case the intrinsic isn't really lowered to a
call. This can cause unnecessary stack checking, at the cost of additional
(wasted) CPU cycles.
In the future we should rely on TargetTransformInfo::isLoweredToCall, but as of
now that routine considers all intrinsics as not being lowerable. That needs
to be corrected, and such a change is on my list of things to get moving on.
As a side note, the updated stack-protector-dbginfo.ll test always seems to
pass. I never see the dbg.declare/dbg.value reaching the
StackProtector::HasAddressTaken, but I don't see any code excluding dbg
intrinsic calls either, so I think it's the safest thing to do.
Reviewers: void, timshen
Reviewed By: timshen
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329450
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Geoff Berry [Fri, 6 Apr 2018 18:47:33 +0000 (18:47 +0000)]
[EarlyCSE] Add debug counter for debugging mis-optimizations. NFC.
Reviewers: reames, spatel, davide, dberlin
Subscribers: mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D45162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329443
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Sameer AbuAsal [Fri, 6 Apr 2018 18:27:45 +0000 (18:27 +0000)]
[RISCV] Update MC compression tests
Summary:
This patch updates MC tests related to compression in RISCV to
insure they work correctly with automatic compression and relaxation
enabled. This is the first part of a series of patches to implement
automatic compression for RISCV.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: shiva0217, efriedma, llvm-commits, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng
Differential Revision: https://reviews.llvm.org/D43328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329441
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Dmitry Preobrazhensky [Fri, 6 Apr 2018 18:24:49 +0000 (18:24 +0000)]
[AMDGPU][MC][GFX9] Added s_call_b64
See bug 36843: https://bugs.llvm.org/show_bug.cgi?id=36843
Differential Revision: https://reviews.llvm.org/D45268
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329440
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Krzysztof Parzyszek [Fri, 6 Apr 2018 18:19:22 +0000 (18:19 +0000)]
[Hexagon] Fix assert with packetizing IMPLICIT_DEF instructions
The compiler is generating packet with the following instructions,
which causes an undefined register assert in the verifier.
$r0 = IMPLICIT_DEF
$r1 = IMPLICIT_DEF
S2_storerd_io killed $r29, 0, killed %d0
The problem is that the packetizer is not saving the IMPLICIT_DEF
instructions, which are needed when checking if it is legal to
add the store instruction. The fix is to add the IMPLICIT_DEF
instructions to the CurrentPacketMIs structure.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329439
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Krzysztof Parzyszek [Fri, 6 Apr 2018 18:13:11 +0000 (18:13 +0000)]
[Hexagon] Prevent a stall across zero-latency instructions in a packet
Packetizer keeps two zero-latency bound instrctions in the same packet ignoring
the stalls on the later instruction. This should not be the case if there is no
data dependence.
Patch by Sumanth Gundapaneni.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329437
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Krzysztof Parzyszek [Fri, 6 Apr 2018 18:10:13 +0000 (18:10 +0000)]
[Hexagon] Remove duplicated code, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329436
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Mandeep Singh Grang [Fri, 6 Apr 2018 18:08:42 +0000 (18:08 +0000)]
[CodeGen] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort.
Refer the comments section in D44363 for a list of all the required patches.
Reviewers: bogner, rnk, MatzeB, RKSimon
Reviewed By: rnk
Subscribers: JDevlieghere, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D45133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329435
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Krzysztof Parzyszek [Fri, 6 Apr 2018 17:51:57 +0000 (17:51 +0000)]
[Hexagon] Handle subregisters when calculating iteration count in HW loops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329434
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Simon Pilgrim [Fri, 6 Apr 2018 17:25:06 +0000 (17:25 +0000)]
Cleanup Reduction helpers by using ArrayRef(NoneType) constructor. NFCI.
Pointed out by @abataev on D45366.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329431
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Dmitry Preobrazhensky [Fri, 6 Apr 2018 17:25:00 +0000 (17:25 +0000)]
[AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done
See bug 36844: https://bugs.llvm.org/show_bug.cgi?id=36844
Differential Revision: https://reviews.llvm.org/D45313
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329430
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Sanjay Patel [Fri, 6 Apr 2018 17:24:08 +0000 (17:24 +0000)]
[InstCombine] limit nsz: -(X - Y) --> Y - X to hasOneUse()
As noted in the post-commit discussion for r329350, we shouldn't
generally assume that fsub is the same cost as fneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329429
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Simon Pilgrim [Fri, 6 Apr 2018 17:18:44 +0000 (17:18 +0000)]
Add additional tests from D45336
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329427
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Simon Pilgrim [Fri, 6 Apr 2018 17:15:56 +0000 (17:15 +0000)]
Add additional tests from D45366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329425
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Craig Topper [Fri, 6 Apr 2018 17:12:18 +0000 (17:12 +0000)]
[X686] Add appropriate ReadAfterLd for the register input to memory forms of ADC/SBB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329424
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Simon Pilgrim [Fri, 6 Apr 2018 17:01:54 +0000 (17:01 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329421
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Dmitry Preobrazhensky [Fri, 6 Apr 2018 16:35:11 +0000 (16:35 +0000)]
[AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*
See bug 36840: https://bugs.llvm.org/show_bug.cgi?id=36840
Differential Revision: https://reviews.llvm.org/D45250
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329419
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Sanjay Patel [Fri, 6 Apr 2018 16:30:52 +0000 (16:30 +0000)]
[InstCombine] add test for fsub+fneg with extra use; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329418
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Craig Topper [Fri, 6 Apr 2018 16:29:31 +0000 (16:29 +0000)]
[X86] Remove InstRWs for basic arithmetic instructions from Sandy Bridge scheduler model.
We can get this right through WriteALU and friends now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329417
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Craig Topper [Fri, 6 Apr 2018 16:16:48 +0000 (16:16 +0000)]
[X86] Attempt to model basic arithmetic instructions in the Haswell/Broadwell/Skylake scheduler models without InstRWs
Summary:
This patch removes InstRW overrides for basic arithmetic/logic instructions. To do this I've added the store address port to RMW. And used a WriteSequence to make the latency additive. It does not cover ADC/SBB because they have different latency.
Apparently we were inconsistent about whether the store has latency or not thus the test changes.
I've also left out Sandy Bridge because the load latency there is currently 4 cycles and should be 5.
Reviewers: RKSimon, andreadb
Reviewed By: andreadb
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45351
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329416
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Craig Topper [Fri, 6 Apr 2018 16:16:46 +0000 (16:16 +0000)]
[X86] Add an extra store address cycle to WriteRMW in the Sandy Bridge/Broadwell/Haswell/Skylake scheduler model.
Even those the address was calculated for the load, its calculated again for the store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329415
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Craig Topper [Fri, 6 Apr 2018 16:16:43 +0000 (16:16 +0000)]
[X86] Merge itineraries for CLC, CMC, and STC.
These are very simple flag setting instructions that appear to only be a single uop. They're unlikely to need this separation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329414
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Simon Pilgrim [Fri, 6 Apr 2018 16:14:27 +0000 (16:14 +0000)]
[CostModel][X86] Regenerate bit count cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329413
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Sanjay Patel [Fri, 6 Apr 2018 16:06:08 +0000 (16:06 +0000)]
[InstCombine] add potential calloc tests and regenerate checks; NFC
D45344 is proposing to remove the use restriction that made the calloc
transform safe, but it doesn't currently address the problematic example
given inD16337. Add a test to make sure that doesn't break.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329412
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Simon Pilgrim [Fri, 6 Apr 2018 16:00:28 +0000 (16:00 +0000)]
[CostModel][X86] Regenerate vector shuffle cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329410
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Mircea Trofin [Fri, 6 Apr 2018 15:54:47 +0000 (15:54 +0000)]
[GlobalOpt] Fix support for casts in ctors.
Summary:
Fixing an issue where initializations of globals where constructors use
casts were silently translated to 0-initialization.
Reviewers: davidxl, evgeny777
Reviewed By: evgeny777
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45198
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329409
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Dmitry Preobrazhensky [Fri, 6 Apr 2018 15:48:39 +0000 (15:48 +0000)]
[AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions
See bug 36839: https://bugs.llvm.org/show_bug.cgi?id=36839
Differential Revision: https://reviews.llvm.org/D45249
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329408
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Simon Pilgrim [Fri, 6 Apr 2018 15:46:26 +0000 (15:46 +0000)]
[CostModel][X86] Regenerate bswap/bitreverse cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329407
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Pete Couperus [Fri, 6 Apr 2018 15:43:11 +0000 (15:43 +0000)]
[ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}.
Add disassembler support for instructions which writeback STATUS32.
https://reviews.llvm.org/D45148
Patch by Yan Luo! (Yan.Luo2@synopsys.com)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329404
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Andrea Di Biagio [Fri, 6 Apr 2018 15:30:02 +0000 (15:30 +0000)]
[llvm-mca] Do not separate iterations with a newline in the timeline view.
Also, update a few tests to minimize the diff in D45369.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329403
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Simon Pilgrim [Fri, 6 Apr 2018 15:28:26 +0000 (15:28 +0000)]
[CostModel][X86] Regenerate integer extension/truncation cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329402
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Simon Pilgrim [Fri, 6 Apr 2018 15:23:26 +0000 (15:23 +0000)]
[CostModel][X86] Regenerate integer division/remainder tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329401
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Simon Pilgrim [Fri, 6 Apr 2018 15:14:34 +0000 (15:14 +0000)]
[CostModel][X86] Regenerate vector shift cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329400
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Simon Pilgrim [Fri, 6 Apr 2018 15:12:36 +0000 (15:12 +0000)]
[CostModel][X86] Regenerate int<->fp cost tests with update_analyze_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329398
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Dmitry Preobrazhensky [Fri, 6 Apr 2018 15:08:42 +0000 (15:08 +0000)]
[AMDGPU][MC][GFX9] Added s_dcache_discard* instructions
See bug 36838: https://bugs.llvm.org/show_bug.cgi?id=36838
Differential Revision: https://reviews.llvm.org/D45247
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329397
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Chad Rosier [Fri, 6 Apr 2018 13:57:21 +0000 (13:57 +0000)]
[LoopUnroll] Make LoopPeeling respect the AllowPeeling preference.
The SimpleLoopUnrollPass isn't suppose to perform loop peeling.
Differential Revision: https://reviews.llvm.org/D45334
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329395
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Philip Pfaffe [Fri, 6 Apr 2018 13:39:16 +0000 (13:39 +0000)]
Followup for r329293: Temporarily disable the breaking test on windows.
This test is failing on windows bots. Disable it temporarily to unbreak
the windows bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329393
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Pavel Labath [Fri, 6 Apr 2018 13:34:12 +0000 (13:34 +0000)]
DWARFVerifier: validate information in name index entries
Summary:
This patch add checks to verify that the information in the name index
entries is consistent with the debug_info section. Specifically, we
check that entries point to valid DIEs, and their names, tags, and
compile units match the information in the debug_info sections.
These checks are only run if the previous checks did not find any errors
in the name index headers. Attempting to proceed with the checks anyway
would likely produce a lot of spurious errors and the verification code
would need to be very careful to avoid crashing.
I also add a couple of more checks to the abbreviation-validation code
to verify that some attributes are always present (an index without a
DW_IDX_die_offset attribute is fairly useless).
The entry verification works only on indexes without any type units - I
haven't attempted to extend it to type units, as we don't even have a
DWARF v5-compatible type unit generator at the moment.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45323
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329392
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Simon Pilgrim [Fri, 6 Apr 2018 12:36:27 +0000 (12:36 +0000)]
[UpdateTestChecks] Add update_analyze_test_checks.py for cost model analysis generation
The script allows the auto-generation of checks for cost model tests to speed up their creation and help improve coverage, which will help a lot with PR36550.
If the need arises we can add support for other analyze passes as well, but the cost models was the one I needed to get done - at the moment it just warns that any other analysis mode is unsupported.
I've regenerated a couple of x86 test files to show the effect.
Differential Revision: https://reviews.llvm.org/D45272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329390
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Simon Pilgrim [Fri, 6 Apr 2018 11:25:21 +0000 (11:25 +0000)]
[X86][SandyBridge] Add (V)DPPS memory fold latencies
Noticed this during D44654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329389
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Simon Pilgrim [Fri, 6 Apr 2018 11:00:51 +0000 (11:00 +0000)]
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions.
I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent.
As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests...
Differential Revision: https://reviews.llvm.org/D44654
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329388
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Hans Wennborg [Fri, 6 Apr 2018 10:20:19 +0000 (10:20 +0000)]
Tweak an assert message in the verifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329387
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Simon Pilgrim [Fri, 6 Apr 2018 10:16:36 +0000 (10:16 +0000)]
[X86][SkylakeServer] Merge 2 InstRW entries to the same sched group. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329386
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Hans Wennborg [Fri, 6 Apr 2018 10:14:09 +0000 (10:14 +0000)]
EntryExitInstrumenter: Handle musttail calls
Inserting instrumentation between a musttail call and ret instruction
would create invalid IR. Instead, treat musttail calls as function
exits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329385
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