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Amaury Sechet [Mon, 7 Mar 2016 22:40:07 +0000 (22:40 +0000)]
Remove unused import in Orc C API
Summary: It is not used.
Reviewers: lhames
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17251
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262870
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Quentin Colombet [Mon, 7 Mar 2016 22:32:42 +0000 (22:32 +0000)]
[IR] Provide an API to skip the details of a structured type when printed.
The mir infrastructure will need this for generic instructions and currently
this feature was only available through the anonymous TypePrinter class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262869
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Quentin Colombet [Mon, 7 Mar 2016 22:09:05 +0000 (22:09 +0000)]
[AsmParser] Add a function to parse a standalone type.
This is useful for MIR serialization. Indeed generic machine instructions
must have a type and we don't want to duplicate the logic in the MIParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262868
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Quentin Colombet [Mon, 7 Mar 2016 21:57:52 +0000 (21:57 +0000)]
[MIR] Teach the MIPrinter about size for generic virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262867
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Matt Arsenault [Mon, 7 Mar 2016 21:54:52 +0000 (21:54 +0000)]
Fix broken example for bitreverse documentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262865
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Matt Arsenault [Mon, 7 Mar 2016 21:54:48 +0000 (21:54 +0000)]
AMDGPU: Match more med3 integer patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262864
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Quentin Colombet [Mon, 7 Mar 2016 21:48:43 +0000 (21:48 +0000)]
[MIR] Teach the parser how to handle the size of generic virtual registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262862
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Quentin Colombet [Mon, 7 Mar 2016 21:41:39 +0000 (21:41 +0000)]
[MachineRegisterInfo] Add a method to set the size of a virtual register a posteriori.
This is required for mir testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262861
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Amaury Sechet [Mon, 7 Mar 2016 21:39:20 +0000 (21:39 +0000)]
Small formating change in Core.cpp . NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262860
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Quentin Colombet [Mon, 7 Mar 2016 21:22:09 +0000 (21:22 +0000)]
[MachineRegisterInfo] Get rid of the global-isel ifdefs.
One additional pointer is not a big deal size-wise and it makes
the code much nicer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262856
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Matt Arsenault [Mon, 7 Mar 2016 21:12:46 +0000 (21:12 +0000)]
AMDGPU: Remove a fixme for ptrrtoint handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262854
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Matt Arsenault [Mon, 7 Mar 2016 21:10:13 +0000 (21:10 +0000)]
AMDGPU: Move function only used by R600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262853
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Matt Arsenault [Mon, 7 Mar 2016 21:10:09 +0000 (21:10 +0000)]
DAGCombiner: Check legality before creating extract_vector_elt
Problem not hit by any in tree target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262852
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Justin Bogner [Mon, 7 Mar 2016 20:15:12 +0000 (20:15 +0000)]
SelectionDAG: Remove some unused AtomicSDNode constructors. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262849
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Adam Nemet [Mon, 7 Mar 2016 18:35:42 +0000 (18:35 +0000)]
[LoopDataPrefetch] If prefetch distance is not set, skip pass
This lets select sub-targets enable this pass. The patch implements the
idea from the recent llvm-dev thread:
http://thread.gmane.org/gmane.comp.compilers.llvm.devel/94925
The goal is to enable the LoopDataPrefetch pass for the Cyclone
sub-target only within Aarch64.
Positive and negative tests will be included in an upcoming patch that
enables selective prefetching of large-strided accesses on Cyclone.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262844
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Marina Yatsina [Mon, 7 Mar 2016 18:11:16 +0000 (18:11 +0000)]
[ms-inline-asm][AVX512] Add ability to use k registers in MS inline asm + fix bag with curly braces
Until now curly braces could only be used in MS inline assembly to mark block start/end.
All curly braces were removed completely at a very early stage.
This approach caused bugs like:
"m{o}v eax, ebx" turned into "mov eax, ebx" without any error.
In addition, AVX-512 added special operands (e.g., k registers), which are also surrounded by curly braces that mark them as such.
Now, we need to keep the curly braces and identify at a later stage if they are marking block start/end (if so, ignore them), or surrounding special AVX-512 operands (if so, parse them as such).
This patch fixes the bug described above and enables the use of AVX-512 special operands.
This commit is the the llvm part of the patch.
The clang part of the review is: http://reviews.llvm.org/D17766
The llvm part of the review is: http://reviews.llvm.org/D17767
Differential Revision: http://reviews.llvm.org/D17767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262843
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Adam Nemet [Mon, 7 Mar 2016 17:49:10 +0000 (17:49 +0000)]
[ScopedNoAliasAA] Make test basic.ll less confusing
Summary:
This testcase had me confused. It made me believe that you can use
alias scopes and alias scopes list interchangeably with alias.scope and
noalias. Both langref and the other testcase use scope lists so I went
looking.
Turns out using scope directly only happens to work by chance. When
ScopedNoAliasAAResult::mayAliasInScopes traverses this as a scope list:
!1 = !{!1, !0, !"some scope"}
, the first entry is in fact a scope but only because the scope is
happened to be defined self-referentially to make it unique globally.
The remaining elements in the tuple (!0, !"some scope") are considered
as scopes but AliasScopeNode::getDomain will just bail on those without
any error.
This change avoids this ambiguity in the test but I've also been
wondering if we should issue some sort of a diagnostics.
Reviewers: dexonsmith, hfinkel
Subscribers: mssimpso, llvm-commits
Differential Revision: http://reviews.llvm.org/D16670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262841
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Adam Nemet [Mon, 7 Mar 2016 17:38:02 +0000 (17:38 +0000)]
Revert "Enable LoopLoadElimination by default"
This reverts commit r262250.
It causes SPEC2006/gcc to generate wrong result (166.s) in AArch64 when
running with *ref* data set. The error happens with
"-Ofast -flto -fuse-ld=gold" or "-O3 -fno-strict-aliasing".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262839
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Chandler Carruth [Mon, 7 Mar 2016 15:12:57 +0000 (15:12 +0000)]
[memdep] Switch to range based for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262831
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Chandler Carruth [Mon, 7 Mar 2016 14:05:09 +0000 (14:05 +0000)]
[DFSan] Remove an overly aggressive assert reported in PR26068.
This code has been successfully used to bootstrap libc++ in a no-asserts
mode for a very long time, so the code that follows cannot be completely
incorrect. I've added a test that shows the current behavior for this
kind of code with DFSan. If it is desirable for DFSan to do something
special when processing an invoke of a variadic function, it can be
added, but we shouldn't keep an assert that we've been ignoring due to
release builds anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262829
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Chandler Carruth [Mon, 7 Mar 2016 12:45:07 +0000 (12:45 +0000)]
[memdep] Switch a function to return true on success instead of false.
This is much more clear and less surprising IMO. It also makes things
more consistent with the increasingly large chunk of LLVM code that
assumes true-on-success.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262826
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Chandler Carruth [Mon, 7 Mar 2016 12:30:06 +0000 (12:30 +0000)]
[memdep] Cleanup the implementation doxygen comments and remove
duplicated comments.
In several cases these had diverged making them especially nice to
canonicalize. I checked to make sure we weren't losing important
information of course.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262825
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Chandler Carruth [Mon, 7 Mar 2016 11:27:56 +0000 (11:27 +0000)]
[memdep] Finish cleaning up all of the comments' doxygen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262824
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Chandler Carruth [Mon, 7 Mar 2016 11:04:46 +0000 (11:04 +0000)]
[memdep] Switch from a hacky use of PointerIntPair and poorly chosen
arbitrary integers cast to Instruction pointers to a sum type over
Instruction * and a PointerEmbeddedInt.
No functionality changed.
Differential Revision: http://reviews.llvm.org/D15845
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262823
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Chandler Carruth [Mon, 7 Mar 2016 10:35:02 +0000 (10:35 +0000)]
[memdep] Update the comments' doxygen style and place them more clearly.
Just cleaning this up, no functionality changed. Next up will be moving
it to use the sum type instead of arbitrary "pointer"-like enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262822
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Chandler Carruth [Mon, 7 Mar 2016 10:19:30 +0000 (10:19 +0000)]
[memdep] Run clang-format over the header before porting it to
the new pass manager.
The port will involve substantial edits here, and would likely introduce
bad formatting if formatted in isolation, so just get all the formatting
up to snuff. I'll also go through and try to freshen the doxygen here as
well as modernizing some of the code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262821
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Craig Topper [Mon, 7 Mar 2016 07:29:12 +0000 (07:29 +0000)]
[CodeGen] Add space-optimized EmitMergeInputChains1_2 to the DAG isel matching tables. Shaves about 5100 bytes from the X86 matcher table. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262815
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Mehdi Amini [Mon, 7 Mar 2016 00:51:00 +0000 (00:51 +0000)]
Add a new insert_as() method to DenseMap and use it for ConstantUniqueMap
Just like the existing find_as() method, the new insert_as() accepts
an extra parameter which is used as a key to find the bucket in the
map.
When creating a Constant, we want to check the map before actually
creating the object. In this case we have to perform two queries to
the map, and this extra parameter can save recomputing the hash value
for the second query.
This is a reapply of r260458, that was reverted because it was
suspected to be the cause of instability of an internal bot, but
wasn't confirmed.
Differential Revision: http://reviews.llvm.org/D16268
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262812
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Mehdi Amini [Mon, 7 Mar 2016 00:38:09 +0000 (00:38 +0000)]
Bitcode reader: Inline readAbbreviatedField in readRecord and move the enclosing loop in each case (NFC)
Summary: This make readRecord 20% faster, measured on an LTO build
Reviewers: rafael
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D17911
From: Mehdi Amini <mehdi.amini@apple.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262811
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NAKAMURA Takumi [Mon, 7 Mar 2016 00:13:09 +0000 (00:13 +0000)]
Revert r130657, "Windows/DynamicLibrary.inc: Clean up ELM_Callback. We may check the decl instead of the versions of individual libraries."
We may assume the type of 1st argument as PCSTR in PENUMLOADED_MODULES_CALLBACK. PSTR was in the ancient mingw32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262810
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Simon Pilgrim [Sun, 6 Mar 2016 21:54:52 +0000 (21:54 +0000)]
[X86][AVX512] Fixed VPERMT2* shuffle mask decoding and enabled target shuffle combining.
Patch to add support for target shuffle combining of X86ISD::VPERMV3 nodes, including support for detecting unary shuffles.
This uncovered several issues with the X86ISD::VPERMV3 shuffle mask decoding of non-64 bit shuffle mask elements - the bit masking wasn't being correctly computed.
Removed non-constant pool mask decode path as we have no way of testing it right now.
Differential Revision: http://reviews.llvm.org/D17916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262809
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Valery Pykhtin [Sun, 6 Mar 2016 20:25:36 +0000 (20:25 +0000)]
[AMDGPU] Using table-driven amd_kernel_code_t field parser in assembler.
Engages code from r262804.
Differential Revision: http://reviews.llvm.org/D17151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262808
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Valery Pykhtin [Sun, 6 Mar 2016 15:13:54 +0000 (15:13 +0000)]
fix sanitizer-ppc64be-linux failure for r262804
error: moving a local object in a return statement prevents copy elision [-Werror,-Wpessimizing-move]
http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/930
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262805
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Valery Pykhtin [Sun, 6 Mar 2016 13:27:13 +0000 (13:27 +0000)]
[AMDGPU] table-driven parser/printer for amd_kernel_code_t structure fields
Differential Revision: http://reviews.llvm.org/D17150
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262804
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Igor Breger [Sun, 6 Mar 2016 12:38:58 +0000 (12:38 +0000)]
AVX512BW: Support llvm intrinsic masked vector load/store for i8/i16 element types on SKX
Differential Revision: http://reviews.llvm.org/D17913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262803
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Wilfred Hughes [Sun, 6 Mar 2016 12:37:34 +0000 (12:37 +0000)]
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262802
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Valery Pykhtin [Sun, 6 Mar 2016 10:31:44 +0000 (10:31 +0000)]
[AMDGPU] SOPxx instructions operand naming fixed in td files.
dst -> sdst
ssrcN -> srcN
Differential Revision: http://reviews.llvm.org/D17646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262801
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Craig Topper [Sun, 6 Mar 2016 08:12:47 +0000 (08:12 +0000)]
[X86] Use high bits of return value from getEncoding instead of predicate functions to populate the REX and VEX prefix bits that extend register encodings. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262800
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Craig Topper [Sun, 6 Mar 2016 08:12:44 +0000 (08:12 +0000)]
[X86] Remove unnecessary masking. The assert above it already guaranteed it. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262799
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Craig Topper [Sun, 6 Mar 2016 08:12:42 +0000 (08:12 +0000)]
[X86] Use uint8_t instead of unsigned char as it shortens the code and more explicitly reflects the desired size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262798
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Igor Breger [Sun, 6 Mar 2016 07:46:03 +0000 (07:46 +0000)]
AVX512: Remove VSHRI kmask patterns from TD file. It is incorrect to use kshiftw to implement VSHRI v4i1 , bits 15-4 is undef so the upper bits of v4i1 may not be zeroed. v4i1 should be zero_extend to v16i1 ( or any natively supported vector).
Differential Revision: http://reviews.llvm.org/D17763
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262797
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Saleem Abdulrasool [Sun, 6 Mar 2016 04:50:55 +0000 (04:50 +0000)]
unitests: add some ARM TargetParser tests
The ARM TargetParser would construct invalid StringRefs. This would cause
asserts to trigger. Add some tests in LLVM to ensure that we dont regress on
this in the future. Although there is a test for this in clang, this ensures
that the changes would get caught in the same repository.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262790
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Alexander Kornienko [Sun, 6 Mar 2016 03:50:08 +0000 (03:50 +0000)]
[docs] Updated docs to work with Doxygen 1.8.11
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262786
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Simon Pilgrim [Sat, 5 Mar 2016 22:53:31 +0000 (22:53 +0000)]
[X86][AVX] Improved VPERMILPS variable shuffle mask decoding.
Added support for decoding VPERMILPS variable shuffle masks that aren't in the constant pool.
Added target shuffle mask decoding for SCALAR_TO_VECTOR+VZEXT_MOVL cases - these can happen for v2i64 constant re-materialization
Followup to D17681
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262784
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Simon Pilgrim [Sat, 5 Mar 2016 22:00:50 +0000 (22:00 +0000)]
[X86] AMD Bobcat CPU (btver1) doesn't support XSAVE
btver1 is a SSSE3/SSE4a only CPU - it doesn't have AVX and doesn't support XSAVE.
Differential Revision: http://reviews.llvm.org/D17683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262782
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Saleem Abdulrasool [Sat, 5 Mar 2016 20:00:44 +0000 (20:00 +0000)]
Support: catch invalid accesses
It is possible to invoke these methods on an invalid input resulting in an
invalid substring construction. It seems that we do not have unit tests for
these methods. Tests to ensure that the invalid call is caught to follow in
clang.
Resolves PR26839.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262778
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Saleem Abdulrasool [Sat, 5 Mar 2016 20:00:41 +0000 (20:00 +0000)]
ExecutionEngine: tweak debug log
Add a newline to separate the log message. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262777
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Yaron Keren [Sat, 5 Mar 2016 16:02:09 +0000 (16:02 +0000)]
Replace GlobalScopeAsm[GlobalScopeAsm.size()-1] with GlobalScopeAsm.back(), NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262775
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Krzysztof Parzyszek [Sat, 5 Mar 2016 15:45:23 +0000 (15:45 +0000)]
Add DAG mutation interface to the post-RA scheduler
Differential Revision: http://reviews.llvm.org/D17868
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262774
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Chandler Carruth [Sat, 5 Mar 2016 08:20:15 +0000 (08:20 +0000)]
[aa-eval] Enhance the comments to better describe the overview of why
this pass exists.
This is based on feedback received when moving this comment from the source
file to a new header file.
Differential Revision: http://reviews.llvm.org/D17476
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262769
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Matthias Braun [Sat, 5 Mar 2016 04:36:13 +0000 (04:36 +0000)]
RegisterCoalescer: Remap subregister lanemasks before exchanging operands
Rematerializing and merging into a bigger register class at the same
time, requires the subregister range lanemasks getting remapped to the
new register class.
This fixes http://llvm.org/PR26805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262768
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Matthias Braun [Sat, 5 Mar 2016 04:36:10 +0000 (04:36 +0000)]
RegisterCoalescer: Need to check DstReg+SrcReg for missing undef flags
copy coalescing with enabled subregister liveness can reveal undef uses,
previously this was only checked for the SrcReg in updateRegDefsUses()
but we need to check DstReg as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262767
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Matthias Braun [Sat, 5 Mar 2016 04:36:08 +0000 (04:36 +0000)]
RegisterPressure: Small cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262766
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Quentin Colombet [Sat, 5 Mar 2016 00:31:04 +0000 (00:31 +0000)]
[X86] Fix the lowering of setjmp intrinsic on i386.
When the lowering of the setjmp intrinsic requires
a global base pointer to be set, make sure such pointer
gets defined by the CGBR pass.
This fixes PR26742.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262762
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Quentin Colombet [Fri, 4 Mar 2016 23:36:32 +0000 (23:36 +0000)]
Add missing triple in my previous commit!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262760
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Quentin Colombet [Fri, 4 Mar 2016 23:29:39 +0000 (23:29 +0000)]
[X86] Do not use cmpxchgXXb when we need the base pointer (RBX).
cmpxchgXXb uses RBX as one of its implicit argument. I.e., when
we use that instruction we need to clobber RBX. This is generally
fine, expect when RBX is a reserved register because in that case,
the register allocator will not track its value and will not
save and restore it when interferences occur.
rdar://problem/
24851412
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262759
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Sanjay Patel [Fri, 4 Mar 2016 23:28:07 +0000 (23:28 +0000)]
[x86] add tests for masked loads with constant masks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262758
91177308-0d34-0410-b5e6-
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Mike Aizatsky [Fri, 4 Mar 2016 23:18:01 +0000 (23:18 +0000)]
[libfuzzer] adding std:string to allowed adaptable argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262757
91177308-0d34-0410-b5e6-
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David Majnemer [Fri, 4 Mar 2016 23:02:15 +0000 (23:02 +0000)]
Fix build breakage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262756
91177308-0d34-0410-b5e6-
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David Majnemer [Fri, 4 Mar 2016 22:56:17 +0000 (22:56 +0000)]
[X86] Support cleaning more than 2**16 bytes of stack
The x86 ret instruction has a 16 bit immediate indicating how many bytes
to pop off of the stack beyond the return address.
There is a problem when extremely large structs are passed by value: we
might not be able to fit the number of bytes to pop into the return
instruction.
To fix this, expand RET_FLAG a little later and use a special sequence
to clean the stack:
pop %ecx ; return address is now in %ecx
add $n, %esp ; clean the stack
push %ecx ; bring the return address back on the stack
ret ; pop the return address and jmp to it's value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262755
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Kostya Serebryany [Fri, 4 Mar 2016 22:35:40 +0000 (22:35 +0000)]
[libFuzzer] log less when re-loading files; fix a silly bug: when running single files actually run all of them, not just the first one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262754
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Philip Reames [Fri, 4 Mar 2016 22:27:39 +0000 (22:27 +0000)]
[LVI] Fix a bug which prevented use of !range metadata within a query
The diff is relatively large since I took a chance to rearrange the code I had to touch in a more obvious way, but the key bit is merely using the !range metadata when we can't analyze the instruction further. The previous !range metadata code was essentially just dead since no binary operator or cast will have !range metadata (per Verifier) and it was otherwise dropped on the floor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262751
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Rong Xu [Fri, 4 Mar 2016 22:08:44 +0000 (22:08 +0000)]
[PGO] Add a commandline option to control number of the VP annotation metadata.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262750
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Michael Kuperstein [Fri, 4 Mar 2016 21:23:29 +0000 (21:23 +0000)]
[DAGCombine] Fix divrem combine not to assume div/rem type is simple.
The divrem combine assumed the type of the div/rem is simple, which isn't
necessarily true. This probably worked fine until r250825, since it only
saw legal types, but now breaks when it runs as a pre-type-legalization
combine.
This fixes PR26835.
Differential Revision: http://reviews.llvm.org/D17878
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262746
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Teresa Johnson [Fri, 4 Mar 2016 21:19:08 +0000 (21:19 +0000)]
Fix new gold test to specify emulation mode.
The thinlto_linkonceresolution.ll gold linker test introduced in r262727
included a target triple, but didn't set the emulation mode, which is
necessary since the default linker target may be different.
Patch by H.J. Lu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262745
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Dan Gohman [Fri, 4 Mar 2016 20:09:57 +0000 (20:09 +0000)]
[WebAssembly] Add another possible code-size optimization to README.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262740
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Renato Golin [Fri, 4 Mar 2016 19:19:36 +0000 (19:19 +0000)]
[ARM] Merging 64-bit divmod lib calls into one
When div+rem calls on the same arguments are found, the ARM back-end merges the
two calls into one __aeabi_divmod call for up to 32-bits values. However,
for 64-bit values, which also have a lib call (__aeabi_ldivmod), it wasn't
merging the calls, and thus calling ldivmod twice and spilling the temporary
results, which generated pretty bad code.
This patch legalises 64-bit lib calls for divmod, so that now all the spilling
and the second call are gone. It also relaxes the DivRem combiner a bit on the
legal type check, since it was already checking for isLegalOrCustom on every
value, so the extra check for isTypeLegal was redundant.
Second attempt, creating TLI.isOperationCustom like isOperationExpand, to make
sure we only emit valid types or the ones that were explicitly marked as custom.
Now, passing check-all and test-suite on x86, ARM and AArch64.
This patch fixes PR17193 (and a long time FIXME in the tests).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262738
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Tom Stellard [Fri, 4 Mar 2016 18:31:18 +0000 (18:31 +0000)]
AMDGPU/SI: Add support for spiling SGPRs to scratch buffer
Summary:
This is necessary for when we run out of VGPRs and can no
longer use v_{read,write}_lane for spilling SGPRs.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D17592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262732
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Teresa Johnson [Fri, 4 Mar 2016 18:16:00 +0000 (18:16 +0000)]
Fix bot failure from r262721: unintented change in gold-plugin save-temps
The split code gen task ID should not be appended to save-temps output
file when the parallelism factor is 1 (not actually splitting).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262731
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Sanjoy Das [Fri, 4 Mar 2016 18:14:09 +0000 (18:14 +0000)]
[Statepoint docs] Delete trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262730
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Tom Stellard [Fri, 4 Mar 2016 18:02:01 +0000 (18:02 +0000)]
AMDGPU/SI: Enable frame index scavenging during PrologEpilogueInserter
Summary:
This allows us to use virtual registers when we need extra registers
for inserting spill instructions in SIRegisterInfo:eliminateFrameIndex().
Once all the frame indices have been eliminated, the
PrologEpilogueInserter does an extra pass over the program to replace
all virtual registers with physical ones.
This allows us to make more efficient use of our emergency spill slots,
so we only need to create one.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D17591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262728
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Teresa Johnson [Fri, 4 Mar 2016 17:48:35 +0000 (17:48 +0000)]
[ThinLTO] Ensure prevailing linkonce emitted as weak in ThinLTO backends
Summary:
Since IR files are all compiled into separate independent object files
in ThinLTO mode, the prevailing linkonce symbols must be emitted in its
object file even if it is no longer referenced there, e.g. if no
references remain in the module after inlining, since it may be
referenced by another ThinLTO compiled object file. This is done by
changing LDPR_PREVAILING_DEF_IRONLY* symbols to LDPR_PREVAILING_DEF,
which converts the prevailing linkonce to weak. We also don't need the
other prevailing IRONLY handling for internalization, which is not
currently performed for ThinLTO.
Test case included.
Reviewers: davidxl, rafael
Subscribers: rafael, joker.eph, llvm-commits
Differential Revision: http://reviews.llvm.org/D16173
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262727
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Krzysztof Parzyszek [Fri, 4 Mar 2016 17:38:05 +0000 (17:38 +0000)]
[Hexagon] Fix lowering of calls with the return type of i1
This fixes an assertion in test/CodeGen/Hexagon/ifcvt-edge-weight.ll
when run with -debug-only=isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262726
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Zoran Jovanovic [Fri, 4 Mar 2016 17:34:31 +0000 (17:34 +0000)]
[mips][microMIPS] Prevent usage of OR16_MMR6 instruction when code for microMIPS is generated.
Author: milena.vujosevic.janicic
Reviewers: dsanders
Differential Revision: http://reviews.llvm.org/D17373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262725
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Teresa Johnson [Fri, 4 Mar 2016 17:06:02 +0000 (17:06 +0000)]
[ThinLTO] Launch importing backends in parallel threads from gold plugin
Summary:
Launch ThinLTO backends (LTO and codegen pipelines with importing) in
parallel using a ThreadPool, after creating the combined index.
The number of threads is controlled by the existing -jobs gold plugin
option, or the hardware concurrency if not specified.
The old behavior of exiting after creating the combined index can be
invoked via a new thinlto-index-only plugin option.
This commit involves just the ThinLTO-specific pieces of D15390, the NFC
and other restructuring pieces were committed independently:
r262677: Add hardware_concurrency interface to llvm::thread (NFC)
r262719: Change split code gen to use ThreadPool
r262721: Refactor gold-plugin codegen to prepare for ThinLTO threads (NFC)
Reviewers: pcc, joker.eph, rafael
Subscribers: rafael, davidxl, llvm-commits, joker.eph
Differential Revision: http://reviews.llvm.org/D15390
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262724
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Teresa Johnson [Fri, 4 Mar 2016 16:36:06 +0000 (16:36 +0000)]
Refactor gold-plugin codegen to prepare for ThinLTO threads (NFC)
This is the NFC part remaining from D15390, which refactors the
current codegen() into a CodeGen class with various modular methods and
other helper functions that will be used by the follow-on ThinLTO piece.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262721
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Teresa Johnson [Fri, 4 Mar 2016 15:39:13 +0000 (15:39 +0000)]
Change split code gen to use ThreadPool
Part of D15390.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262719
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Simon Pilgrim [Fri, 4 Mar 2016 15:19:42 +0000 (15:19 +0000)]
[X86][AVX512] Added some basic X86ISD::VPERMV3 shuffle combining tests
None of these actually combine yet as we haven't enabled X86ISD::VPERMV3 for target shuffle combining
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262718
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Sam Kolton [Fri, 4 Mar 2016 12:29:14 +0000 (12:29 +0000)]
Test commit access
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262714
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Simon Pilgrim [Fri, 4 Mar 2016 11:15:23 +0000 (11:15 +0000)]
[X86][SSSE3] Added combine test for unary shuffle (pshufb) only referencing elements from the second input of a binary shuffle (punpcklbw)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262710
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Valery Pykhtin [Fri, 4 Mar 2016 10:59:50 +0000 (10:59 +0000)]
test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262709
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Benjamin Kramer [Fri, 4 Mar 2016 10:49:30 +0000 (10:49 +0000)]
Make headers self-contained again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262702
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Nikolay Haustov [Fri, 4 Mar 2016 10:39:50 +0000 (10:39 +0000)]
AMDGPU/SI: add llvm.amdgcn.image.atomic.* intrinsics
These correspond to IMAGE_ATOMIC_* and are going to be used by Mesa for the
GL_ARB_shader_image_load_store extension.
Initial change by Nicolai H.hnle
Differential Revision: http://reviews.llvm.org/D17401
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262701
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Justin Bogner [Fri, 4 Mar 2016 01:52:47 +0000 (01:52 +0000)]
Annotate our undefined behaviour to sneak it past the sanitizers
We have known UB in some ilists where we static cast half nodes to
(larger) derived types and use the address. See llvm.org/PR26753.
This needs to be fixed, but in the meantime it'd be nice if running
ubsan didn't complain. This adds annotations in the two places where
ubsan complains while running check-all of a sanitized clang build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262683
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Easwaran Raman [Fri, 4 Mar 2016 01:18:40 +0000 (01:18 +0000)]
Fix a memory leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262682
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Justin Bogner [Fri, 4 Mar 2016 00:58:39 +0000 (00:58 +0000)]
CodeGen: Tune the SmallVector size in LiveRange
The vast majority of LiveRanges (ie, 4/5) have exactly 1 segment and 1
value number, and a good chunk of the rest have 2 of each, so
allocating space for 4 is wasteful. This is especially noticeable when
dealing with a very large number of vregs, and I have an internal case
where dropping this to 2 shaves over 5% off of peak memory when
compiling a particularly large function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262681
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Easwaran Raman [Fri, 4 Mar 2016 00:44:01 +0000 (00:44 +0000)]
Fix a use-after-free bug introduced in r262636
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262679
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Teresa Johnson [Fri, 4 Mar 2016 00:25:54 +0000 (00:25 +0000)]
Add hardware_concurrency interface to llvm::thread (NFC)
Part of D15390.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262677
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Evgeniy Stepanov [Fri, 4 Mar 2016 00:23:29 +0000 (00:23 +0000)]
[gold] Handle modules that are not included in the link.
Gold has a newly added LDPT_GET_SYMBOLS_V3 callback that can
distinguish between a module that is not included in the link, and
one that is included but has its entire interface preempted by others.
Fixes PR26674.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262676
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Easwaran Raman [Thu, 3 Mar 2016 23:55:41 +0000 (23:55 +0000)]
Fix memory leak in tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262674
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Mike Aizatsky [Thu, 3 Mar 2016 23:45:29 +0000 (23:45 +0000)]
[libfuzzer] arbitrary function adapter.
The adapter automates converting sequence of bytes into arbitrary
arguments.
Differential Revision: http://reviews.llvm.org/D17829
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262673
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Philip Reames [Thu, 3 Mar 2016 23:24:44 +0000 (23:24 +0000)]
[docs] Add a description of current problem areas to the statepoint docs
Triggered by a question on llvm-dev about status
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262671
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Guozhi Wei [Thu, 3 Mar 2016 23:21:38 +0000 (23:21 +0000)]
[InstCombine] Combine A->B->A BitCast
This patch enhances InstCombine to handle following case:
A -> B bitcast
PHI
B -> A bitcast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262670
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NAKAMURA Takumi [Thu, 3 Mar 2016 22:38:39 +0000 (22:38 +0000)]
llvm/test/CodeGen/ARM/rem_crash.ll: Avoid unsupported targets to specify explicit triple.
We will see it for targeting win32;
LLVM ERROR: CPU: 'generic' does not support ARM mode execution!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262668
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Kostya Serebryany [Thu, 3 Mar 2016 22:36:37 +0000 (22:36 +0000)]
[libFuzzer] when interrupted, call _Exit() instead of exit()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262667
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Simon Pilgrim [Thu, 3 Mar 2016 21:55:01 +0000 (21:55 +0000)]
[X86][AVX512BW] Fixed 512-bit PSHUFB shuffle mask decode and added combine test.
PSHUFB decoder was assuming that input was 128 or 256-bit vector only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262661
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Lang Hames [Thu, 3 Mar 2016 21:23:15 +0000 (21:23 +0000)]
[RuntimeDyld] Fix '_' stripping in RTDyldMemoryManager::getSymbolAddressInProcess.
The RTDyldMemoryManager::getSymbolAddressInProcess method accepts a
linker-mangled symbol name, but it calls through to dlsym to do the lookup (via
DynamicLibrary::SearchForAddressOfSymbol), and dlsym expects an unmangled
symbol name.
Historically we've attempted to "demangle" by removing leading '_'s on all
platforms, and fallen back to an extra search if that failed. That's broken, as
it can cause symbols to resolve incorrectly on platforms that don't do mangling
if you query '_foo' and the process also happens to contain a 'foo'.
Fix this by demangling conditionally based on the host platform. That's safe
here because this function is specifically for symbols in the host process, so
the usual cross-process JIT looking concerns don't apply.
M unittests/ExecutionEngine/ExecutionEngineTest.cpp
M lib/ExecutionEngine/RuntimeDyld/RTDyldMemoryManager.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262657
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Philip Reames [Thu, 3 Mar 2016 19:50:32 +0000 (19:50 +0000)]
[ValueTracking] "constant fold" an experimental hidden option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262648
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Philip Reames [Thu, 3 Mar 2016 19:44:06 +0000 (19:44 +0000)]
[ValueTracking] Remove dead code from an old experiment
This experiment was originally about trying to use facts implied dominating conditions to infer more precise known bits. While the compile time was found to be acceptable on several large code bases, we never found sufficiently profitable examples to justify turning on the code by default. Given this, it's time to abandon the experiment.
Several folks have commented that they've found this useful for experimentation, but nothing has come of those experiments. Given how easy the patch is to apply, there's no reason to leave the code in tree.
For anyone interested in further investigation in this area, I recommend finding the summary email I sent on one of the original review threads. In particular, I now believe the use-list based approach is strictly worse than the dom-tree-walking approach.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262646
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Sanjay Patel [Thu, 3 Mar 2016 19:19:04 +0000 (19:19 +0000)]
[InstCombine] transform bitcasted bitwise logic ops with constants (PR26702)
Given that we're not actually reducing the instruction count in the included
regression tests, I think we would call this a canonicalization step.
The motivation comes from the example in PR26702:
https://llvm.org/bugs/show_bug.cgi?id=26702
If we hoist the bitwise logic ahead of the bitcast, the previously unoptimizable
example of:
define <4 x i32> @is_negative(<4 x i32> %x) {
%lobit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
%not = xor <4 x i32> %lobit, <i32 -1, i32 -1, i32 -1, i32 -1>
%bc = bitcast <4 x i32> %not to <2 x i64>
%notnot = xor <2 x i64> %bc, <i64 -1, i64 -1>
%bc2 = bitcast <2 x i64> %notnot to <4 x i32>
ret <4 x i32> %bc2
}
Simplifies to the expected:
define <4 x i32> @is_negative(<4 x i32> %x) {
%lobit = ashr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
ret <4 x i32> %lobit
}
Differential Revision: http://reviews.llvm.org/D17583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@262645
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