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Alexandre Demers [Thu, 7 Jan 2021 23:53:03 +0000 (18:53 -0500)]
drm/amdgpu: fix DRM_INFO flood if display core is not supported (bug 210921)
This fix bug 210921 where DRM_INFO floods log when hitting an unsupported ASIC in
amdgpu_device_asic_has_dc_support(). This info should be only called once.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210921
Signed-off-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Fri, 8 Jan 2021 16:32:11 +0000 (11:32 -0500)]
drm/amdgpu/display: fix build with CONFIG_DRM_AMD_DC_DCN disabled
dc_allow_idle_optimizations() needs to be protected by
CONFIG_DRM_AMD_DC_DCN.
Fixes:
71338cb4a7c2 ("drm/amd/display: enable idle optimizations for linux (MALL stutter)")
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Tue, 29 Dec 2020 10:32:11 +0000 (18:32 +0800)]
drm/amd/pm: modify the fine grain tuning function for Renoir
This patch is to improve the fine grain tuning function for Renoir.
The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage
to config gfxclk. Meanwhile, another sysfs
node -- power_dpm_force_perfomance_level also affects the gfx clk.
It will cause confusion when these two sysfs nodes works
together.
And the flag "od_enabled" is used to control the overdrive function for
dGPU, like navi10, navi14 and navi21.
APU like Renior or Vangogh uses this "od_enabled" to configure
the frequency range of gfx clock, but the max value of frequency
range will not be higher than the safe limit, it is not "overdrive".
So this patch adds two new flags -- "fine_grain_enabled" and
"fine_grain_started" to avoid this confusion, the flag will
make these two sysfs nodes work separately.
The flag "fine_grain_enabled" is set as "enabled" by default,
so the fine grain tuning function will be enabled by default.
But the flag "fine_grain_started" is set as "false" by default,
so the fine grain function will not take effect until it is set as
"true".
Only when power_dpm_force_perfomance_level is changed to
"manual" mode, the flag "fine_grain_started" will be set as "true",
and the fine grain tuning function will be started.
In other profile modes, including "auto", "high", "low", "profile_peak",
"profile_standard", "profile_min_sclk", "profile_min_mclk",
the flag "fine_grain_started" will be set as "false", and the od range of
fine grain tuning function will be restored default value.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Thu, 7 Jan 2021 06:34:10 +0000 (14:34 +0800)]
drm/amd/pm: add the parameters of power profiles for vangogh
This pacth is to add the parameters of power profiles for vangogh,
includeing "profile_peak", "profile_standard", "profile_min_sclk",
"profile_min_mclk".
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Victor Zhao [Tue, 5 Jan 2021 07:04:01 +0000 (15:04 +0800)]
drm/amdgpu/psp: fix psp gfx ctrl cmds
psp GFX_CTRL_CMD_ID_CONSUME_CMD different for windows and linux,
according to psp, linux cmds are not correct.
v2: only correct GFX_CTRL_CMD_ID_CONSUME_CMD.
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Reviewed-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Wed, 6 Jan 2021 03:43:27 +0000 (11:43 +0800)]
drm/amdkfd: check more client ids in interrupt handler
Add check for SExSH clients in kfd interrupt handler.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily.Deng [Tue, 5 Jan 2021 03:21:25 +0000 (11:21 +0800)]
drm/amdgpu: Correct the read sclk for navi10
According to hw, after navi10,it runs in dfll mode, and should
read sclk from AverageGfxclkFrequency.
Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily.Deng [Fri, 11 Dec 2020 03:38:54 +0000 (11:38 +0800)]
drm/amdgpu: Add new mode 2560x1440
Add one more 2k resolution which appears frequently in market.
Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 5 Jan 2021 16:42:08 +0000 (11:42 -0500)]
Revert "drm/amd/display: Fix memory leaks in S3 resume"
This reverts commit
a135a1b4c4db1f3b8cbed9676a40ede39feb3362.
This leads to blank screens on some boards after replugging a
display. Revert until we understand the root cause and can
fix both the leak and the blank screen after replug.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211033
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1427
Cc: Stylon Wang <stylon.wang@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: Andre Tomt <andre@tomt.net>
Cc: Oleksandr Natalenko <oleksandr@natalenko.name>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Defang Bo [Tue, 5 Jan 2021 16:06:39 +0000 (00:06 +0800)]
drm/amdgpu: Add check to prevent IH overflow
Similar to commit <
b82175750131>("drm/amdgpu: fix IH overflow on Vega10 v2").
When an ring buffer overflow happens the appropriate bit is set in the WPTR
register which is also written back to memory. But clearing the bit in the
WPTR doesn't trigger another memory writeback.
So what can happen is that we end up processing the buffer overflow over and
over again because the bit is never cleared. Resulting in a random system
lockup because of an infinite loop in an interrupt handler.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Defang Bo <bodefang@126.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 4 Jan 2021 16:24:20 +0000 (11:24 -0500)]
drm/amdgpu/display: drop DCN support for aarch64
From Ard:
"Simply disabling -mgeneral-regs-only left and right is risky, given that
the standard AArch64 ABI permits the use of FP/SIMD registers anywhere,
and GCC is known to use SIMD registers for spilling, and may invent
other uses of the FP/SIMD register file that have nothing to do with the
floating point code in question. Note that putting kernel_neon_begin()
and kernel_neon_end() around the code that does use FP is not sufficient
here, the problem is in all the other code that may be emitted with
references to SIMD registers in it.
So the only way to do this properly is to put all floating point code in
a separate compilation unit, and only compile that unit with
-mgeneral-regs-only."
Disable support until the code can be properly refactored to support this
properly on aarch64.
Acked-by: Will Deacon <will@kernel.org>
Reported-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Tue, 5 Jan 2021 06:53:14 +0000 (14:53 +0800)]
drm/amdgpu: enable ras eeprom support for sienna cichlid
added I2C address and asic support flag
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Tue, 5 Jan 2021 00:37:21 +0000 (08:37 +0800)]
drm/amdgpu: fix no bad_pages issue after umc ue injection
old code wrongly used the bad page status as the function return value,
which cause amdgpu_ras_badpages_read always return failed.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiawei Gu [Tue, 29 Dec 2020 12:35:33 +0000 (20:35 +0800)]
drm/amdgpu: fix potential memory leak during navi12 deinitialization
Navi12 HDCP & DTM deinitialization needs continue to free bo if already
created though initialized flag is not set.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Mon, 28 Dec 2020 18:50:59 +0000 (19:50 +0100)]
drm/amd/display: Enable fp16 also on DCE-8/10/11.
The hw supports fp16, this is not only useful for HDR,
but also for standard dynamic range displays, because
it allows to get more precise color reproduction with
about 11 - 12 bpc linear precision in the unorm range
0.0 - 1.0.
Working fp16 scanout+display (and HDR over HDMI) was
verified on a DCE-8 asic, so i assume that the more
recent DCE-10/11 will work equally well, now that
format-specific plane scaling constraints are properly
enforced, e.g., the inability of fp16 to scale on older
hw like DCE-8 to DCE-11.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mario Kleiner [Mon, 28 Dec 2020 18:50:58 +0000 (19:50 +0100)]
drm/amd/display: Check plane scaling against format specific hw plane caps.
This takes hw constraints specific to pixel formats into account,
e.g., the inability of older hw to scale fp16 format framebuffers.
It should now allow safely to enable fp16 formats also on DCE-8,
DCE-10, DCE-11.0
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 4 Dec 2020 20:10:46 +0000 (15:10 -0500)]
drm/amdgpu: take runtime pm reference when we attach a buffer
And drop it when we detach. If the shared buffer is in vram,
we need to make sure we don't put the device into runtime
suspend.
Acked-by: Shashank Sharma <shashank.sharma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Tue, 22 Sep 2020 16:01:17 +0000 (12:01 -0400)]
drm/amd/display: Create and Destroy PSR resources for DCN302
We need these to support PSR on DCN302
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Thu, 30 Jul 2020 21:03:49 +0000 (17:03 -0400)]
drm/amd/display: enable idle optimizations for linux (MALL stutter)
[Why]
We can only use this feature when the display is idle. When active vblank
irq count is 0 we know all the displays are idle.
[How]
-Add a active vblank irq counter
-Update the counter when we enable/disable vblank irq
-if vblank irq count is 0 we can consider mall stutter
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nick Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joshua Aberback [Mon, 31 Aug 2020 05:58:03 +0000 (01:58 -0400)]
drm/amd/display: Update idle optimization handling
[How]
- use dc interface instead of hwss interface in cursor functions, to keep
dc->idle_optimizations_allowed updated
- add dc interface to check if idle optimizations might apply to a plane
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Arnd Bergmann [Sun, 3 Jan 2021 14:02:32 +0000 (15:02 +0100)]
drm/amd/display: Fix unused variable warning
Some of the newly added code is hidden inside of #ifdef
blocks, but one variable is unused when debugfs is disabled:
drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:8370:8: error: unused variable 'configure_crc' [-Werror,-Wunused-variable]
Change the #ifdef to an if(IS_ENABLED()) check to fix the warning
and avoid adding more #ifdefs.
Fixes:
c920888c604d ("drm/amd/display: Expose new CRC window property")
Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tian Tao [Tue, 29 Dec 2020 02:55:47 +0000 (10:55 +0800)]
drm/amd/display: fix comparison pointer to bool warning in dc.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/core/dc.c:1543:12-19: WARNING: Comparison
to bool
drivers/gpu/drm/amd/display/dc/core/dc.c:1496:14-42: WARNING: Comparison
to bool
drivers/gpu/drm/amd/display/dc/core/dc.c:971:15-48: WARNING: Comparison
to bool
drivers/gpu/drm/amd/display/dc/core/dc.c:976:15-44: WARNING: Comparison
to bool
Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chenyang Li [Sat, 26 Dec 2020 08:56:07 +0000 (16:56 +0800)]
drm/amdgpu: Fix macro name _AMDGPU_TRACE_H_ in preprocessor if condition
Add an underscore in amdgpu_trace.h line 24 "_AMDGPU_TRACE_H".
Fixes:
d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)")
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Chenyang Li <lichenyang@loongson.cn>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zheng Yongjun [Tue, 22 Dec 2020 13:31:00 +0000 (21:31 +0800)]
gpu/drm/radeon: use DIV_ROUND_UP macro to do calculation
Don't open-code DIV_ROUND_UP() kernel macro.
Signed-off-by: Zheng Yongjun <zhengyongjun3@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tian Tao [Mon, 21 Dec 2020 11:16:35 +0000 (19:16 +0800)]
drm/amd/display: remove useless else if
Fix the following coccinelle report:
drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c:1357:6-8:
WARNING: possible condition with no effect (if == else)
Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tian Tao [Thu, 31 Dec 2020 00:56:17 +0000 (08:56 +0800)]
drm/amd/display: remove unused including <linux/version.h>
Remove including <linux/version.h> that don't need it.
Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Tue, 29 Dec 2020 09:19:37 +0000 (17:19 +0800)]
drm/amd/pm: improve the fine grain tuning function for RV/RV2/PCO
This patch is to improve the fine grain tuning function for RV/RV2/PCO.
The fine grain tuning function uses the sysfs node -- pp_od_clk_voltage
to config gfxclk. Meanwhile, another sysfs
node -- power_dpm_force_perfomance_level also affects the gfx clk.
It will cause confusion when these two sysfs nodes works
together. So this patch adds one flag to avoid this confusion, the flag
will make these two sysfs nodes work separately.
The flag is set as "disabled" by default, so the fine grain tuning function
will be disabled by default.
Only when power_dpm_force_perfomance_level is changed to
"manual" mode, the flag will be set as "enabled",
and the fine grain tuning function will be enabled.
In other profile modes, including "auto", "high", "low",
"profile_peak", "profile_standard", "profile_min_sclk",
"profile_min_mclk", the flag will be set as "disabled",
and the od range of fine grain tuning function will
be restored default value.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Thu, 31 Dec 2020 07:47:40 +0000 (15:47 +0800)]
drm/amd/pm: enable dclk/vclk dpm function in "auto" power profile for vangogh
This patch is to enable dclk/vclk dpm function in "auto" power profile
for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
pengzhou [Wed, 16 Dec 2020 05:14:15 +0000 (13:14 +0800)]
drm/amdgpu: do optimization for psp command submit
In the psp command submit logic,
the function msleep(1) delayed too long,
Changing it to usleep_range(10, 100) to
have a better performance.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Wed, 30 Dec 2020 10:08:23 +0000 (18:08 +0800)]
drm/amd/pm: fix the failure when change power profile for renoir
This patch is to fix the failure when change power profile to
"profile_peak" for renoir.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 4 Jan 2021 09:30:46 +0000 (17:30 +0800)]
drm/amdgpu: remove redundant include of navi10_enum
Remove unnecessary include of navi10_enum header file.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 28 Dec 2020 09:04:06 +0000 (17:04 +0800)]
drm/amdgpu: remove redundant logic related HDP
Remove hdp_flush function from amdgpu_nbio struct as it have been unified
into hdp struct.
Remove the include about hdp register which was not used.
V2: Remove hdp golden setting which is unnecessary.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 28 Dec 2020 09:02:21 +0000 (17:02 +0800)]
drm/amdgpu: switch hdp callback functions for hdp v5
Switch to use the HDP functions which unified on hdp structure instead of
the scattered hdp callback functions.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 28 Dec 2020 08:54:16 +0000 (16:54 +0800)]
drm/amdgpu: switch hdp callback functions for hdp v4
Switch to use the HDP functions which unified on hdp structure instead of
the scattered hdp callback functions.
V2: clean up hdp reset ras error count function.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 28 Dec 2020 08:46:55 +0000 (16:46 +0800)]
drm/amdgpu: add hdp version 5 functions
Unify hdp related function into hdp structure for hdp version 5.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 28 Dec 2020 08:42:40 +0000 (16:42 +0800)]
drm/amdgpu: add hdp version 4 functions
Unify hdp related function into hdp structure for hdp version 4.
V2: Add function to remap hdp registers for nbio version 6.1
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 24 Dec 2020 07:49:18 +0000 (15:49 +0800)]
drm/amdgpu: add amdgpu_hdp structure
amdgpu_hdp hold all the callbacks for hdp
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiawei Gu [Wed, 23 Dec 2020 05:54:57 +0000 (13:54 +0800)]
drm/amdgpu: fix potential NULL pointer when check_atom_bios() fails
Asic funcs pointer needs being checked whether is NULL. Because when
check_atom_bios() fails in req_init_data handshake, asic funcs pointer
is not initialized yet.
Signed-off-by: Jiawei Gu <Jiawei.Gu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chen Li [Fri, 25 Dec 2020 03:58:00 +0000 (11:58 +0800)]
drm/amdgpu: use GTT for uvd_get_create/destory_msg
On modern gpus, GTT (system memory) works as well here, and this may
also be a workaround for platforms which cannot map vram correctly.
Signed-off-by: chenli <chenli@uniontech.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chen Li [Fri, 25 Dec 2020 03:54:57 +0000 (11:54 +0800)]
drm/radeon: use writel to avoid gcc optimization v3
When using e8860(gcn1) on arm64, the kernel crashed on drm/radeon:
[ 11.240414] pc : __memset+0x4c/0x188
[ 11.244101] lr : radeon_uvd_get_create_msg+0x114/0x1d0 [radeon]
[ 11.249995] sp :
ffff00000d7eb700
[ 11.253295] x29:
ffff00000d7eb700 x28:
ffff8001f632a868
[ 11.258585] x27:
0000000000040000 x26:
ffff00000de00000
[ 11.263875] x25:
0000000000000125 x24:
0000000000000001
[ 11.269168] x23:
0000000000000000 x22:
0000000000000005
[ 11.274459] x21:
ffff00000df24000 x20:
ffff8001f74b4000
[ 11.279753] x19:
0000000000124000 x18:
0000000000000020
[ 11.285043] x17:
0000000000000000 x16:
0000000000000000
[ 11.290336] x15:
ffff000009309000 x14:
ffffffffffffffff
[ 11.290340] x13:
ffff0000094b6f88 x12:
ffff0000094b6bd2
[ 11.290343] x11:
ffff00000d7eb700 x10:
ffff00000d7eb700
[ 11.306246] x9 :
ffff00000d7eb700 x8 :
ffff00000df2402c
[ 11.306254] x7 :
0000000000000000 x6 :
ffff0000094b626a
[ 11.306257] x5 :
0000000000000000 x4 :
0000000000000004
[ 11.306262] x3 :
ffffffffffffffff x2 :
0000000000000fd4
[ 11.306265] x1 :
0000000000000000 x0 :
ffff00000df2402c
[ 11.306272] Call trace:
[ 11.306316] __memset+0x4c/0x188
[ 11.306638] uvd_v1_0_ib_test+0x70/0x1c0 [radeon]
[ 11.306758] radeon_ib_ring_tests+0x54/0xe0 [radeon]
...
Obviously, the __memset call is generated by gcc(8.3.1). It optimizes
this for loop into memset. But this may break on some platforms which
cannot map device memory correctly. So, just invoke `writel` to handle this.
v3 (chk): minor cleanups in code and commit message
Signed-off-by: Chen Li <chenli@uniontech.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Wed, 30 Dec 2020 11:45:15 +0000 (19:45 +0800)]
drm/amdgpu: fix a GPU hang issue when remove device
When GFXOFF is enabled and GPU is idle, driver will fail to access some
registers. Therefore change to disable power gating before all access
registers with MMIO.
Dmesg log is as following:
amdgpu 0000:03:00.0: amdgpu: amdgpu: finishing device.
amdgpu: cp queue pipe 4 queue 0 preemption failed
amdgpu 0000:03:00.0: amdgpu: failed to write reg 2890 wait reg 28a2
amdgpu 0000:03:00.0: amdgpu: failed to write reg 1a6f4 wait reg 1a706
amdgpu 0000:03:00.0: amdgpu: failed to write reg 2890 wait reg 28a2
amdgpu 0000:03:00.0: amdgpu: failed to write reg 1a6f4 wait reg 1a706
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dennis Li [Wed, 30 Dec 2020 02:27:42 +0000 (10:27 +0800)]
drm/amdgpu: fix a memory protection fault when remove amdgpu device
ASD and TA share the same firmware in SIENNA_CICHLID and only TA
firmware is requested during boot, so only need release TA firmware when
remove device.
[ 83.877150] general protection fault, probably for non-canonical address 0x1269f97e6ed04095: 0000 [#1] SMP PTI
[ 83.888076] CPU: 0 PID: 1312 Comm: modprobe Tainted: G W OE
5.9.0-rc5-deli-amd-vangogh-0.0.6.6-114-gdd99d5669a96-dirty #2
[ 83.901160] Hardware name: System manufacturer System Product Name/TUF Z370-PLUS GAMING II, BIOS 0411 09/21/2018
[ 83.912353] RIP: 0010:free_fw_priv+0xc/0x120
[ 83.917531] Code: e8 99 cd b0 ff b8 a1 ff ff ff eb 9f 4c 89 f7 e8 8a cd b0 ff b8 f4 ff ff ff eb 90 0f 1f 00 0f 1f 44 00 00 55 48 89 e5 41 54 53 <4c> 8b 67 18 48 89 fb 4c 89 e7 e8 45 94 41 00 b8 ff ff ff ff f0 0f
[ 83.937576] RSP: 0018:
ffffbc34c13a3ce0 EFLAGS:
00010206
[ 83.943699] RAX:
ffffffffbb681850 RBX:
ffffa047f117eb60 RCX:
0000000080800055
[ 83.951879] RDX:
ffffbc34c1d5f000 RSI:
0000000080800055 RDI:
1269f97e6ed04095
[ 83.959955] RBP:
ffffbc34c13a3cf0 R08:
0000000000000000 R09:
0000000000000001
[ 83.968107] R10:
ffffbc34c13a3cc8 R11:
00000000ffffff00 R12:
ffffa047d6b23378
[ 83.976166] R13:
ffffa047d6b23338 R14:
ffffa047d6b240c8 R15:
0000000000000000
[ 83.984295] FS:
00007f74f6712540(0000) GS:
ffffa047fbe00000(0000) knlGS:
0000000000000000
[ 83.993323] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 84.000056] CR2:
0000556a1cca4e18 CR3:
000000021faa8004 CR4:
00000000003706f0
[ 84.008128] DR0:
0000000000000000 DR1:
0000000000000000 DR2:
0000000000000000
[ 84.016155] DR3:
0000000000000000 DR6:
00000000fffe0ff0 DR7:
0000000000000400
[ 84.024174] Call Trace:
[ 84.027514] release_firmware.part.11+0x4b/0x70
[ 84.033017] release_firmware+0x13/0x20
[ 84.037803] psp_sw_fini+0x77/0xb0 [amdgpu]
[ 84.042857] amdgpu_device_fini+0x38c/0x5d0 [amdgpu]
[ 84.048815] amdgpu_driver_unload_kms+0x43/0x70 [amdgpu]
[ 84.055055] drm_dev_unregister+0x73/0xb0 [drm]
[ 84.060499] drm_dev_unplug+0x28/0x30 [drm]
[ 84.065598] amdgpu_dev_uninit+0x1b/0x40 [amdgpu]
[ 84.071223] amdgpu_pci_remove+0x4e/0x70 [amdgpu]
[ 84.076835] pci_device_remove+0x3e/0xc0
[ 84.081609] device_release_driver_internal+0xfb/0x1c0
[ 84.087558] driver_detach+0x4d/0xa0
[ 84.092041] bus_remove_driver+0x5f/0xe0
[ 84.096854] driver_unregister+0x2f/0x50
[ 84.101594] pci_unregister_driver+0x22/0xa0
[ 84.106806] amdgpu_exit+0x15/0x2b [amdgpu]
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Thu, 31 Dec 2020 05:05:09 +0000 (13:05 +0800)]
drm/amdgpu: switched to cached noretry setting for vangogh
global noretry setting is cached to gmc.noretry
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Wed, 30 Dec 2020 11:40:49 +0000 (19:40 +0800)]
drm/amdgpu: remove unnecessary asic check for sdma5.2
For sdma5.2, all sdma instances will share the same fw,
remove unnecessary asic check to be more generic.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Tue, 29 Dec 2020 06:10:28 +0000 (14:10 +0800)]
drm/amd/display: fix sysfs amdgpu_current_backlight_pwm NULL pointer issue
fix NULL pointer issue when read sysfs amdgpu_current_backlight_pwm sysfs node.
Call Trace:
[ 248.273833] BUG: kernel NULL pointer dereference, address:
0000000000000130
[ 248.273930] #PF: supervisor read access in kernel mode
[ 248.273993] #PF: error_code(0x0000) - not-present page
[ 248.274054] PGD 0 P4D 0
[ 248.274092] Oops: 0000 [#1] SMP PTI
[ 248.274138] CPU: 2 PID: 1377 Comm: cat Tainted: G OE 5.9.0-rc5-drm-next-5.9+ #1
[ 248.274233] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 3802 03/15/2018
[ 248.274641] RIP: 0010:dc_link_get_backlight_level+0x5/0x70 [amdgpu]
[ 248.274718] Code: 67 ff ff ff 41 b9 03 00 00 00 e9 45 ff ff ff d1 ea e9 55 ff ff ff 0f 1f 44 00 00 66 2e
0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 <48> 8b 87 30 01 00 00 48 8b 00 48 8b 88 88 03 00 00 48 8d 81 e8 01
[ 248.274919] RSP: 0018:
ffffb5ad809b3df0 EFLAGS:
00010203
[ 248.274982] RAX:
ffffa0f77d1c0010 RBX:
ffffa0f793ae9168 RCX:
0000000000000001
[ 248.275064] RDX:
ffffa0f79753db00 RSI:
0000000000000001 RDI:
0000000000000000
[ 248.275145] RBP:
ffffb5ad809b3e00 R08:
ffffb5ad809b3da0 R09:
0000000000000000
[ 248.275225] R10:
ffffb5ad809b3e68 R11:
0000000000000000 R12:
ffffa0f793ae9190
[ 248.275306] R13:
ffffb5ad809b3ef0 R14:
0000000000000001 R15:
ffffa0f793ae9168
[ 248.275388] FS:
00007f5f1ec4d540(0000) GS:
ffffa0f79ec80000(0000) knlGS:
0000000000000000
[ 248.275480] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 248.275547] CR2:
0000000000000130 CR3:
000000042a03c005 CR4:
00000000003706e0
[ 248.275628] DR0:
0000000000000000 DR1:
0000000000000000 DR2:
0000000000000000
[ 248.275708] DR3:
0000000000000000 DR6:
00000000fffe0ff0 DR7:
0000000000000400
[ 248.275789] Call Trace:
[ 248.276124] ? current_backlight_read+0x24/0x40 [amdgpu]
[ 248.276194] seq_read+0xc3/0x3f0
[ 248.276240] full_proxy_read+0x5c/0x90
[ 248.276290] vfs_read+0xa7/0x190
[ 248.276334] ksys_read+0xa7/0xe0
[ 248.276379] __x64_sys_read+0x1a/0x20
[ 248.276429] do_syscall_64+0x37/0x80
[ 248.276477] entry_SYSCALL_64_after_hwframe+0x44/0xa9
[ 248.276538] RIP: 0033:0x7f5f1e75c191
[ 248.276585] Code: fe ff ff 48 8d 3d b7 9d 0a 00 48 83 ec 08 e8 46 4d 02 00 66 0f 1f 44 00 00 48 8d 05 71 07
2e 00 8b 00 85 c0 75 13 31 c0 0f 05 <48> 3d 00 f0 ff ff 77 57 f3 c3 0f 1f 44 00 00 41 54 55 49 89 d4 53Hw
[ 248.276784] RSP: 002b:
00007ffcb1fc3f38 EFLAGS:
00000246 ORIG_RAX:
0000000000000000
[ 248.276872] RAX:
ffffffffffffffda RBX:
0000000000020000 RCX:
00007f5f1e75c191
[ 248.276953] RDX:
0000000000020000 RSI:
00007f5f1ec2b000 RDI:
0000000000000003
[ 248.277034] RBP:
0000000000020000 R08:
00000000ffffffff R09:
0000000000000000
[ 248.277115] R10:
0000000000000022 R11:
0000000000000246 R12:
00007f5f1ec2b000
[ 248.277195] R13:
0000000000000003 R14:
00007f5f1ec2b00f R15:
0000000000020000
[ 248.277279] Modules linked in: amdgpu(OE) iommu_v2 gpu_sched ttm(OE) drm_kms_helper cec drm
i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs
lockd grace fscache nls_iso8859_1 snd_hda_codec_realtek snd_hda_codec_hdmi snd_hda_codec_generic
ledtrig_audio intel_rapl_msr intel_rapl_common snd_hda_intel snd_intel_dspcfg x86_pkg_temp_thermal
intel_powerclamp snd_hda_codec snd_hda_core snd_hwdep snd_pcm snd_seq_midi snd_seq_midi_event mei_hdcp
coretemp snd_rawmidi snd_seq kvm_intel kvm snd_seq_device snd_timer irqbypass joydev snd input_leds soundcore
crct10dif_pclmul crc32_pclmul ghash_clmulni_intel aesni_intel crypto_simd cryptd glue_helper rapl intel_cstate
mac_hid mei_me serio_raw mei eeepc_wmi wmi_bmof asus_wmi mxm_wmi intel_wmi_thunderbolt acpi_pad sparse_keymap
efi_pstore sch_fq_codel parport_pc ppdev lp parport sunrpc ip_tables x_tables autofs4 hid_logitech_hidpp
hid_logitech_dj hid_generic usbhid hid e1000e psmouse ahci libahci wmi video
[ 248.278211] CR2:
0000000000000130
[ 248.278221] ---[ end trace
1fbe72fe6f91091d ]---
[ 248.357226] RIP: 0010:dc_link_get_backlight_level+0x5/0x70 [amdgpu]
[ 248.357272] Code: 67 ff ff ff 41 b9 03 00 00 00 e9 45 ff ff ff d1 ea e9 55 ff ff ff 0f 1f 44 00 00 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 <48> 8b 87 30 01 00 00 48 8b 00 48 8b 88 88 03 00 00 48 8d 81 e8 01
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Thu, 24 Dec 2020 10:04:30 +0000 (18:04 +0800)]
drm/amd/pm: add support to umd P-state function for vangogh
This patch is to add support to umd P-state function for vangogh.
It enables the "set" function of 3 sysfs nodes: pp_dpm_mclk,
pp_dpm_fclk, pp_dpm_socclk, the functions is used to set the DPM
frequency level of memclk/fclk/socclk.
Due to only after enabling the "power_dpm_force_performance_level"
sysfs node, it is allowed to set these three nodes,
so this patch also enables the "powe_dpm_force_performance_level"
sysfs node, which is used to change power profile.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Thu, 24 Dec 2020 09:59:59 +0000 (17:59 +0800)]
drm/amd/pm: add some basic functions to support umd P-state function for vangogh.
This patch is to add some basic functions to support
umd P-state function for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Thu, 24 Dec 2020 09:36:42 +0000 (17:36 +0800)]
drm/amd/pm: add some basic functions to support umd P-state function for vangogh.
This patch is to add some basic functions to support umd
P-state function for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Fri, 18 Dec 2020 08:07:14 +0000 (16:07 +0800)]
drm/amd/pm: enable the fine grain tuning function for renoir
This patch is to enable the fine grain tuning function for renoir.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Thu, 24 Dec 2020 08:19:19 +0000 (16:19 +0800)]
drm/amd/pm: add the fine grain tuning function for renoir
This patch is to add the fine grain tuning function for renoir.
This function uses the pp_od_clk_voltage sysfs file to configure the min
and max value of gfx clock frequency manually or restore the default value.
Command guide:
echo "s level value" > pp_od_clk_voltage
"s" - set the sclk frequency
"level" - 0 or 1, "0" represents the min value, "1" represents
the max value
"value" - the target value of sclk frequency, it should
be limited in the safe range
echo "r" > pp_od_clk_voltage
"r" - reset the sclk frequency, restore the default value instantly
echo "c" > pp_od_clk_voltage
"c" - commit the min and max value of sclk frequency to the system
only after the commit command, the target values set by "s" command
will take effect.
Example:
1)change power profile from "auto" to "standard"
$ cat power_dpm_force_performance_level
auto
$ echo "profile_standard" > power_dpm_force_performance_level
$ cat power_dpm_force_performance_level
profile_standard
2)check the default sclk frequency
$ cat pp_od_clk_voltage
OD_SCLK:
0: 200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
3)use "s" -- set command to configure the min and max sclk frequency
$ echo "s 0 600" > pp_od_clk_voltage
$ echo "s 1 1000" > pp_od_clk_voltage
$ echo "c" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0: 600Mhz
1: 1000Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
4)use "r" -- reset command to restore the min or max sclk frequency
$ echo "r" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0: 200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Fri, 25 Dec 2020 04:22:51 +0000 (12:22 +0800)]
drm/amd/pm: updated PM to I2C controller port on sienna cichlid
sienna cichlid interfaces with RAS eeprom on I2C controller port 1
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Fri, 18 Dec 2020 06:32:02 +0000 (14:32 +0800)]
drm/amd/pm: improve the fine grain tuning function for RV/RV2/PCO
This patch is to improve the fine grain tuning function for RV/RV2/PCO.
This patch adds two new commands: "restore" and "commit".
This function uses the pp_od_clk_voltage sysfs file to configure the min
and max value of gfx clock frequency manually or restore the default value.
Command guide:
echo "s level value" > pp_od_clk_voltage
"s" - set the sclk frequency
"level" - 0 or 1, "0" represents the min value, "1" represents
the max value
"value" - the target value of sclk frequency, it should be limited in the
safe range
echo "r" > pp_od_clk_voltage
"r" - reset the sclk frequency, restore the default value instantly
echo "c" > pp_od_clk_voltage
"c" - commit the min and max value of sclk frequency to the system
only after the commit command, the target values set by "s" command
will take effect.
Example:
1)change power profile from "auto" to "manual"
$ cat power_dpm_force_performance_level
auto
$ echo "manual" > power_dpm_force_performance_level
$ cat power_dpm_force_performance_level
manual
2)check the default sclk frequency
$ cat pp_od_clk_voltage
OD_SCLK:
0: 200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
3)use "s" -- set command to configure the min and max sclk frequency
$ echo "s 0 600" > pp_od_clk_voltage
$ echo "s 1 1000" > pp_od_clk_voltage
$ echo "c" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0: 600Mhz
1: 1000Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
4)use "r" -- reset command to restore the min or max sclk frequency
$ echo "r" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0: 200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Thu, 24 Dec 2020 08:11:33 +0000 (16:11 +0800)]
drm/amd/pm: enable the "fetch" function of pp_dpm_vclk/dclk for vangogh
This patch is to enable the "fetch" function of pp_dpm_vclk and
pp_dpm_dclk.
It allows to fetch the current frequency of vcn and dcn and their
DPM levels for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Wed, 16 Dec 2020 06:44:10 +0000 (14:44 +0800)]
drm/amd/pm: add two new sysfs nodes for vangogh
This patch is to add two new sysfs nodes for vangogh:
pp_dpm_dclk and pp_dpm_vclk.
The two sysfs nodes are similar to pp_dpm_fclk/memclk/socclk.
pp_dpm_dclk represents the DPM frequency of dcn unit.
pp_dpm_vclk represents the DPM frequency of vcn unit.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Wed, 16 Dec 2020 03:26:43 +0000 (11:26 +0800)]
drm/amd/pm: add new feature map macros to resolve duplicate name
This patch is to add new feature map macros to resolve duplicate name.
Vangogh uses one different format to name some feature bits of swSMU, it
causes some duplicate name in the existing feature map list.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Tue, 15 Dec 2020 08:41:26 +0000 (16:41 +0800)]
drm/amd/pm: add support to umd P-state "fetch" function for vangogh
This patch is to add supoort to umd P-state function for vangogh.
It enables the "fetch" function of 3 sysfs nodes: pp_dpm_mclk,
pp_dpm_fclk, pp_dpm_socclk,the function is used to fetch
the current frequency of memclk/fclk/socclk.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojian Du [Mon, 14 Dec 2020 09:05:55 +0000 (17:05 +0800)]
drm/amd/pm: correct the sensor value of power for vangogh
This patch is to correct the sensor value of power for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 22 Dec 2020 10:16:11 +0000 (18:16 +0800)]
drm/amdgpu: drop psp ih programming for sriov guest on navi
the psp access ih path is not needed in navi
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jane Jian <Jane.Jian@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Markus Elfring [Sat, 19 Dec 2020 17:18:59 +0000 (18:18 +0100)]
drm/amd/display: Use common error handling code in dc_create()
Adjust a jump target so that a bit of exception handling can be better
reused at the end of this function.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Markus Elfring [Sat, 19 Dec 2020 17:04:33 +0000 (18:04 +0100)]
drm/amd/display: Return directly after a failed kzalloc() in dc_create()
* Return directly after a call of the function “kzalloc” failed
at the beginning.
* Delete a label which became unnecessary with this refactoring.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 18 Dec 2020 21:31:18 +0000 (16:31 -0500)]
drm/amdkfd: check both client id and src id in interrupt handlers
We can have the same src ids for different client ids so make sure to
check both the client id and the source id when handling interrupts.
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 18 Dec 2020 16:49:16 +0000 (11:49 -0500)]
drm/amdgpu: fix handling of irq domains on soc15 and newer GPUs
We need to take into account the client id otherwise we'll end
up sending generic events for any src id that is registered.
We only support irq domains on pre-soc15 parts so client is
always legacy.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 21 Dec 2020 05:39:40 +0000 (13:39 +0800)]
drm/amdgpu: de-initialize software ih ring
tear down software ih ring and its state.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 21 Dec 2020 03:46:58 +0000 (11:46 +0800)]
drm/amdgpu: set ih soft ring enabled flag for vega and navi
software ih ring is enabled in vega10 and navi
ih block by default.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 21 Dec 2020 03:18:14 +0000 (11:18 +0800)]
drm/amdgpu: enable software ih ring for vega20 ih block
software ih ring will be used as a workaround
in case hardware ih ring 1 and ring 2 don't work
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 19 Nov 2020 09:30:43 +0000 (17:30 +0800)]
drm/amd/pm: support overdrive vddgfx offset setting(V2)
This is supported by Sienna Cichlid, Navy Flounder and Dimgrey
Cavefish. For these ASICs, the target voltage calculation can be
illustrated by "voltage = voltage calculated from v/f curve +
overdrive vddgfx offset".
V2: limit the smu_version check for Sienna Cichlid only
Here are some sample usages about this new OD setting:
1. Check current vddgfx offset setting by
cat /sys/class/drm/card0/device/pp_od_clk_voltage
...
...
OD_VDDGFX_OFFSET:
0mV
...
...
2. Set new vddgfx offset by
echo "vo 10" > /sys/class/drm/card0/device/pp_od_clk_voltage
cat /sys/class/drm/card0/device/pp_od_clk_voltage
...
...
OD_VDDGFX_OFFSET:
10mV
...
...
3. Commit the new setting by
echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 19 Nov 2020 07:56:28 +0000 (15:56 +0800)]
drm/amd/pm: enable Sienna Cichlid overdrive support
Enable Sienna Cichlid gfxclk/uclk overdrive support.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 19 Nov 2020 07:53:47 +0000 (15:53 +0800)]
drm/amd/pm: populate Sienna Cichlid default overdrive table settings
Populate the bootup overdrive table settings.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jinzhou Su [Thu, 17 Dec 2020 09:37:38 +0000 (17:37 +0800)]
drm/amd/pm: Add interface for request WGPs
When user specifies a reduced WGP(CU) config via disalbe_cu module
parameter, this does not disable the clocks which uses additional
power. This interface send active WGP number to SMU and SMU will
cooperate with RLC to power off relative WGPs.
v2: Add request active WGPs in Vangogh smu post init.
Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ryan Taylor [Wed, 16 Dec 2020 17:59:55 +0000 (09:59 -0800)]
drm/amd/pm: add pptable_funcs documentation (v3)
Documents the hooks in struct pptable_funcs.
v2: Improved documentation accuracy.
v3: Improved set_default_od_settings() definition.
Signed-off-by: Ryan Taylor <Ryan.Taylor@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 12 Dec 2020 15:04:08 +0000 (23:04 +0800)]
drm/amdgpu: don't create ih ring 1 and ring 2 for APU
APUs don't support ih ring 1 and ring 2.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Sat, 12 Dec 2020 14:16:58 +0000 (22:16 +0800)]
drm/amdgpu: drop ih reroute function from psp v11
For all the ASICs that integrate psp v11, vega20
doesn't support ih reroute. arcturus and later will
allow kernel driver to program ih_cfg_index/data
through mmio directly. navi1x and onwards will only
support grb_ih_set command in sriov configuration.
psp_v11_0_reroute_ih is not needed any more.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 16:23:16 +0000 (00:23 +0800)]
drm/amdgpu: drop IH_CHICKEN programming from vega10 ih block
except for RENOIR, it is not correct to have
IH_CHICKEN programming in vega10 ih block.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 16:04:36 +0000 (00:04 +0800)]
drm/amdgpu: correct ih_chicken programming for vega10/vega20 ih blocks
IH_CHICKEN.MC_SPACE_FBPA_ENABLE field is only
valid when IH_RB_CNTL.MC_SPACE is programed to 0x3,
frame buffer physical address. For both bus address
and gpu virtual address, don't program MC_SPACE_FBPA_ENABLE
field
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 9 Dec 2020 05:49:01 +0000 (13:49 +0800)]
drm/amdgpu: retire the vega20 code path from navi10 ih block
already switched to vega20 ih block for vega20
and arcturus. no need to add vega20 support in
navi10 ih block
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 15:36:57 +0000 (23:36 +0800)]
drm/amdgpu: switch to vega20 ih block for vega20/arcturus
replace navi10 ih block with vega20 ih block for
vega20 and arcturus
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 9 Dec 2020 05:47:20 +0000 (13:47 +0800)]
drm/amdgpu: reroute vmc/utcl2 interrupts to ih ring 1 for arcturus
in case page faults overwhlem the interrupt handlers
and the driver lost the valuable interrupt information
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Fri, 18 Dec 2020 13:48:59 +0000 (21:48 +0800)]
drm/amdgpu: create vega20 ih blocks
vega20 ih blocks will be used for vega20/arcturus
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 8 Dec 2020 09:22:30 +0000 (17:22 +0800)]
drm/amdgpu: add osssys v4_2 ip headers (v2)
v1: add osssys v4_2 register offset and shift masks
header files. vega20 and arcturus will refer to
these ip headers. (Hawking)
v2: clean up osssys v4_2 registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Hawking Zhang [Wed, 25 Nov 2020 07:29:42 +0000 (15:29 +0800)]
drm/amdgpu: switch to common decode iv helper
The iv format is the same for all the soc15 adpater
and onwards and can share a common function to
decode iv.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 25 Nov 2020 07:25:51 +0000 (15:25 +0800)]
drm/amdgpu: add a helper function to decode iv
since from soc15, all the chips share the same
iv format. create a common helper to decode iv
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:30:12 +0000 (23:30 +0800)]
drm/amdgpu: use cached ih rb control reg offsets for navi10
all the ih rb control register offsets are cached
at the beginning of navi10 ih_sw_init.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 9 Dec 2020 05:36:32 +0000 (13:36 +0800)]
drm/amdgpu: switch to ih_enable_ring for navi10
use navi10_ih_enable_ring to enable all the
available ring buffers for navi1x and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:23:16 +0000 (23:23 +0800)]
drm/amdgpu: switch to ih_toggle_interrupts for navi10
replace ih_enable_interrupts and ih_disable_interrupts
with ih_toggle_interrupts
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:20:55 +0000 (23:20 +0800)]
drm/amdgpu: switch to ih_init_register_offset for navi10
Initialize ih control registers offset through helper
function navi10_ih_init_register_offset.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:19:03 +0000 (23:19 +0800)]
drm/amdgpu: add helper to toggle ih ring interrupts for navi10
navi10_ih_toggle_ring_interrupts will be used to
enable/disable an ih ring interrupts for navi1x
and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:17:13 +0000 (23:17 +0800)]
drm/amdgpu: add helper to enable an ih ring for navi10
navi10_ih_enable_ring will be used to enable an
ih ring for navi1x and onwards
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:15:32 +0000 (23:15 +0800)]
drm/amdgpu: add helper to init ih ring regs for navi10
navi10_ih_init_register_offset will be used to init
register offset for all the available ih rings
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 30 Nov 2020 14:49:40 +0000 (22:49 +0800)]
drm/amdgpu: correct ih cg programming for vega10 ih block
vega10/12 and RAVEN don't support soft override
ih_buffer_mem_clk.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:13:12 +0000 (23:13 +0800)]
drm/amdgpu: use cached ih rb control reg offsets for vega10
all the ih rb control register offsets are cached
at the beginning of ih_sw_init.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 8 Dec 2020 14:10:47 +0000 (22:10 +0800)]
drm/amdgpu: switch to ih_enable_ring for vega10
use vega10_ih_enable_ring to enable all the
available ring buffers for vega10/12, RAVEN
series and RENOIR APUs
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:03:32 +0000 (23:03 +0800)]
drm/amdgpu: switch to ih_toggle_interrupts for vega10
replace ih_enable_interrupts and ih_disable_interrupts
with ih_toggle_interrupts
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 15:01:02 +0000 (23:01 +0800)]
drm/amdgpu: switch to ih_init_register_offset for vega10
Initialize ih control registers offset through helper
function vega10_ih_init_register_offset.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 14:54:47 +0000 (22:54 +0800)]
drm/amdgpu: add helper to toggle ih ring interrupts for vega10
vega10_ih_toggle_ring_interrupts will be used to
enable/disable an ih ring interrupts for vega10/12,
RAVEN series and RENOIR APUs
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 14:53:17 +0000 (22:53 +0800)]
drm/amdgpu: add helper to enable an ih ring for vega10
vega10_ih_enable_ring will be used to enable an
ih ring for vega10/12, RAVEN series and RENOIR.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 14:44:40 +0000 (22:44 +0800)]
drm/amdgpu: add helper to init ih ring regs for vega10
vega10_ih_init_register_offset will be used to init
register offset for all the available ih rings
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Tue, 1 Dec 2020 14:36:46 +0000 (22:36 +0800)]
drm/amdgpu: add amdgpu_ih_regs structure
amdgpu_ih_regs holds all the registers for
an ih ring
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Stylon Wang [Tue, 10 Nov 2020 07:40:06 +0000 (15:40 +0800)]
drm/amd/display: Fix memory leaks in S3 resume
EDID parsing in S3 resume pushes new display modes
to probed_modes list but doesn't consolidate to actual
mode list. This creates a race condition when
amdgpu_dm_connector_ddc_get_modes() re-initializes the
list head without walking the list and results in memory leak.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=209987
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Alex Deucher [Fri, 18 Dec 2020 16:19:30 +0000 (11:19 -0500)]
drm/amdgpu: Fix a copy-pasta comment
This is not a scsi driver.
Reviewed-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 17 Dec 2020 17:11:36 +0000 (12:11 -0500)]
drm/amdgpu: only set DP subconnector type on DP and eDP connectors
Fixes a crash in drm_object_property_set_value() because the property
is not set for internal DP ports that connect to a bridge chips
(e.g., DP to VGA or DP to LVDS).
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210739
Fixes:
65bf2cf95d3ade ("drm/amdgpu: utilize subconnector property for DP through atombios")
Tested-By: Kris Karas <bugs-a17@moonlit-rail.com>
Cc: Oleg Vasilev <oleg.vasilev@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 5.10.x