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Samuel Holland [Wed, 13 Jul 2022 02:52:33 +0000 (21:52 -0500)]
pinctrl: sunxi: Add driver for Allwinner D1
This SoC contains a pinctrl with a new register layout. Use the variant
parameter to set the right register offsets. This pinctrl also increases
the number of functions per pin from 8 to 16, taking advantage of all 4
bits in the mux config field (so far, only functions 0-8 and 14-15 are
used). This increases the maximum possible number of functions.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20220713025233.27248-7-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Wed, 13 Jul 2022 02:52:32 +0000 (21:52 -0500)]
pinctrl: sunxi: Make some layout parameters dynamic
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the
pinctrl registers. This new layout widens the drive level field, which
affects the pull register offset and the overall bank size.
In order to support multiple register layouts, some of the layout
parameters need to be set based on the pinctrl variant. This requires
passing the pinctrl struct pointer to the register/offset calculation
functions.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-6-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Wed, 13 Jul 2022 02:52:31 +0000 (21:52 -0500)]
pinctrl: sunxi: Refactor register/offset calculation
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the
pinctrl registers. This new layout widens the drive level field, which
affects the pull register offset and the overall bank size.
As a first step to support this, combine the register and offset
calculation functions, and refactor the math to depend on one constant
for field widths instead of three. This minimizes the code size impact
of making some of the factors dynamic.
While rewriting these functions, move them to the implementation file,
since that is the only file where they are used. And make the comment
more generic, without mentioning specific offsets/sizes.
The callers are updated to expect a shifted mask, and to use consistent
terminology (reg/shift/mask/val).
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-5-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Wed, 13 Jul 2022 02:52:30 +0000 (21:52 -0500)]
pinctrl: sunxi: Support the 2.5V I/O bias mode
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the
1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level
and disabling the "withstand function".
H616 supports this capability on its main PIO only. A100 supports this
capability on both its PIO and R-PIO.
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Wed, 13 Jul 2022 02:52:29 +0000 (21:52 -0500)]
pinctrl: sunxi: Add I/O bias setting for H6 R-PIO
H6 requires I/O bias configuration on both of its PIO devices.
Previously it was only done for the main PIO.
The setting for Port L is at bit 0, so the bank calculation needs to
account for the pin base. Otherwise the wrong bit is used.
Fixes:
cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on H6")
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-3-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Wed, 13 Jul 2022 02:52:28 +0000 (21:52 -0500)]
dt-bindings: pinctrl: Add compatible for Allwinner D1
D1 contains a pin controller similar to previous SoCs, but with some
register layout changes. It includes 6 interrupt-capable pin banks.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-2-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Robert Marko [Mon, 11 Jul 2022 20:34:05 +0000 (22:34 +0200)]
pinctrl: qcom-pmic-gpio: add support for PMP8074
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Robert Marko [Mon, 11 Jul 2022 20:34:04 +0000 (22:34 +0200)]
dt-bindings: pinctrl: qcom,pmic-gpio: add PMP8074
Document the compatible for PMP8074 which has 12 GPIO-s with holes at
GPIO1 and GPIO12.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220711203408.2949888-3-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Dominik Kobinski [Thu, 25 Nov 2021 21:53:10 +0000 (22:53 +0100)]
pinctrl: qcom: spmi-gpio: Add pm8226 compatibility
Add support for pm8226 SPMI GPIOs. The PMIC features
8 GPIOs, with no holes inbetween.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Suggested-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com>
Link: https://lore.kernel.org/r/20211125215310.62371-1-dominikkobinski314@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Shevchenko [Wed, 29 Jun 2022 11:58:40 +0000 (14:58 +0300)]
pinctrl: core: Use device_match_of_node() helper
Instead of open coding, use device_match_of_node() helper.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220629115840.16241-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
AngeloGioacchino Del Regno [Thu, 30 Jun 2022 11:04:53 +0000 (13:04 +0200)]
dt-bindings: pinctrl: mt8195: Add gpio-line-names property
Add the 'gpio-line-names' property to mt8195-pinctrl, as this will be
used in devicetrees to describe pin names.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220630110453.186526-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
AngeloGioacchino Del Regno [Thu, 30 Jun 2022 13:15:43 +0000 (15:15 +0200)]
dt-bindings: pinctrl: mt8195: Add and use drive-strength-microamp
As was already done for MT8192 in commit
b52e695324bb ("dt-bindings:
pinctrl: mt8192: Add drive-strength-microamp"), replace the custom
mediatek,drive-strength-adv property with the standardized pinconf
'drive-strength-microamp' one.
Similarly to the mt8192 counterpart, there's no user of property
'mediatek,drive-strength-adv', hence removing it is safe.
Fixes:
69c3d58dc187 ("dt-bindings: pinctrl: mt8195: Add mediatek,drive-strength-adv property")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220630131543.225554-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
AngeloGioacchino Del Regno [Thu, 30 Jun 2022 12:23:34 +0000 (14:23 +0200)]
dt-bindings: pinctrl: mt8195: Fix name for mediatek,rsel-resistance-in-si-unit
When this property was introduced, it contained underscores, but
the actual code wants dashes.
Change it from mediatek,rsel_resistance_in_si_unit to
mediatek,rsel-resistance-in-si-unit.
Fixes:
91e7edceda96 ("dt-bindings: pinctrl: mt8195: change pull up/down description")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220630122334.216903-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Claudiu Beznea [Mon, 4 Jul 2022 10:12:53 +0000 (13:12 +0300)]
pinctrl: at91: remove #ifdef CONFIG_PM
Remove #ifdef CONFIG_PM and use pm_ptr() macro instead.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704101253.808519-2-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Claudiu Beznea [Mon, 4 Jul 2022 10:12:52 +0000 (13:12 +0300)]
pinctrl: at91-pio4: remove #ifdef CONFIG_PM_SLEEP
Remove #ifdef CONFIG_PM_SLEEP and use pm_sleep_ptr() macro instead.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704101253.808519-1-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andre Przywara [Fri, 8 Jul 2022 10:52:32 +0000 (11:52 +0100)]
dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
for GPIO port I.
Extend the range of supply port names to include vcc-pi-supply to cover
that.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220708105235.3983266-5-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andre Przywara [Fri, 8 Jul 2022 10:52:30 +0000 (11:52 +0100)]
dt-bindings: pinctrl: sunxi: Make interrupts optional
The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
interrupt (it features only two pins).
However the binding requires at least naming one upstream interrupt,
plus the #interrupt-cells and interrupt-controller properties.
Drop the unconditional requirement for the interrupt properties, and
make them dependent on being not this particular pinctrl device.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220708105235.3983266-3-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stephan Gerhold [Tue, 28 Jun 2022 14:55:02 +0000 (16:55 +0200)]
pinctrl: qcom: Add pinctrl driver for MSM8909
Make it possible to control pins using the TLMM block in the MSM8909 SoC
by adding the necessary definitions for GPIOs, groups and functions.
The driver is originally taken from the msm-4.9 release [1] from Qualcomm,
but cleaned up significantly with several fixes and clarifications.
[1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220628145502.4158234-3-stephan.gerhold@kernkonzept.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stephan Gerhold [Tue, 28 Jun 2022 14:55:01 +0000 (16:55 +0200)]
dt-bindings: pinctrl: Add DT schema for qcom,msm8909-tlmm
Document the "qcom,msm8909-tlmm" compatible for the TLMM/pin control
block in the MSM8909 SoC, together with the allowed GPIOs and functions.
Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220628145502.4158234-2-stephan.gerhold@kernkonzept.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Jianlong Huang [Mon, 27 Jun 2022 08:53:33 +0000 (10:53 +0200)]
pinctrl: starfive: Serialize adding groups and functions
The pinctrl dt_node_to_map method may be called in parallel which leads
us to call pinconf_generic_add_group and pinconf_generic_add_function
in parallel. This is not supported though and leads to errors, so add a
mutex to serialize these calls.
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220627085333.1774396-1-emil.renner.berthing@canonical.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sat, 9 Jul 2022 23:10:14 +0000 (01:10 +0200)]
Merge tag 'renesas-pinctrl-for-v5.20-tag2' of git://git./linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.20 (take two)
- Add support for the RZ/V2M and R-Car V4H SoCs,
- Miscellaneous fixes and improvements.
Basavaraj Natikar [Mon, 13 Jun 2022 06:41:27 +0000 (12:11 +0530)]
pinctrl: amd: Remove contact information
Remove contact information.
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/r/20220613064127.220416-4-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Basavaraj Natikar [Mon, 13 Jun 2022 06:41:26 +0000 (12:11 +0530)]
pinctrl: amd: Don't save/restore interrupt status and wake status bits
Saving/restoring interrupt and wake status bits across suspend can
cause the suspend to fail if an IRQ is serviced across the
suspend cycle.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Fixes:
79d2c8bede2c ("pinctrl/amd: save pin registers over suspend/resume")
Link: https://lore.kernel.org/r/20220613064127.220416-3-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Basavaraj Natikar [Mon, 13 Jun 2022 06:41:25 +0000 (12:11 +0530)]
pinctrl: amd: Use devm_platform_get_and_ioremap_resource
Use devm_platform_get_and_ioremap_resource() to simplify code.
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/r/20220613064127.220416-2-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sat, 9 Jul 2022 23:07:08 +0000 (01:07 +0200)]
Merge tag 'intel-pinctrl-v5.20-1' of gitolite.pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.20-1
* Update MAINTAINERS to set the Intel pin control status to Supported
* Switch Intel pin control drivers to use struct pingroup
The following is an automated git shortlog grouped by driver:
baytrail:
- Switch to to embedded struct pingroup
cherryview:
- Switch to to embedded struct pingroup
intel:
- Add Intel Meteor Lake pin controller support
- Drop no more used members of struct intel_pingroup
- Switch to to embedded struct pingroup
- Embed struct pingroup into struct intel_pingroup
lynxpoint:
- Switch to to embedded struct pingroup
MAINTAINERS:
- Update Intel pin control to Supported
Merge branch 'ib-v5.20-amd-pinctrl':
- Merge branch 'ib-v5.20-amd-pinctrl'
merrifield:
- Switch to to embedded struct pingroup
Robert Marko [Fri, 24 Jun 2022 19:51:12 +0000 (21:51 +0200)]
pinctrl: qcom: spmi-gpio: make the irqchip immutable
Commit
6c846d026d49 ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.
Following this change the following warning is now observed for the SPMI
PMIC pinctrl driver:
gpio gpiochip1: (
200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it!
Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20220624195112.894916-1-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Kuninori Morimoto [Fri, 1 Jul 2022 01:41:02 +0000 (01:41 +0000)]
pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBx
AVB1 needs MODSEL6, AVB2 needs MODSEL5 settings.
This patch adds missing MODSELx settings for the affected pins.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87k08xsj81.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:40:49 +0000 (01:40 +0000)]
pinctrl: renesas: r8a779g0: Add missing MODSELx for TSN0
TSN0 needs MODSEL4 settings.
This patch adds missing MODSELx settings for the affected pins.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87letdsj8e.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:40:42 +0000 (01:40 +0000)]
pinctrl: renesas: r8a779g0: Add missing ERROROUTC_A
This patch adds missing ERROROUTC_A settings.
Current existing ERROROUTC should be _B, this patch tidies it up.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87mtdtsj8m.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:40:27 +0000 (01:40 +0000)]
pinctrl: renesas: r8a779g0: Add missing PWM
R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed.
This patch adds missing PWM settings, and tidies these up.
According to Document, GP3_14 Function4 is PWM2_A,
but we can't select it at P1SR3[27:24].
This patch just ignore it for now.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87o7y9sj90.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:40:17 +0000 (01:40 +0000)]
pinctrl: renesas: r8a779g0: Add missing FlexRay
This patch adds missing FlexRay pins.
Because Document (Rev.0.51) has 2x FXR_TXENA/B pin with no suffix (_A, _B),
this patch names them as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87pmipsj9a.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:40:09 +0000 (01:40 +0000)]
pinctrl: renesas: r8a779g0: Add missing TPU0TOx_A
This patch adds missing TPU0TOx_A.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87r135sj9j.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:39:59 +0000 (01:39 +0000)]
pinctrl: renesas: r8a779g0: Add missing CANFD5_B
This patch adds missing CANFD5_B.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87sfnlsj9t.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:39:51 +0000 (01:39 +0000)]
pinctrl: renesas: r8a779g0: Add missing SCIF1_X
This patch adds missing SCIF1_X.
Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B),
this patch names it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87tu81sja1.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:39:44 +0000 (01:39 +0000)]
pinctrl: renesas: r8a779g0: Add missing SCIF3
R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87v8shsja7.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:39:34 +0000 (01:39 +0000)]
pinctrl: renesas: r8a779g0: Add missing HSCIF1_X
This patch adds missing HSCIF1.
Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B),
this patch names it as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:39:24 +0000 (01:39 +0000)]
pinctrl: renesas: r8a779g0: Add missing HSCIF3_A
This patch adds missing HSCIF3_A.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87y1xdsjar.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:39:11 +0000 (01:39 +0000)]
pinctrl: renesas: r8a779g0: Add missing IRQx_A/IRQx_B
This patch adds missing IRQx_A/IRQx_B, and tidies up existing IRQs.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87zghtsjb4.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:39:03 +0000 (01:39 +0000)]
pinctrl: renesas: r8a779g0: Add missing TCLKx_A/TCLKx_B/TCLKx_X
This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X.
Because Document (Rev.0.51) has 2x TCLK3/TCLK4 with no suffix (_A, _B),
this patch names them as _X.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/871qv5txvt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:38:40 +0000 (01:38 +0000)]
pinctrl: renesas: r8a779g0: Tidyup POC1 voltage
According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx,
GP1_23 - GP1_28 are 1.8/3.3V. But they are not on Table 7.28.
According to the HW team, there are no bits assigned.
This patch follows HW team's comment.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/8735fltxwg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:37:34 +0000 (01:37 +0000)]
pinctrl: renesas: r8a779g0: Tidy up ioctrl_regs
Remove POC2 which is not documented, and remove TD0SEL3 which is not
needed.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/874k01txy9.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:37:21 +0000 (01:37 +0000)]
pinctrl: renesas: r8a779g0: Remove unused MOD_SELx definitions
Current R-Car V4H PFC code has many MOD_SELx definitions with all 0.
But these have no meaning. This patch removes them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/875ykhtxym.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:37:12 +0000 (01:37 +0000)]
pinctrl: renesas: r8a779g0: Remove unused IPxSRx definitions
Current R-Car V4H PFC code has many IPxSRx definitions with all 0.
But these have no meaning. This patch removes them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/877d4xtxyv.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:36:59 +0000 (01:36 +0000)]
pinctrl: renesas: r8a779g0: Remove unused NOGP definitions
Current R-Car V4H PFC code has many NOGP definitions. But these are not
used, and they are different from original usage. This patch removes
them.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/878rpdtxz8.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:36:51 +0000 (01:36 +0000)]
pinctrl: renesas: r8a779g0: Fixup MODSEL8
MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is
indicating that I2C needs 1. But we should use 0 for all cases in
reality. New Datasheet should be updated.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87a69ttxzg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Phong Hoang [Fri, 1 Jul 2022 01:36:21 +0000 (01:36 +0000)]
pinctrl: renesas: r8a779g0: Add pins, groups and functions
This patch adds SCIF, I2C, EthernetAVB, HSCIF, MMC, QSPI, MSIOF, PWM,
CAN-FD, Ethernet-TSN, PCIe pins, groups, and functions.
This patch was created based on the Rev.0.51 datasheet.
Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: CongDang <cong.dang.xn@renesas.com>
Signed-off-by: Kazuya Mizuguch <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
[Morimoto: merged above patches into one, cleanup white space, sort modules alphabetically, fixup comments]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87bku9ty0b.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
LUU HOAI [Fri, 1 Jul 2022 01:36:13 +0000 (01:36 +0000)]
pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support
This patch adds initial pinctrl support for the R-Car V4H (R8A779G0)
SoC, including bias, drive strength and voltage control.
This patch was created based on the Rev.0.51 datasheet.
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:36:04 +0000 (01:36 +0000)]
pinctrl: renesas: Add PORT_GP_CFG_13 macros
Add PORT_GP_CFG_13() and PORT_GP_13() helper macros, to be used by the
r8a779g0 subdriver.
Based on a larger patch in the BSP by LUU HOAI.
Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87edz5ty0r.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Kuninori Morimoto [Fri, 1 Jul 2022 01:35:52 +0000 (01:35 +0000)]
dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support
Document Pin Function Controller (PFC) support for the Renesas R-Car V4H
(R8A779G0) SoC.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87fsjlty13.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Phil Edworthy [Fri, 24 Jun 2022 08:48:33 +0000 (09:48 +0100)]
pinctrl: renesas: Add RZ/V2M pin and gpio controller driver
Add support for pin and gpio controller driver for RZ/V2M SoC.
Based on the RZ/G2L driver.
Note that the DETDO and DETMS dedicated pins are currently not
documented in the HW manual as to which pin group they are in.
HW team has since said that the output level of 1.8V I/O group 4
(for MD0-7, and debugger) is the same as the 1.8V I/O group 3.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220624084833.22605-3-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Phil Edworthy [Fri, 24 Jun 2022 08:48:32 +0000 (09:48 +0100)]
dt-bindings: pinctrl: Add DT bindings for Renesas RZ/V2M pinctrl
Add device tree binding documentation and header file for Renesas
RZ/V2M pinctrl.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220624084833.22605-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Andy Shevchenko [Thu, 30 Jun 2022 12:38:58 +0000 (15:38 +0300)]
pinctrl: intel: Add Intel Meteor Lake pin controller support
This driver adds pinctrl/GPIO support for Intel Meteor Lake. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Samuel Holland [Tue, 21 Jun 2022 03:42:23 +0000 (22:42 -0500)]
pinctrl: axp209: Support the AXP221/AXP223/AXP809 variant
These PMICs each have 2 GPIOs with the same register layout as AXP813,
but without an ADC function. They all fall back to the AXP221 compatible
string, so only that one needs to be listed in the driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20220621034224.38995-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Tue, 21 Jun 2022 03:42:21 +0000 (22:42 -0500)]
dt-bindings: gpio: Add AXP221/AXP223/AXP809 compatibles
These PMICs each have 2 GPIOs with the same register layout as AXP813,
but without an ADC function.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220621034224.38995-2-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Srinivasa Rao Mandadapu [Wed, 29 Jun 2022 07:54:50 +0000 (13:24 +0530)]
pinctrl: qcom: sc7280: Fix compile bug
Fix the compilation error, caused by updating constant variable.
Hence remove redundant constant variable, which is no more useful
as per new design.
The issue is due to some unstaged changes. Fix it up.
Fixes:
36fe26843d6d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1656489290-20881-1-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Geert Uytterhoeven [Wed, 15 Jun 2022 13:59:41 +0000 (15:59 +0200)]
pinctrl: renesas: r8a779f0: Remove unused POC2
The POWER Condition Control Register 2 (POC2) is unused, and the
documentation does not define any valid bits. Remove it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d8a9ea39b49d24e39f4da3f00b64bce34016887d.1655301529.git.geert+renesas@glider.be
Geert Uytterhoeven [Wed, 15 Jun 2022 13:58:40 +0000 (15:58 +0200)]
dt-bindings: pinctrl: renesas: Remove spaces before #define
Remove spaces at the beginning of lines with #defines.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/5188ef93a911ce3781b16530fdebbf0f0af462b6.1655301264.git.geert+renesas@glider.be
Krzysztof Kozlowski [Thu, 16 Jun 2022 00:52:57 +0000 (17:52 -0700)]
dt-bindings: pinctrl: nuvoton,wpcm450-pinctrl: align key node name
gpio-keys schema requires keys to have more generic name.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220616005333.18491-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nícolas F. R. A. Prado [Mon, 27 Jun 2022 17:32:08 +0000 (13:32 -0400)]
dt-bindings: pinctrl: mt8192: Add RSEL values to bias-pull-{up,down}
Commit
fe44e4984018 ("pinctrl: mediatek: add rsel setting on mt8192")
added RSEL bias type definition for some pins on mt8192. In order to be
able to configure the bias on those pins, add the RSEL values in the
bias-pull-up and bias-pull-down properties in the binding.
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220627173209.604400-1-nfraprado@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Krzysztof Kozlowski [Fri, 24 Jun 2022 08:10:22 +0000 (10:10 +0200)]
pinctrl: samsung: do not use bindings header with constants
The Samsung SoC pin controller driver uses only three defines from the
bindings header with pin configuration register values, which proves
the point that this header is not a proper bindings-type abstraction
layer with IDs.
Define the needed register values directly in the driver and stop using
the bindings header.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220605160508.134075-8-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20220624081022.32384-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Xiang wangx [Sat, 18 Jun 2022 13:08:54 +0000 (21:08 +0800)]
pinctrl: aspeed: Fix typo in comment
Delete the redundant word 'and'.
Signed-off-by: Xiang wangx <wangxiang@cdjrlc.com>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Link: https://lore.kernel.org/r/20220618130854.12321-1-wangxiang@cdjrlc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Aidan MacDonald [Wed, 22 Jun 2022 18:50:10 +0000 (19:50 +0100)]
pinctrl: ingenic: Convert to immutable irq chip
Update the driver to use an immutable IRQ chip to fix this warning:
"not an immutable chip, please consider fixing it!"
Preserve per-chip labels by adding an ->irq_print_chip() callback.
Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20220622185010.2022515-3-aidanmacdonald.0x0@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Aidan MacDonald [Wed, 22 Jun 2022 18:50:09 +0000 (19:50 +0100)]
pinctrl: ingenic: Use irqd_to_hwirq()
Instead of accessing ->hwirq directly, use irqd_to_hwirq().
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20220622185010.2022515-2-aidanmacdonald.0x0@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sai Krishna Potthuri [Fri, 17 Jun 2022 10:46:59 +0000 (16:16 +0530)]
pinctrl: pinctrl-zynqmp: Fix kernel-doc warning
Fix the below kernel-doc warning by adding the description for return
value.
"warning: No description found for return value of
'zynqmp_pmux_get_function_groups'".
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1655462819-28801-5-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sai Krishna Potthuri [Fri, 17 Jun 2022 10:46:58 +0000 (16:16 +0530)]
pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedance
Add support to handle 'output-enable' and 'bias-high-impedance'
configurations. As part of the output-enable configuration, ZynqMP pinctrl
driver takes care of removing the pins from tri-state.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1655462819-28801-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sai Krishna Potthuri [Fri, 17 Jun 2022 10:46:57 +0000 (16:16 +0530)]
dt-bindings: pinctrl-zynqmp: Add output-enable configuration
Add 'output-enable' configuration parameter to the properties list.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1655462819-28801-3-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sai Krishna Potthuri [Fri, 17 Jun 2022 10:46:56 +0000 (16:16 +0530)]
firmware: xilinx: Add configuration values for tri-state
Add configuration values(enable/disable) for tri-state parameter.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Link: https://lore.kernel.org/r/1655462819-28801-2-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Clément Léger [Fri, 17 Jun 2022 10:35:48 +0000 (12:35 +0200)]
pinctrl: ocelot: allow building as a module
Set PINCTRL_OCELOT config option as a tristate and add
MODULE_DEVICE_TABLE()/MODULE_LICENSE() to export appropriate
information. Moreover, switch from builtin_platform_driver()
to module_platform_driver().
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
Link: https://lore.kernel.org/r/20220617103548.490092-1-clement.leger@bootlin.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 27 Jun 2022 09:20:46 +0000 (11:20 +0200)]
pinctrl: qcom: sc7280: Fix compile bug
The idea was right but the code was breaking in next.
I assume some unstaged commit was involed. Fix it up.
Cc: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Cc: Stephen Boyd <swboyd@chromium.org>
Fixes:
36fe26843d6d ("pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets")
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sun, 26 Jun 2022 23:58:27 +0000 (01:58 +0200)]
Merge tag 'renesas-pinctrl-for-v5.20-tag1' of git://git./linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.20
- Fix reporting of input disabled pins on RZ/G2L.
Linus Walleij [Sun, 26 Jun 2022 23:55:16 +0000 (01:55 +0200)]
pinctrl: mediatek: mt8192: Fix compile warnings
After applying patches I get these warnings:
drivers/pinctrl/mediatek/pinctrl-mt8192.c:1302:56:
warning: "/*" within comment [-Wcomment]
drivers/pinctrl/mediatek/pinctrl-mt8192.c:1362:56:
warning: "/*" within comment [-Wcomment]
Something is wrong with the missing end-slashes. Add them.
Cc: Guodong Liu <guodong.liu@mediatek.com>
Cc: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:37:00 +0000 (21:37 +0800)]
pinctrl: mediatek: fix the pinconf definition of some GPIO pins
Remove pin definitions that do not support the R0 & R1 pinconfig property.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-6-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:36:59 +0000 (21:36 +0800)]
pinctrl: mediatek: dropping original advanced drive configuration function
Function bias_combo getter/setters already handle all cases advanced drive
configuration, include drive for I2C related pins.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-5-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:36:58 +0000 (21:36 +0800)]
pinctrl: mediatek: add rsel setting on mt8192
1. I2C pins's resistance value can be controlled by rsel register.
This patch provides rsel (resistance selection) setting on mt8192.
2. Also add the missing pull type array for mt8192 to document the
pull type of each pin and prevent invalid pull type settings.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-4-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:36:57 +0000 (21:36 +0800)]
pinctrl: mediatek: add drive for I2C related pins on mt8192
This patch provides the advanced drive raw data setting version
for I2C used pins on mt8192.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-3-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Guodong Liu [Fri, 24 Jun 2022 13:36:56 +0000 (21:36 +0800)]
pinctrl: mediatek: add generic driving setup property on mt8192
1. The dt-binding expects that drive-strength arguments be passed
in mA, but the driver was expecting raw values. And that this
commit changes the driver so that it is aligned with the binding.
2. This commit provides generic driving setup, which support
2/4/6/8/10/12/14/16mA driving, original driver just set raw data
setup setting when use drive-strength property.
Signed-off-by: Guodong Liu <guodong.liu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220624133700.15487-2-guodong.liu@mediatek.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stefan Wahren [Tue, 14 Jun 2022 20:28:31 +0000 (22:28 +0200)]
pinctrl: bcm2835: Make the irqchip immutable
Commit
6c846d026d49 ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips. The bcm2835 pinctrl is also affected by this
warning.
Fix this by making the irqchip in the bcm2835 pinctrl driver immutable.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220614202831.236341-3-stefan.wahren@i2se.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Stefan Wahren [Tue, 14 Jun 2022 20:28:30 +0000 (22:28 +0200)]
pinctrl: bcm2835: drop irq_enable/disable callbacks
The commit
b8a19382ac62 ("pinctrl: bcm2835: Fix support for threaded level
triggered IRQs") assigned the irq_mask/unmask callbacks with the
already existing functions for irq_enable/disable. The wasn't completely
the right way (tm) to fix the issue, because these callbacks shouldn't
be identical. So fix this by rename the functions to represent their
intension and drop the unnecessary irq_enable/disable assigment.
Suggested-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220614202831.236341-2-stefan.wahren@i2se.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Lukas Bulwahn [Mon, 13 Jun 2022 12:29:55 +0000 (14:29 +0200)]
MAINTAINERS: add include/dt-bindings/pinctrl to PIN CONTROL SUBSYSTEM
Maintainers of the directory Documentation/devicetree/bindings/pinctrl
are also the maintainers of the corresponding directory
include/dt-bindings/pinctrl.
Add the file entry for include/dt-bindings/pinctrl to the appropriate
section in MAINTAINERS.
Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20220613122955.20714-1-lukas.bulwahn@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nikita Travkin [Sun, 12 Jun 2022 14:59:54 +0000 (19:59 +0500)]
pinctrl: qcom: msm8916: Allow CAMSS GP clocks to be muxed
GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the
function was never assigned to the pingroup (even though the function
exists already).
Add this mode to the related pins.
Fixes:
5373a2c5abb6 ("pinctrl: qcom: Add msm8916 pinctrl driver")
Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20220612145955.385787-4-nikita@trvn.ru
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Srinivasa Rao Mandadapu [Sat, 11 Jun 2022 04:22:37 +0000 (09:52 +0530)]
pinctrl: qcom: sc7280: Add clock optional check for ADSP bypass targets
Update lpass lpi pin control driver, with clock optional check for ADSP
disabled platforms. This check required for distingushing ADSP based
platforms and ADSP bypass platforms.
In case of ADSP enabled platforms, where audio is routed through ADSP
macro and decodec GDSC Switches are triggered as clocks by pinctrl
driver and ADSP firmware controls them. So It's mandatory to enable
them in ADSP based solutions.
In case of ADSP bypass platforms clock voting is optional as these macro
and dcodec GDSC switches are maintained as power domains and operated from
lpass clock drivers.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1654921357-16400-3-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Srinivasa Rao Mandadapu [Sat, 11 Jun 2022 04:22:36 +0000 (09:52 +0530)]
dt-bindings: pinctrl: qcom: sc7280: Add boolean param for ADSP bypass platforms
Add boolean param qcom,adsp-bypass-mode to support adsp bypassed sc7280
platforms. Which is required to make clock voting as optional for ADSP
bypass platforms.
Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1654921357-16400-2-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Andy Shevchenko [Mon, 20 Jun 2022 11:28:47 +0000 (14:28 +0300)]
pinctrl: intel: Drop no more used members of struct intel_pingroup
There are no more used members in the struct intel_pingroup, drop them.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Mon, 20 Jun 2022 11:28:48 +0000 (14:28 +0300)]
pinctrl: intel: Switch to to embedded struct pingroup
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Mon, 20 Jun 2022 11:28:48 +0000 (14:28 +0300)]
pinctrl: merrifield: Switch to to embedded struct pingroup
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Mon, 20 Jun 2022 11:28:48 +0000 (14:28 +0300)]
pinctrl: lynxpoint: Switch to to embedded struct pingroup
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Mon, 20 Jun 2022 11:28:48 +0000 (14:28 +0300)]
pinctrl: cherryview: Switch to to embedded struct pingroup
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Mon, 20 Jun 2022 11:28:48 +0000 (14:28 +0300)]
pinctrl: baytrail: Switch to to embedded struct pingroup
Since struct intel_pingroup got a new member, switch the driver to use it.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Mon, 20 Jun 2022 09:06:07 +0000 (12:06 +0300)]
pinctrl: intel: Embed struct pingroup into struct intel_pingroup
Add a new member to the struct intel_pingroup to cover generic
pin control group parameters. The idea is to convert all users
(one-by-one) to it and drop old members later on.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Andy Shevchenko [Wed, 15 Jun 2022 15:06:56 +0000 (18:06 +0300)]
Merge branch 'ib-v5.20-amd-pinctrl'
Merge branch 'ib-v5.20-amd-pinctrl' of
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
to develop Intel pin control driver changes based on provided new data structure.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Krzysztof Kozlowski [Tue, 7 Jun 2022 12:13:35 +0000 (14:13 +0200)]
dt-bindings: pinctrl: sunplus,sp7021-pinctrl: reference generic schema
Reference generic pin controller schema to enforce proper root node
name.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220607121335.131497-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Miaoqian Lin [Tue, 7 Jun 2022 11:16:01 +0000 (15:16 +0400)]
pinctrl: nomadik: Fix refcount leak in nmk_pinctrl_dt_subnode_to_map
of_parse_phandle() returns a node pointer with refcount
incremented, we should use of_node_put() on it when not need anymore.
Add missing of_node_put() to avoid refcount leak."
Fixes:
c2f6d059abfc ("pinctrl: nomadik: refactor DT parser to take two paths")
Signed-off-by: Miaoqian Lin <linmq006@gmail.com>
Link: https://lore.kernel.org/r/20220607111602.57355-1-linmq006@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Wed, 15 Jun 2022 13:54:49 +0000 (15:54 +0200)]
Merge branch 'ib-v5.20-amd-pinctrl' into devel
Samuel Holland [Tue, 31 May 2022 05:36:23 +0000 (00:36 -0500)]
dt-bindings: pinctrl: sunxi: Disallow the resets property
None of the sunxi pin controllers have a module reset line. This is
confirmed by documentation (A80) as well as experimentation (A33).
Since the property is not applicable to any variant of the hardware,
let's remove it from the binding.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220531053623.43851-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Tue, 31 May 2022 05:36:22 +0000 (00:36 -0500)]
ARM: dts: sunxi: Drop resets from r_pio nodes
None of the sunxi pin controllers have a module reset line. This is
confirmed by documentation (A80) as well as experimentation (A33).
Let's remove the inaccurate properties.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220531053623.43851-3-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Samuel Holland [Tue, 31 May 2022 05:36:21 +0000 (00:36 -0500)]
pinctrl: sunxi: Remove reset controller consumers
None of the sunxi pin controllers have a module reset line. All of the
SoC documentation, where available, agrees. The bits that would be used
for the PIO reset (i.e. matching the order of the clock gate bits) are
always reserved, both in the CCU and in the PRCM. And experiments on
several SoCs, including the A33, confirm that those reserved bits indeed
have no effect.
Let's remove this superfluous code and dependency, and also remove the
include statement that was copied to the other r_pio drivers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220531053623.43851-2-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nícolas F. R. A. Prado [Wed, 25 May 2022 15:57:14 +0000 (11:57 -0400)]
dt-bindings: pinctrl: mt8192: Use generic bias instead of pull-*-adv
Commit
cafe19db7751 ("pinctrl: mediatek: Backward compatible to previous
Mediatek's bias-pull usage") allowed the bias-pull-up and bias-pull-down
properties to be used for setting PUPD/R1/R0 type bias on mtk-paris
based SoC's, which was previously only supported by the custom
mediatek,pull-up-adv and mediatek,pull-down-adv properties.
Since the bias-pull-{up,down} properties already have defines associated
thus being more descriptive and is more universal on MediaTek platforms,
and given that there are no mediatek,pull-{up,down}-adv users on mt8192
yet, remove the custom adv properties in favor of the generic ones.
Note that only mediatek,pull-up-adv was merged in the binding, but not
its down counterpart.
Fixes:
edbacb36ea50 ("dt-bindings: pinctrl: mt8192: Add mediatek,pull-up-adv property")
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogiocchino.delregno@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220525155714.1837360-3-nfraprado@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Nícolas F. R. A. Prado [Wed, 25 May 2022 15:57:13 +0000 (11:57 -0400)]
dt-bindings: pinctrl: mt8192: Add drive-strength-microamp
Commit
e5fabbe43f3f ("pinctrl: mediatek: paris: Support generic
PIN_CONFIG_DRIVE_STRENGTH_UA") added support for using
drive-strength-microamp instead of mediatek,drive-strength-adv.
Since there aren't any users of mediatek,drive-strength-adv on mt8192
yet, remove this property and add drive-strength-microamp in its place,
which has a clearer meaning.
Fixes:
4ac68333ff6d ("dt-bindings: pinctrl: mt8192: Add mediatek,drive-strength-adv property")
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogiocchino.delregno@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220525155714.1837360-2-nfraprado@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Basavaraj Natikar [Wed, 1 Jun 2022 15:29:00 +0000 (20:59 +0530)]
pinctrl: amd: Implement pinmux functionality
Provide pinmux functionality by implementing pinmux_ops.
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220601152900.1012813-7-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Basavaraj Natikar [Wed, 1 Jun 2022 15:28:59 +0000 (20:58 +0530)]
pinctrl: amd: Add amd_get_iomux_res function
Presently there is no way to change pinmux configuration run time.
Hence add a function to get IOMUX resource which can be used to
configure IOMUX GPIO pins run time.
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220601152900.1012813-6-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>