OSDN Git Service
Akira Hatanaka [Tue, 20 Dec 2011 23:28:36 +0000 (23:28 +0000)]
Set the correct stack pointer register that should be saved or restored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012
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Jim Grosbach [Tue, 20 Dec 2011 23:20:00 +0000 (23:20 +0000)]
Enable and fix a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011
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Chris Lattner [Tue, 20 Dec 2011 23:14:57 +0000 (23:14 +0000)]
Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on
the build bot in some cases. The basic issue happens when a source module contains
both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if
the destination module contains a "%foo" type, and it will return true... because
both the source and destination modules are in the same LLVMContext. We don't want
to map source types to other source types, so don't do the remapping if the mapped
type came from the source module.
Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is
pretty great that way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147010
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Jim Grosbach [Tue, 20 Dec 2011 23:11:00 +0000 (23:11 +0000)]
ARM .req register name aliases are case insensitive, just like regnames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009
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Akira Hatanaka [Tue, 20 Dec 2011 23:10:57 +0000 (23:10 +0000)]
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008
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Akira Hatanaka [Tue, 20 Dec 2011 22:58:01 +0000 (22:58 +0000)]
Fix indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007
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Akira Hatanaka [Tue, 20 Dec 2011 22:52:19 +0000 (22:52 +0000)]
64-bit data directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005
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Akira Hatanaka [Tue, 20 Dec 2011 22:40:40 +0000 (22:40 +0000)]
32-to-64-bit sext_inreg pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004
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Akira Hatanaka [Tue, 20 Dec 2011 22:36:08 +0000 (22:36 +0000)]
Add 64-bit extload patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003
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Akira Hatanaka [Tue, 20 Dec 2011 22:33:53 +0000 (22:33 +0000)]
Add patterns for matching extloads with 64-bit address. The patterns are enabled
only when the target ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001
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Jim Grosbach [Tue, 20 Dec 2011 22:26:38 +0000 (22:26 +0000)]
Move comment to appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000
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Akira Hatanaka [Tue, 20 Dec 2011 22:25:50 +0000 (22:25 +0000)]
Add code in MipsDAGToDAGISel for selecting constant +0.0.
MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999
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Jakob Stoklund Olesen [Tue, 20 Dec 2011 22:15:04 +0000 (22:15 +0000)]
Heed spill slot alignment on ARM.
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997
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Akira Hatanaka [Tue, 20 Dec 2011 22:09:36 +0000 (22:09 +0000)]
Revert part of r146995 that was accidentally commmitted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146996
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Akira Hatanaka [Tue, 20 Dec 2011 22:06:20 +0000 (22:06 +0000)]
32-to-64-bit sign extension pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146995
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Akira Hatanaka [Tue, 20 Dec 2011 21:50:49 +0000 (21:50 +0000)]
Add a pattern for matching zero-store with 64-bit address. The pattern is enabled
only when the target ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146992
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Jim Grosbach [Tue, 20 Dec 2011 20:46:29 +0000 (20:46 +0000)]
ARM assembly parsing and encoding for VST2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990
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Lang Hames [Tue, 20 Dec 2011 20:23:40 +0000 (20:23 +0000)]
Fix assert condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146987
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Jakub Staszak [Tue, 20 Dec 2011 20:03:10 +0000 (20:03 +0000)]
Add some constantness to BranchProbabilityInfo and BlockFrequnencyInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146986
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Jim Grosbach [Tue, 20 Dec 2011 20:03:00 +0000 (20:03 +0000)]
ARM enable a few more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985
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Devang Patel [Tue, 20 Dec 2011 19:29:36 +0000 (19:29 +0000)]
Add support to add named metadata operand.
Patch by Andrew Wilkins!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146984
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Jim Grosbach [Tue, 20 Dec 2011 19:21:26 +0000 (19:21 +0000)]
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983
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Evan Cheng [Tue, 20 Dec 2011 18:26:50 +0000 (18:26 +0000)]
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981
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Jason W Kim [Tue, 20 Dec 2011 17:38:12 +0000 (17:38 +0000)]
First steps in ARM AsmParser support for .eabi_attribute and .arch
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977
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Elena Demikhovsky [Tue, 20 Dec 2011 13:34:28 +0000 (13:34 +0000)]
This is the second fix related to VZEXT_MOVL node.
The failure that I see in the current version is:
LLVM ERROR: Cannot select: 0x18b8f70: v4i64 = X86ISD::VZEXT_MOVL 0x18beee0 [ID=14]
0x18beee0: v4i64 = insert_subvector 0x18b8c70, 0x18b9170, 0x18b9570 [ID=13]
0x18b8c70: v4i64 = insert_subvector 0x18b9870, 0x18bf4e0, 0x18b9970 [ID=12]
0x18b9870: v4i64 = undef [ID=4]
0x18bf4e0: v2i64 = bitcast 0x18bf3e0 [ID=10]
0x18bf3e0: v4i32 = BUILD_VECTOR 0x18b9770, 0x18b9770, 0x18b9770, 0x18b9770 [ID=8]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9770: i32 = TargetConstant<0> [ID=6]
0x18b9970: i32 = Constant<0> [ID=3]
0x18b9170: v2i64 = undef [ORD=1] [ID=1]
0x18b9570: i32 = Constant<2> [ID=5]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146975
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Chandler Carruth [Tue, 20 Dec 2011 11:19:37 +0000 (11:19 +0000)]
Begin teaching the X86 target how to efficiently codegen patterns that
use the zero-undefined variants of CTTZ and CTLZ. These are just simple
patterns for now, there is more to be done to make real world code using
these constructs be optimized and codegen'ed properly on X86.
The existing tests are spiffed up to check that we no longer generate
unnecessary cmov instructions, and that we generate the very important
'xor' to transform bsr which counts the index of the most significant
one bit to the number of leading (most significant) zero bits. Also they
now check that when the variant with defined zero result is used, the
cmov is still produced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146974
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Manuel Klimek [Tue, 20 Dec 2011 11:04:23 +0000 (11:04 +0000)]
Fixes a potential compilation error.
Pulling the template implementation into the header to guarantee
that it's visible to all possible instantiations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146973
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Manuel Klimek [Tue, 20 Dec 2011 10:42:52 +0000 (10:42 +0000)]
Pulls the implementation of skip() into JSONParser.
This is the first step towards migrating more of the parser
implementation into the parser class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146971
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Manuel Klimek [Tue, 20 Dec 2011 10:34:29 +0000 (10:34 +0000)]
Fixing option for JSON benchmark broken since the change to size_t.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146970
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Manuel Klimek [Tue, 20 Dec 2011 09:26:26 +0000 (09:26 +0000)]
Addressing style issues in JSON parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146968
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Chandler Carruth [Tue, 20 Dec 2011 08:42:11 +0000 (08:42 +0000)]
Fix up the CMake build for the new files added in r146960, they're
likely to stay either way that discussion ends up resolving itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146966
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David Blaikie [Tue, 20 Dec 2011 08:22:49 +0000 (08:22 +0000)]
Revert pragma clang suppressions that confuse GCC. (I'll worry about how to suppress/fix these problems properly when we figure out how to keep LLVM -Wweak-vtables clean)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146965
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Nadav Rotem [Tue, 20 Dec 2011 08:02:50 +0000 (08:02 +0000)]
Add a few lines to the release notes:
1. pointer-vector
2. type legalizer changes and vector-select
3. X86 ISA changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146964
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David Blaikie [Tue, 20 Dec 2011 02:50:00 +0000 (02:50 +0000)]
Unweaken vtables as per llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960
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Andrew Trick [Tue, 20 Dec 2011 01:43:20 +0000 (01:43 +0000)]
Unit test for r146950: LSR postinc expansion, PR11571.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146951
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Andrew Trick [Tue, 20 Dec 2011 01:42:24 +0000 (01:42 +0000)]
LSR: Fix another corner case in expansion of postinc users.
Fixes PR11571: Instruction does not dominate all uses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146950
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Bob Wilson [Tue, 20 Dec 2011 01:29:27 +0000 (01:29 +0000)]
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar
10567930.
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146949
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Chris Lattner [Tue, 20 Dec 2011 01:11:37 +0000 (01:11 +0000)]
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146940
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Dan Gohman [Tue, 20 Dec 2011 01:10:56 +0000 (01:10 +0000)]
Add a line to ReleaseNotes for half float.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146939
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Jim Grosbach [Tue, 20 Dec 2011 00:59:38 +0000 (00:59 +0000)]
ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://
10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937
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Chris Lattner [Tue, 20 Dec 2011 00:12:26 +0000 (00:12 +0000)]
Now that PR11464 is fixed, reapply the patch to fix PR11464,
merging types by name when we can. We still don't guarantee type name linkage
but we do it when obviously the right thing to do. This makes LTO type names
easier to read, for example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146932
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Chris Lattner [Tue, 20 Dec 2011 00:03:52 +0000 (00:03 +0000)]
fix PR11464 by preventing the linker from mapping two different struct types from the source module onto the same opaque destination type. An opaque type can only be resolved to one thing or another after all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146929
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Chris Lattner [Tue, 20 Dec 2011 00:03:41 +0000 (00:03 +0000)]
add a method to improve compatibility with SmallVector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146928
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Dan Gohman [Tue, 20 Dec 2011 00:02:33 +0000 (00:02 +0000)]
Add basic generic CodeGen support for half.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146927
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Jim Grosbach [Mon, 19 Dec 2011 23:51:07 +0000 (23:51 +0000)]
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://
10603913
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925
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Evan Cheng [Mon, 19 Dec 2011 23:26:44 +0000 (23:26 +0000)]
Move tests to FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146923
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Jim Grosbach [Mon, 19 Dec 2011 23:06:24 +0000 (23:06 +0000)]
ARM assembly parsing and encoding support for LDRD(label).
rdar://
9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921
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Evan Cheng [Mon, 19 Dec 2011 22:01:30 +0000 (22:01 +0000)]
Add a if-conversion optimization that allows 'true' side of a diamond to be
unpredicated. That is, turn
subeq r0, r1, #1
addne r0, r1, #1
into
sub r0, r1, #1
addne r0, r1, #1
For targets where conditional instructions are always executed, this may be
beneficial. It may remove pseudo anti-dependency in out-of-order execution
CPUs. e.g.
op r1, ...
str r1, [r10] ; end-of-life of r1 as div result
cmp r0, #65
movne r1, #44 ; raw dependency on previous r1
moveq r1, #12
If movne is unpredicated, then
op r1, ...
str r1, [r10]
cmp r0, #65
mov r1, #44 ; r1 written unconditionally
moveq r1, #12
Both mov and moveq are no longer depdendent on the first instruction. This gives
the out-of-order execution engine more freedom to reorder them.
This has passed entire LLVM test suite. But it has not been enabled for any ARM
variant pending more performance evaluation.
rdar://
8951196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146914
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Eli Friedman [Mon, 19 Dec 2011 21:53:12 +0000 (21:53 +0000)]
Add "using" to silence warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146913
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Akira Hatanaka [Mon, 19 Dec 2011 20:24:28 +0000 (20:24 +0000)]
Add a test case for r146900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146901
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Akira Hatanaka [Mon, 19 Dec 2011 20:21:18 +0000 (20:21 +0000)]
Add patterns for matching immediates whose lower 16-bit is cleared. These
patterns emit a single LUi instruction instead of a pair of LUi and ORi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146900
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Eli Friedman [Mon, 19 Dec 2011 20:06:03 +0000 (20:06 +0000)]
Attempt to fix PR11607 by shuffling around which class defines which methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146897
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Akira Hatanaka [Mon, 19 Dec 2011 19:52:25 +0000 (19:52 +0000)]
Tidy up. Simplify logic. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146896
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Jim Grosbach [Mon, 19 Dec 2011 19:51:03 +0000 (19:51 +0000)]
ARM NEON two-operand aliases for VPADD.
rdar://
10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895
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Akira Hatanaka [Mon, 19 Dec 2011 19:44:09 +0000 (19:44 +0000)]
Remove definitions of double word shift plus 32 instructions. Assembler or
direct-object emitter should emit the appropriate shift instruction depending
on the shift amount.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146893
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Jim Grosbach [Mon, 19 Dec 2011 19:43:50 +0000 (19:43 +0000)]
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146892
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Akira Hatanaka [Mon, 19 Dec 2011 19:32:20 +0000 (19:32 +0000)]
Remove unused predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146889
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Akira Hatanaka [Mon, 19 Dec 2011 19:28:37 +0000 (19:28 +0000)]
Remove the restriction on the first operand of the add node in SelectAddr.
This change reduces the number of instructions generated.
For example,
(load (add (sub $n0, $n1), (MipsLo got(s))))
results in the following sequence of instructions:
1. sub $n2, $n0, $n1
2. lw got(s)($n2)
Previously, three instructions were needed.
1. sub $n2, $n0, $n1
2. addiu $n3, $n2, got(s)
3. lw 0($n3)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146888
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Jim Grosbach [Mon, 19 Dec 2011 19:02:41 +0000 (19:02 +0000)]
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146887
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Jim Grosbach [Mon, 19 Dec 2011 18:57:38 +0000 (18:57 +0000)]
ARM NEON implied destination aliases for VMAX/VMIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885
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Jim Grosbach [Mon, 19 Dec 2011 18:31:43 +0000 (18:31 +0000)]
ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884
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Jim Grosbach [Mon, 19 Dec 2011 18:11:17 +0000 (18:11 +0000)]
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882
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Jakob Stoklund Olesen [Mon, 19 Dec 2011 16:53:40 +0000 (16:53 +0000)]
Remove a register class that can just as well be synthesized.
Add the new TableGen register class synthesizer feature to the release
notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146875
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Jakob Stoklund Olesen [Mon, 19 Dec 2011 16:53:37 +0000 (16:53 +0000)]
Handle sub-register operands in recomputeRegClass().
Now that getMatchingSuperRegClass() returns accurate results, it can be
used to compute constraints imposed by instructions using a sub-register
of a virtual register.
This means we can recompute the register class of any virtual register
by combining the constraints from all its uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146874
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Jakob Stoklund Olesen [Mon, 19 Dec 2011 16:53:34 +0000 (16:53 +0000)]
Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873
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Jakob Stoklund Olesen [Mon, 19 Dec 2011 16:53:28 +0000 (16:53 +0000)]
Synthesize register classes for TRI::getMatchingSuperRegClass().
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results. The function is
still not auto-generated, so it still returns inexact results.
This produces these new register classes:
ARM:
QQPR_with_dsub_0_in_DPR_8
QQQQPR_with_dsub_0_in_DPR_8
X86:
GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
GR64_with_sub_16bit_in_GR16_NOREX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
GR64_with_sub_32bit_in_GR32_TC
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
GR64_with_sub_32bit_in_GR32_AD
GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX
The other targets in the tree are not weird enough to be affected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146872
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Manuel Klimek [Mon, 19 Dec 2011 09:56:35 +0000 (09:56 +0000)]
Allow for benchmarking more than 4GB of memory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146864
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Manuel Klimek [Mon, 19 Dec 2011 09:32:05 +0000 (09:32 +0000)]
Adds a flag to allow specifying the memory limitations of the JSON benchmark.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146863
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Jakub Staszak [Sun, 18 Dec 2011 21:52:30 +0000 (21:52 +0000)]
- Use getExitingBlock instead of getExitingBlocks.
- Remove trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146854
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Benjamin Kramer [Sun, 18 Dec 2011 20:51:31 +0000 (20:51 +0000)]
Another variadics tweak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146852
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Joerg Sonnenberger [Sun, 18 Dec 2011 20:35:43 +0000 (20:35 +0000)]
Allow inlining of functions with returns_twice calls, if they have the
attribute themselve.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146851
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Benjamin Kramer [Sun, 18 Dec 2011 19:59:20 +0000 (19:59 +0000)]
Use the fancy new VariadicFunction template instead of a plain variadic function.
Some compilers were complaining about passing StringRef to it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146850
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Dylan Noblesmith [Sun, 18 Dec 2011 18:50:16 +0000 (18:50 +0000)]
capitalize project name, reference bugzilla
And fix the double-[]. It was including the [] as part of
the project name somehow, resulting in PACKAGE_TARNAME "-llvm-"
and a strange docdir default:
./configure --help | grep docdir
--docdir=DIR documentation root [DATAROOTDIR/doc/-llvm-]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146849
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Benjamin Kramer [Sun, 18 Dec 2011 12:00:09 +0000 (12:00 +0000)]
Hexagon: Remove unused variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146846
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Chad Rosier [Sat, 17 Dec 2011 22:19:53 +0000 (22:19 +0000)]
Revert 146728 as it's causing failures on some of the external bots as well as
internal nightly testers. Original commit message:
By popular demand, link up types by name if they are isomorphic and one is an
autorenamed version of the other. This makes the IR easier to read, because
we don't end up with random renamed versions of the types after LTO'ing a large
app.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146838
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Kevin Enderby [Sat, 17 Dec 2011 19:48:52 +0000 (19:48 +0000)]
Revert r146822 at Pete Cooper's request as it broke clang self hosting.
Hope I did this correctly :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146834
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Craig Topper [Sat, 17 Dec 2011 19:16:44 +0000 (19:16 +0000)]
Remove an unused X86ISD node type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146833
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Benjamin Kramer [Sat, 17 Dec 2011 14:36:05 +0000 (14:36 +0000)]
X86: Factor the bswap asm matching to be slightly less horrible to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146831
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Chandler Carruth [Sat, 17 Dec 2011 10:20:15 +0000 (10:20 +0000)]
As Doug pointed out (and I really should know), it is perfectly easy to
make VariadicFunction actually be trivial. Do so, and also make it look
more like your standard trivial functor by making it a struct with no
access specifiers. The unit test is updated to initialize its functors
properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146827
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Pete Cooper [Sat, 17 Dec 2011 06:32:38 +0000 (06:32 +0000)]
SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands.
For example,
if (a == b) {
if (a > b) // this is false
Fixes some of the issues on <rdar://problem/
10554090>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146822
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Manuel Klimek [Sat, 17 Dec 2011 06:29:32 +0000 (06:29 +0000)]
Deleting the json-bench-test until I understand why it is flaky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146821
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Evan Cheng [Sat, 17 Dec 2011 01:25:34 +0000 (01:25 +0000)]
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805
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Pete Cooper [Sat, 17 Dec 2011 01:20:32 +0000 (01:20 +0000)]
Refactor code used in InstCombine::FoldAndOfICmps to new file.
This will be used by SimplifyCfg in a later commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146803
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Rafael Espindola [Sat, 17 Dec 2011 01:14:52 +0000 (01:14 +0000)]
Add back the MC bits of 126425. Original patch by Nathan Jeffords. I added the
asm parsing and testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146801
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Lang Hames [Sat, 17 Dec 2011 01:08:46 +0000 (01:08 +0000)]
Make sure that the lower bits on the VSELECT condition are properly set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146800
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Jakob Stoklund Olesen [Sat, 17 Dec 2011 00:07:02 +0000 (00:07 +0000)]
Preserve more memory operands in ARMExpandPseudo.
I don't think this affects anything but verbose assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146787
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Dan Gohman [Sat, 17 Dec 2011 00:04:22 +0000 (00:04 +0000)]
The powers that be have decided that LLVM IR should now support 16-bit
"half precision" floating-point with a first-class type.
This patch adds basic IR support (but not codegen support).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146786
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Eric Christopher [Fri, 16 Dec 2011 23:42:45 +0000 (23:42 +0000)]
When recursing for the original size of a type, stop if we are at a
pointer or a reference type - we actually just want the size of the
pointer then for that.
Fixes rdar://
10335756
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146785
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Eric Christopher [Fri, 16 Dec 2011 23:42:42 +0000 (23:42 +0000)]
Resolve part of a fixme and add a new one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146784
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Eric Christopher [Fri, 16 Dec 2011 23:42:38 +0000 (23:42 +0000)]
Add a fixme here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146783
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Eric Christopher [Fri, 16 Dec 2011 23:42:35 +0000 (23:42 +0000)]
Fix spacing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146782
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Eric Christopher [Fri, 16 Dec 2011 23:42:33 +0000 (23:42 +0000)]
Update documentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146781
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Eric Christopher [Fri, 16 Dec 2011 23:42:31 +0000 (23:42 +0000)]
Extraneous whitespace and 80-col.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146780
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Jakob Stoklund Olesen [Fri, 16 Dec 2011 23:00:05 +0000 (23:00 +0000)]
Fix off-by-one error in bucket sort.
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/
10594653>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146767
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Dylan Noblesmith [Fri, 16 Dec 2011 20:36:31 +0000 (20:36 +0000)]
APInt: update asserts for base-36
Hexatridecimal was added in r139695.
And fix the unittest that now triggers the assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146754
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Jakob Stoklund Olesen [Fri, 16 Dec 2011 19:10:00 +0000 (19:10 +0000)]
Don't adjust for alignment padding in OffsetIsInRange.
This adjustment is already included in the block offsets computed by
BasicBlockInfo, and adjusting again here can cause the pass to loop.
When CreateNewWater splits a basic block, OffsetIsInRange would reject
the new CPE on the next pass because of the too conservative alignment
adjustment. This caused the block to be split again, and so on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146751
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Benjamin Kramer [Fri, 16 Dec 2011 19:08:59 +0000 (19:08 +0000)]
Hexagon: Fix a nasty order-of-initialization bug.
Reenable the tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146750
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Devang Patel [Fri, 16 Dec 2011 17:51:31 +0000 (17:51 +0000)]
In DICompositeType, referenced to derived type is either metadata or null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146744
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Devang Patel [Fri, 16 Dec 2011 17:50:04 +0000 (17:50 +0000)]
Clarify and fix subprogram description.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146743
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Jakob Stoklund Olesen [Fri, 16 Dec 2011 16:07:41 +0000 (16:07 +0000)]
Note ARM constant island alignment in the release notes.
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146739
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