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Florian Hahn [Fri, 27 Apr 2018 13:52:51 +0000 (13:52 +0000)]
[LoopInterchange] Allow some loops with PHI nodes in the exit block.
We currently support LCSSA PHI nodes in the outer loop exit, if their
incoming values do not come from the outer loop latch or if the
outer loop latch has a single predecessor. In that case, the outer loop latch
will be executed only if the inner loop gets executed. If we have multiple
predecessors for the outer loop latch, it may be executed even if the inner
loop does not get executed.
This is a first step to support the case described in
https://bugs.llvm.org/show_bug.cgi?id=30472
Reviewers: efriedma, karthikthecool, mcrosier
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D43237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331037
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Oliver Stannard [Fri, 27 Apr 2018 13:45:32 +0000 (13:45 +0000)]
[AArch64] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the AArch64 dot-product instructions introduced in
v8.2-A.
Differential revisioon: https://reviews.llvm.org/D46107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331036
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Benjamin Kramer [Fri, 27 Apr 2018 13:36:05 +0000 (13:36 +0000)]
[NVPTX] Turn on Loop/SLP vectorization
Since PTX has grown a <2 x half> datatype vectorization has become more
important. The late LoadStoreVectorizer intentionally only does loads
and stores, but now arithmetic has to be vectorized for optimal
throughput too.
This is still very limited, SLP vectorization happily creates <2 x half>
if it's a legal type but there's still a lot of register moving
happening to get that fed into a vectorized store. Overall it's a small
performance win by reducing the amount of arithmetic instructions.
I haven't really checked what the loop vectorizer does to PTX code, the
cost model there might need some more tweaks. I didn't see it causing
harm though.
Differential Revision: https://reviews.llvm.org/D46130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331035
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Simon Pilgrim [Fri, 27 Apr 2018 13:32:42 +0000 (13:32 +0000)]
[X86] Replace some system instruction instregex single matches with instrs entry. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331034
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Aleksandar Beserminji [Fri, 27 Apr 2018 13:30:27 +0000 (13:30 +0000)]
[mips] Fix how compiler fuse instructions to fmadd/fmsub
This patch makes compiler does not fuse fmul and fadd/fsub into
fmadd/fmsub by default. Instead, -fp-contract=fast option can
be used when such behavior is desired.
Differential Revision: https://reviews.llvm.org/D46057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331033
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Oliver Stannard [Fri, 27 Apr 2018 12:50:40 +0000 (12:50 +0000)]
[ARM] Codegen for v8.2A dot product intrinsics
This adds IR intrinsics for the ARM dot-product instructions introduced in
v8.2-A.
Differential revision: https://reviews.llvm.org/D46106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331032
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Alex Bradbury [Fri, 27 Apr 2018 11:50:30 +0000 (11:50 +0000)]
[RISCV] Add remat.ll test case
This test case demonstrates suboptimal codegen due to the fact that simple
constants aren't recognised as rematerialisable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331028
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David Green [Fri, 27 Apr 2018 11:29:49 +0000 (11:29 +0000)]
[ARM] Enable misched for R52.
Back when the R52 schedule was added in rL286949, there was no way
to enable machine schedules in ARM for specific cores. Since then a
target feature has been added. This enables the feature for R52,
removing the need to manually specify compiler flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331027
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Mikhail Maltsev [Fri, 27 Apr 2018 09:12:12 +0000 (09:12 +0000)]
[IR] Do not assume that function pointers are aligned
Summary:
The value tracking analysis uses function alignment to infer that the
least significant bits of function pointers are known to be zero.
Unfortunately, this is not correct for ARM targets: the least
significant bit of a function pointer stores the ARM/Thumb state
information (i.e., the LSB is set for Thumb functions and cleared for
ARM functions).
The original approach (https://reviews.llvm.org/D44781) introduced a
new field for function pointer alignment in the DataLayout structure
to address this. But it seems unlikely that optimizations based on
function pointer alignment would bring much benefit in practice to
justify the additional maintenance burden, so this patch simply
assumes that function pointer alignment is always unknown.
Reviewers: javed.absar, efriedma
Reviewed By: efriedma
Subscribers: kristof.beyls, llvm-commits, hfinkel, rogfer01
Differential Revision: https://reviews.llvm.org/D46110
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331025
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Petar Jovanovic [Fri, 27 Apr 2018 09:12:08 +0000 (09:12 +0000)]
[mips] Add support for Virtualization ASE
This includes
Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall
mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0,
Assembler directives: .set virt, .set novirt, .module virt, .module novirt
Attribute: virt
.MIPS.abiflags: VZ (0x100)
Patch by Vladimir Stefanovic.
Differential Revision: https://reviews.llvm.org/D44905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331024
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Serguei Katkov [Fri, 27 Apr 2018 08:02:50 +0000 (08:02 +0000)]
[SCEV] Add trivial case handling for umin utilities. NFC.
Reviewers: sanjoy, mkazantsev
Reviewed By: mkazantsev
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331022
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Serguei Katkov [Fri, 27 Apr 2018 03:56:53 +0000 (03:56 +0000)]
[SCEV] Introduce bulk umin creation utilities
Add new umin creation method which accepts a list of operands.
SCEV does not represents umin which is required in getExact, so
it transforms umin to umax with not. As a result the transformation of
tree of max to max with several operands does not work.
We just use the new introduced method for creation umin from several operands.
Reviewers: sanjoy, mkazantsev
Reviewed By: sanjoy
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46047
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331015
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Matt Morehouse [Fri, 27 Apr 2018 01:48:09 +0000 (01:48 +0000)]
Revert "[SimplifyLibcalls] Replace locked IO with unlocked IO"
This reverts r331002 due to sanitizer bot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331011
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Eli Friedman [Fri, 27 Apr 2018 00:32:24 +0000 (00:32 +0000)]
[LowerTypeTests] Mark .cfi.jumptable nounwind.
It doesn't unwind, and the wrong marking leads to the creation of an
.eh_frame section when it isn't necessary.
Differential Revision: https://reviews.llvm.org/D46082
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331008
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Eli Friedman [Fri, 27 Apr 2018 00:21:34 +0000 (00:21 +0000)]
[MachineOutliner] Don't outline from functions with a section marking.
The program might have unusual expectations for functions; for example,
the Linux kernel's build system warns if it finds references from .text
to .init.data.
I'm not sure this is something we actually want to make any guarantees
about (there isn't any explicit rule that would disallow outlining
in this case), but we might want to be conservative anyway.
Differential Revision: https://reviews.llvm.org/D46091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331007
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Sam Clegg [Fri, 27 Apr 2018 00:17:24 +0000 (00:17 +0000)]
typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331006
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Sam Clegg [Fri, 27 Apr 2018 00:17:21 +0000 (00:17 +0000)]
[WebAssembly] Section symbols must have local binding
Summary: Also test for symbols information in test/MC/WebAssembly/debug-info.ll.
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D46160
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331005
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David Bolvansky [Thu, 26 Apr 2018 22:31:43 +0000 (22:31 +0000)]
[SimplifyLibcalls] Replace locked IO with unlocked IO
Summary: If file stream arg is not captured and source is fopen, we could replace IO calls by unlocked IO ("_unlocked" function variants) to gain better speed,
Reviewers: efriedma, RKSimon, spatel, sanjoy, hfinkel, majnemer
Subscribers: lebedev.ri, llvm-commits
Differential Revision: https://reviews.llvm.org/D45736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331002
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Matt Davis [Thu, 26 Apr 2018 22:30:40 +0000 (22:30 +0000)]
[MCA] [NFC] Remove unused Index formal from ResourceManager::issueInstruction
Summary: The instruction index was never referenced in the body. Just a minor cleanup.
Reviewers: andreadb
Reviewed By: andreadb
Subscribers: javed.absar, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D46142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331001
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Matt Davis [Thu, 26 Apr 2018 21:55:45 +0000 (21:55 +0000)]
[Docs] Escape the @ symbol, so that it appears in documentation output. [NFC]
Summary:
The '@' character is a special character in Doxygen. In a handful of cases we were not escaping this character which resulted in llvm intrinsics not being rendered properly. Specifically, the @llvm part was removed.
For example, see https://llvm.org/doxygen/classllvm_1_1AssumptionCache.html. There are a few references to '.assume' without the @llvm. prefix. This patch corrects this.
Reviewers: sanjoy
Reviewed By: sanjoy
Subscribers: llvm-commits, sanjoy
Differential Revision: https://reviews.llvm.org/D45981
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330998
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Chandler Carruth [Thu, 26 Apr 2018 21:46:01 +0000 (21:46 +0000)]
[x86] Revert r330322 (& r330323): Lowering x86 adds/addus/subs/subus intrinsics
The LLVM commit introduces a crash in LLVM's instruction selection.
I filed http://llvm.org/PR37260 with the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330997
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Roman Lebedev [Thu, 26 Apr 2018 21:41:56 +0000 (21:41 +0000)]
[InstCombine][NFC] Regenerate checks in or-xor.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330996
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Reid Kleckner [Thu, 26 Apr 2018 21:13:59 +0000 (21:13 +0000)]
Fix WAsm dwarfdump.ll test on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330995
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Roman Lebedev [Thu, 26 Apr 2018 21:13:09 +0000 (21:13 +0000)]
[InstCombine][NFC] Regenerate checks in and-or-not.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330994
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Adrian Prantl [Thu, 26 Apr 2018 20:59:58 +0000 (20:59 +0000)]
Revert "Fix a bug that prevents global variables from having a DW_OP_deref."
This reverts commit r3309704 while investigating bot breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330993
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Sanjoy Das [Thu, 26 Apr 2018 20:52:28 +0000 (20:52 +0000)]
[InstCombine] Simplify Add with remainder expressions as operands.
Summary:
Simplify integer add expression X % C0 + (( X / C0 ) % C1) * C0 to
X % (C0 * C1). This is a common pattern seen in code generated by the XLA
GPU backend.
Add test cases for this new optimization.
Patch by Bixia Zheng!
Reviewers: sanjoy
Reviewed By: sanjoy
Subscribers: efriedma, craig.topper, lebedev.ri, llvm-commits, jlebar
Differential Revision: https://reviews.llvm.org/D45976
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330992
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Sanjoy Das [Thu, 26 Apr 2018 20:52:27 +0000 (20:52 +0000)]
Add test cases to prepare for the optimization that simplifies Add with
remainder expressions as operands.
Summary:
Add test cases to prepare for the new optimization that Simplifies integer add
expression X % C0 + (( X / C0 ) % C1) * C0 to X % (C0 * C1).
Patch by Bixia Zheng!
Reviewers: sanjoy
Reviewed By: sanjoy
Subscribers: jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46017
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330991
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Roman Tereshin [Thu, 26 Apr 2018 20:22:17 +0000 (20:22 +0000)]
[GlobalISel] Reporting rules covered as part of the InstructionSelect's debug-only printing
The main goal of this change is to make it much easier to track which
rules are actually covered by Testgen'erated regression tests.
Reviewers: aemerson, dsanders
Differential Revision: https://reviews.llvm.org/D46095
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330988
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Roman Lebedev [Thu, 26 Apr 2018 20:07:17 +0000 (20:07 +0000)]
[InstCombine][NFC] add2.ll: add a few commutative checks.
Fixes some missing test coverage in InstCombineAddSub.cpp, visitAdd()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330986
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Roman Lebedev [Thu, 26 Apr 2018 20:07:12 +0000 (20:07 +0000)]
[InstCombine][NFC] Autogenerate checks in add2.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330985
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Simon Atanasyan [Thu, 26 Apr 2018 19:55:28 +0000 (19:55 +0000)]
[mips] Accept 32-bit offsets for lb and lbu commands
`lb` and `lbu` commands accepts 16-bit signed offsets. But GAS accepts
larger offsets for these commands. If an offset does not fit in 16-bit
range, `lb` command is translated into lui/lb or lui/addu/lb series.
It's interesting that initially LLVM assembler supported this feature,
but later it was broken.
This patch restores support for 32-bit offsets. It replaces `mem_simm16`
operand for `LB` and `LBu` definitions by the new `mem_simmptr` operand.
This operand is intended to check that offset fits to the same size as
using for pointers. Later we will be able to extend this rule and
accepts 64-bit offsets when it is possible.
Some issues remain:
- The regression also affects LD, SD, LH, LHU commands. I'm going
to fix them by a separate patch.
- GAS accepts any 32-bit values as an offset. Now LLVM accepts signed
16-bit values and this patch extends the range to signed 32-bit offsets.
In other words, the following code accepted by GAS and still triggers
an error by LLVM:
```
lb $4, 0x80000004
# gas
lui a0, 0x8000
lb a0, 4(a0)
```
- In case of 64-bit pointers GAS accepts a 64-bit offset and translates
it to the li/dsll/lb series of commands. LLVM still rejects it.
Probably this feature has never been implemented in LLVM. This issue
is for a separate patch.
```
lb $4, 0x800000001
# gas
li a0, 0x8000
dsll a0, a0, 0x14
lb a0, 4(a0)
```
Differential Revision: https://reviews.llvm.org/D45020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330983
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Sam Clegg [Thu, 26 Apr 2018 19:27:28 +0000 (19:27 +0000)]
[WebAssembly] Write DWARF data into wasm object file
- Writes ".debug_XXX" into corresponding custom sections.
- Writes relocation records into "reloc.debug_XXX" sections.
Patch by Yury Delendik!
Differential Revision: https://reviews.llvm.org/D44184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330982
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Matt Arsenault [Thu, 26 Apr 2018 19:21:37 +0000 (19:21 +0000)]
DAG: Fix not legalizing vector fcanonicalizes
If an fcanoncialize was done on a vector type that was legal,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330981
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Matt Arsenault [Thu, 26 Apr 2018 19:21:32 +0000 (19:21 +0000)]
AMDGPU: Extend extract_vector_elt fneg combine to fabs
Fixes a regression in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330980
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Matt Arsenault [Thu, 26 Apr 2018 19:21:26 +0000 (19:21 +0000)]
AMDGPU: Consolidate SubtargetPredicate definitions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330979
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Justin Bogner [Thu, 26 Apr 2018 19:15:25 +0000 (19:15 +0000)]
Specify REQUIRES: default_triple in a few tests
These were all failing when specifying LLVM_DEFAULT_TARGET_TRIPLE=''.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330977
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Geoff Berry [Thu, 26 Apr 2018 18:50:45 +0000 (18:50 +0000)]
[AArch64] Fix scavenged spill slot base when stack realignment required.
Summary:
Use the FP for scavenged spill slot accesses to prevent corruption of
the callee-save region when the SP is re-aligned.
Based on problem and patch reported by @paulwalker-arm
This is an alternative to solution proposed in D45770
Reviewers: t.p.northover, paulwalker-arm, thegameg, javed.absar
Subscribers: qcolombet, mcrosier, paulwalker-arm, kristof.beyls, rengolin, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D46063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330976
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Roman Lebedev [Thu, 26 Apr 2018 18:44:37 +0000 (18:44 +0000)]
[NFC][InstCombine] rem.ll: add a few commutative tests.
This closes a gap in missing test coverage in
isKnownToBeAPowerOfTwo() from ValueTracking.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330975
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Roman Lebedev [Thu, 26 Apr 2018 18:44:32 +0000 (18:44 +0000)]
[NFC][InstCombine] Regenerate rem.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330974
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Alexander Shaposhnikov [Thu, 26 Apr 2018 18:28:17 +0000 (18:28 +0000)]
[llvm-objcopy] Implement --redefine-sym option
This diff implements --redefine-sym option
for changing the name of a symbol.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D46029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330973
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Michael Berg [Thu, 26 Apr 2018 18:17:58 +0000 (18:17 +0000)]
augmenting description for fcmp fmf - NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330972
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Adrian Prantl [Thu, 26 Apr 2018 18:17:04 +0000 (18:17 +0000)]
Fix a bug that prevents global variables from having a DW_OP_deref.
For local variables the first DW_OP_deref is consumed by turning the
location kind into a memeory location, but that only makes sense for
values that are in a register to begin with, which cannot happen for
global variables that are attached to a symbol.
rdar://problem/
39741860
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330970
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Sam Clegg [Thu, 26 Apr 2018 18:15:32 +0000 (18:15 +0000)]
[WebAssembly] Add version to object file metadata
Summary: See https://github.com/WebAssembly/tool-conventions/issues/54
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D46069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330969
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Andrea Di Biagio [Thu, 26 Apr 2018 18:03:24 +0000 (18:03 +0000)]
[Tablegen] SubtargetEmitter: move the logic that prints predicates for variant scheduling classes to helper functions. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330968
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Haicheng Wu [Thu, 26 Apr 2018 17:56:50 +0000 (17:56 +0000)]
[GlobalMerge] Fix a typo
now => know
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330965
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Vlad Tsyrklevich [Thu, 26 Apr 2018 17:54:53 +0000 (17:54 +0000)]
Revert "Enable EliminateAvailableExternally pass for -O1"
This reverts commit r330961 because it breaks a handful of clang tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330964
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Paul Semel [Thu, 26 Apr 2018 17:44:43 +0000 (17:44 +0000)]
[llvm-objcopy] Add --localize-symbol option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330963
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Vlad Tsyrklevich [Thu, 26 Apr 2018 17:34:51 +0000 (17:34 +0000)]
Update stale comment in AsmWriter.cpp
Summary:
The old comment referred to llvm/IR/Writer.h which doesn't longer exist.
This patch replaces it with an up-to-date description of AsmWriter library.
Patch by Alex Yursha.
Reviewers: gribozavr, vlad.tsyrklevich
Reviewed By: vlad.tsyrklevich
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330962
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Vlad Tsyrklevich [Thu, 26 Apr 2018 17:33:24 +0000 (17:33 +0000)]
Enable EliminateAvailableExternally pass for -O1
Summary:
Follow-up to D43690, the EliminateAvailableExternally pass currently
runs under -O0 and -O2 and up. Under -O1 we would still want to drop
available_externally symbols to reduce space without inlining having
run.
Reviewers: tejohnson
Reviewed By: tejohnson
Subscribers: mehdi_amini, llvm-commits, kcc
Differential Revision: https://reviews.llvm.org/D46093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330961
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Sam Clegg [Thu, 26 Apr 2018 17:05:04 +0000 (17:05 +0000)]
[WebAssembly] objdump: Don't assume all relocations have symbols
Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D46134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330959
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Sanjay Patel [Thu, 26 Apr 2018 17:04:07 +0000 (17:04 +0000)]
[docs] provide the specific sanitizer option to detect junk-in-the-ftrunc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330958
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Sam Clegg [Thu, 26 Apr 2018 16:41:51 +0000 (16:41 +0000)]
[WebAssembly] Implement getRelocationValueString()
And use it in llvm-objdump.
Differential Revision: https://reviews.llvm.org/D46092
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330957
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Simon Dardis [Thu, 26 Apr 2018 16:22:47 +0000 (16:22 +0000)]
[mips] Fix a test case which is keeping the expensive checks bot win red (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330956
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Mark Searles [Thu, 26 Apr 2018 16:11:19 +0000 (16:11 +0000)]
[AMDGPU][Waitcnt] As of gfx7, VMEM operations do not increment the export counter and the input registers are available in the next instruction; update the waitcnt pass to take this into account.
Differential Revision: https://reviews.llvm.org/D46067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330954
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Simon Dardis [Thu, 26 Apr 2018 16:06:34 +0000 (16:06 +0000)]
[mips] Correct the definitions of some control instructions
Correct the definitions of ei, di, eret, deret, wait, syscall and break.
Also provide microMIPS specific aliases to match the MIPS aliases.
Additionally correct the definition of the wait instruction so that
it is present in the instruction mapping tables.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D45939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330952
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Sanjay Patel [Thu, 26 Apr 2018 16:04:44 +0000 (16:04 +0000)]
[DAGCombiner] limit ftrunc optimizations with function attribute
As noted, the attribute name is subject to change once we have
the clang side implemented, but it's clear that we need some
kind of attribute-based predication here based on the discussion
for:
rL330437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330951
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Sanjay Patel [Thu, 26 Apr 2018 15:36:15 +0000 (15:36 +0000)]
[x86] add tests to show potential opt-out of ftrunc optimization; NFC
This is another preliminary step for disabling this transform as
discussed in the post-commit thread for:
rL330437
I'm using one of the names suggested there for the attribute, but
we can fix that up as needed once the clang side of this is sorted
out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330950
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Alex Bradbury [Thu, 26 Apr 2018 15:34:27 +0000 (15:34 +0000)]
[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
This causes some slight shuffling but no meaningful codegen differences on the
corpus I used for testing, but it has a larger impact when combined with e.g.
rematerialisation. Regardless, it makes sense to report as accurate
target-specific information as possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330949
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Benjamin Kramer [Thu, 26 Apr 2018 15:26:29 +0000 (15:26 +0000)]
[NVPTX] Make the legalizer expand shufflevector of <2 x half>
There's no direct instruction for this, but it's trivially implemented
with two movs. Without this the code generator just dies when
encountering a shufflevector.
Differential Revision: https://reviews.llvm.org/D46116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330948
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Sanjay Patel [Thu, 26 Apr 2018 15:20:18 +0000 (15:20 +0000)]
[DAGCombiner] refactor FP->int->FP folds; NFC
As discussed in the post-review comments for rL330437,
we need to guard this fold to allow existing code to
keep working with the undefined behavior that they've
come to rely on.
That would mean duplicating more code than we already
have, so let's fix that first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330947
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Matthew Simpson [Thu, 26 Apr 2018 14:50:04 +0000 (14:50 +0000)]
[SLP] Add tests for transposable binary operations
These test cases are vectorizable, but we are currently unable to vectorize
them effectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330945
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Alex Bradbury [Thu, 26 Apr 2018 14:04:18 +0000 (14:04 +0000)]
[RISCV] Implement isZextFree
This returns true for 8-bit and 16-bit loads, allowing LBU/LHU to be selected
and avoiding unnecessary masks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330943
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Alex Bradbury [Thu, 26 Apr 2018 14:00:35 +0000 (14:00 +0000)]
[RISCV] Add test case showing suboptimal codegen when loading unsigned char/short
Implementing isZextFree will allow lbu or lhu to be selected rather than
lb+mask and lh+mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330942
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Matthew Simpson [Thu, 26 Apr 2018 13:48:33 +0000 (13:48 +0000)]
[TTI, AArch64] Add transpose shuffle kind
This patch adds a new shuffle kind useful for transposing a 2xn matrix. These
transpose shuffle masks read corresponding even- or odd-numbered vector
elements from two n-dimensional source vectors and write each result into
consecutive elements of an n-dimensional destination vector. The transpose
shuffle kind is meant to model the TRN1 and TRN2 AArch64 instructions. As such,
this patch also considers transpose shuffles in the AArch64 implementation of
getShuffleCost.
Differential Revision: https://reviews.llvm.org/D45982
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330941
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Alex Bradbury [Thu, 26 Apr 2018 13:37:00 +0000 (13:37 +0000)]
[RISCV] Implement isTruncateFree
Adapted from ARM's implementation introduced in r313533 and r314280.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330940
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Lama Saba [Thu, 26 Apr 2018 13:16:11 +0000 (13:16 +0000)]
[X86] Fix Update Kill Register in Avoid SFB Pass - Bug 37153
Differential Revision: https://reviews.llvm.org/D45823
Change-Id: Icf6f34f6babc3cb2ff5292fde003472473037a71
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330939
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Alex Bradbury [Thu, 26 Apr 2018 13:15:17 +0000 (13:15 +0000)]
[RISCV] Implement isLegalICmpImmediate
I'm unable to construct a representative test case that demonstrates the
advantage, but it seems sensible to report accurate target-specific
information regardless.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330938
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Alex Bradbury [Thu, 26 Apr 2018 13:00:37 +0000 (13:00 +0000)]
[RISCV] Implement isLegalAddImmediate
This causes a trivial improvement in the recently added lsr-legaladdimm.ll
test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330937
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Alex Bradbury [Thu, 26 Apr 2018 12:57:29 +0000 (12:57 +0000)]
[RISCV] Add test/CodeGen/RISCV/lsr-legaladdimm.ll
Add a test case which will show a codegen difference upon the implementation
of a target-specific isLegalAddImmediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330936
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Andrea Di Biagio [Thu, 26 Apr 2018 12:56:26 +0000 (12:56 +0000)]
[Tablegen] Simplify code in CodeGenSchedule. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330935
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Sander de Smalen [Thu, 26 Apr 2018 12:54:42 +0000 (12:54 +0000)]
[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.
Patch [2/2] in a series to improve assembler diagnostics for SVE:
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330934
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Benjamin Kramer [Thu, 26 Apr 2018 12:30:16 +0000 (12:30 +0000)]
[NVPTX] Deduplicate code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330933
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Alex Bradbury [Thu, 26 Apr 2018 12:13:48 +0000 (12:13 +0000)]
[RISCV] Implement isLegalAddressingMode for RISC-V
This has no impact on codegen for the current RISC-V unit tests or my small
benchmark set and very minor changes in a few programs in the GCC torture
suite. Based on this, I haven't been able to produce a representative test
program that demonstrates a benefit from isLegalAddressingMode. I'm committing
the patch anyway, on the basis that presenting accurate information to the
target-independent code is preferable to relying on incorrect generic
assumptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330932
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Florian Hahn [Thu, 26 Apr 2018 10:26:17 +0000 (10:26 +0000)]
[LoopInterchange] Ignore debug intrinsics during legality checks.
Reviewers: aprantl, mcrosier, karthikthecool
Reviewed By: aprantl
Subscribers: mattd, vsk, #debug-info, llvm-commits
Differential Revision: https://reviews.llvm.org/D45379
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330931
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Sander de Smalen [Thu, 26 Apr 2018 09:24:45 +0000 (09:24 +0000)]
[AsmMatcher] Extend PredicateMethod with optional DiagnosticPredicate
An optional, light-weight and backward-compatible mechanism to allow
specifying that a diagnostic _only_ applies to a partial mismatch (NearMiss),
rather than a full mismatch.
Patch [1/2] in a series to improve assembler diagnostics for SVE.
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: olista01
Differential Revision: https://reviews.llvm.org/D45879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330930
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Sander de Smalen [Thu, 26 Apr 2018 08:43:22 +0000 (08:43 +0000)]
[AArch64][SVE] Asm: Negative tests for all LD1 gather (scalar+vector) load instructions.
Patch [3/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45958
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330929
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Sander de Smalen [Thu, 26 Apr 2018 08:19:53 +0000 (08:19 +0000)]
[AArch64][SVE] Asm: Support for gather LD1/LDFF1 (scalar + vector) load instructions.
Patch [2/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46023
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330928
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Shoaib Meenai [Thu, 26 Apr 2018 06:04:46 +0000 (06:04 +0000)]
[cmake] Make linker detection take flags into account
LLVM might be compiled using a toolchain file which controls the linker
to use via flags (e.g. `-B` or `-fuse-ld=`). Take these flags into
account for linker detection. We can also correct the detection by
manually passing LLVM_USE_LINKER, of course, but it seems more
convenient to have the detection take flags into account.
Differential Revision: https://reviews.llvm.org/D45464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330924
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Craig Topper [Thu, 26 Apr 2018 05:07:40 +0000 (05:07 +0000)]
[X86] Print 'tbyte ptr' instead of 'xword ptr' for f80mem in Intel syntax.
This matches objdump.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330922
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Craig Topper [Thu, 26 Apr 2018 03:53:39 +0000 (03:53 +0000)]
[X86] Remove alignment restriction on loading folding of pcmp[ei]str* during isel too.
This is a follow up to the changes in r330896 which enabled folding after isel during peephole and register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330897
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Chandler Carruth [Thu, 26 Apr 2018 03:17:25 +0000 (03:17 +0000)]
[x86] Allow folding unaligned memory operands into pcmp[ei]str*
instructions.
These have special permission according to the x86 manual to read
unaligned memory, and this folding is done by ICC and GCC as well.
This corrects one of the issues identified in PR37246.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330896
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Chandler Carruth [Thu, 26 Apr 2018 03:12:17 +0000 (03:12 +0000)]
[x86] NFC: Add tests for idiomatic usage patterns of SSE4.2 string
comparison instructions (pcmp[ei]stri*).
These will help show improvements from fixes to PR37246.
I've not really covered the mask forms of this intrinsic as I don't have
as good of an intuition about the likely usage patterns there. Happy for
someone to extend this with tests covering the mask form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330895
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Max Kazantsev [Thu, 26 Apr 2018 02:07:40 +0000 (02:07 +0000)]
Revert "[SCEV] Make computeExitLimit more simple and more powerful"
This reverts commit
023c8be90980e0180766196cba86f81608b35d38.
This patch triggers miscompile of zlib on PowerPC platform. Most likely it is
caused by some pre-backend PPC-specific pass, but we don't clearly know the
reason yet. So we temporally revert this patch with intention to return it
once the problem is resolved. See bug 37229 for details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330893
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Reid Kleckner [Wed, 25 Apr 2018 23:34:15 +0000 (23:34 +0000)]
[codeview] Ignore .cv_loc directives at the end of a function
If no data or instructions are emitted after a location directive, we
should clear the cv_loc when we change sections, or it will be emitted
at the beginning of the next section. This violates our invariant that
all .cv_loc directives belong to the same section. Add clearer
assertions for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330884
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Vedant Kumar [Wed, 25 Apr 2018 21:50:09 +0000 (21:50 +0000)]
[ADT] Make filter_iterator support bidirectional iteration
This makes it possible to reverse a filtered range. For example, here's
a way to visit memory accesses in a BasicBlock in reverse order:
auto MemInsts = reverse(make_filter_range(BB, [](Instruction &I) {
return isa<StoreInst>(&I) || isa<LoadInst>(&I);
}));
for (auto &MI : MemInsts)
...
To implement this functionality, I factored out forward iteration
functionality into filter_iterator_base, and added a specialization of
filter_iterator_impl which supports bidirectional iteration. Thanks to
Tim Shen, Zachary Turner, and others for suggesting this design and
providing feedback! This version of the patch supersedes the original
(https://reviews.llvm.org/D45792).
This was motivated by a problem we encountered in D45657: we'd like to
visit the non-debug-info instructions in a BasicBlock in reverse order.
Testing: check-llvm, check-clang
Differential Revision: https://reviews.llvm.org/D45853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330875
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Simon Pilgrim [Wed, 25 Apr 2018 20:59:16 +0000 (20:59 +0000)]
[CostModel][X86] Remove hard coded SDIV/UDIV vector costs
Algorithmically compute the 'x20' SDIV/UDIV vector costs - this is necessary for PR36550 when DIV costs will be driven from the scheduler models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330870
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Reid Kleckner [Wed, 25 Apr 2018 20:16:24 +0000 (20:16 +0000)]
Fix PluginsTests failure on Windows buildbots by enabling it everywhere
lit is picking up a stale executable in the unittests tree, which is
failing on Windows.
To simplify the CMake and avoid problems like this in the future, now we
always compile the test, but the test exits successfully when plugins
are not enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330867
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Tom Stellard [Wed, 25 Apr 2018 20:02:53 +0000 (20:02 +0000)]
AMDGPU/R600: Move int_r600_store_stream_output to the public intrinsic file
Summary:
The TableGen'd GlobalISel instruction selector assumes all intrinsics are in
the public Intrinsic:: namespace.
Reviewers: jvesely, nhaehnle
Reviewed By: jvesely, nhaehnle
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D45989
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330866
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Mark Searles [Wed, 25 Apr 2018 19:21:26 +0000 (19:21 +0000)]
[AMDGPU] Waitcnt pass: add debug options
- Add "amdgpu-waitcnt-forcezero" to force all waitcnt instrs to be emitted as s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
- Add debug counters to control force emit of s_waitcnt instrs; debug counters:
si-insert-waitcnts-forceexp: force emit s_waitcnt expcnt(0) instrs
si-insert-waitcnts-forcevm: force emit s_waitcnt lgkmcnt(0) instrs
si-insert-waitcnts-forcelgkm: force emit s_waitcnt vmcnt(0) instrs
- Add some debug statements
Note that a variant of this patch was previously committed/reverted.
Differential Revision: https://reviews.llvm.org/D45888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330862
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David Bolvansky [Wed, 25 Apr 2018 18:58:53 +0000 (18:58 +0000)]
[SimplifyLibcalls] Atoi, strtol replacements
Reviewers: spatel, lebedev.ri, xbolva00, efriedma
Reviewed By: xbolva00, efriedma
Subscribers: efriedma, llvm-commits
Differential Revision: https://reviews.llvm.org/D45418
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330860
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Francis Visoiu Mistrih [Wed, 25 Apr 2018 18:58:06 +0000 (18:58 +0000)]
[MIR] Add support for debug metadata for fixed stack objects
Debug var, expr and loc were only supported for non-fixed stack objects.
This patch adds the following fields to the "fixedStack:" entries, and
renames the ones from "stack:" to:
* debug-info-variable
* debug-info-expression
* debug-info-location
Differential Revision: https://reviews.llvm.org/D46032
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330859
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Nico Weber [Wed, 25 Apr 2018 18:34:00 +0000 (18:34 +0000)]
IWYU llvm-config.h for LLVM_VERSION_STRING
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330856
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Sam Clegg [Wed, 25 Apr 2018 18:24:08 +0000 (18:24 +0000)]
[WebAssebmly] Add Module name to WasmSymbol
Imports in a wasm module can have custom module name. This change
adds the module name to the WasmSymbol structure so that the linker
can preserve this module name.
This is needed to fix: https://bugs.llvm.org/show_bug.cgi?id=37168
Differential Revision: https://reviews.llvm.org/D45797
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330854
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Nico Weber [Wed, 25 Apr 2018 18:06:23 +0000 (18:06 +0000)]
Rename sancov.cc to sancov.cpp
LLVM uses cpp as its C++ file ending.
https://reviews.llvm.org/D46068
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330853
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Simon Pilgrim [Wed, 25 Apr 2018 18:03:31 +0000 (18:03 +0000)]
[CostModel][X86] Add div/rem tests for non-uniform constant divisors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330852
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Craig Topper [Wed, 25 Apr 2018 17:35:03 +0000 (17:35 +0000)]
[X86] Form MUL_IMM for multiplies with 3/5/9 to encourage LEA formation over load folding.
Previously we only formed MUL_IMM when we split a constant. This blocked load folding on those cases. We should also form MUL_IMM for 3/5/9 to favor LEA over load folding.
Differential Revision: https://reviews.llvm.org/D46040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330850
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Reid Kleckner [Wed, 25 Apr 2018 17:30:00 +0000 (17:30 +0000)]
Revert r330755 "[lit] Report line number for failed RUN command"
It is causing many tests to fail on Windows buildbots:
http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/10211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330848
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Alex Bradbury [Wed, 25 Apr 2018 17:25:29 +0000 (17:25 +0000)]
[RISCV] Allow call pseudoinstruction to be used to call a function name that coincides with a register name
Previously `call zero`, `call f0` etc would fail. This leads to compilation
failures if building programs that define functions with those names and using
-save-temps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330846
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Nico Weber [Wed, 25 Apr 2018 17:24:41 +0000 (17:24 +0000)]
Don't list a source file twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330845
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Taewook Oh [Wed, 25 Apr 2018 17:19:21 +0000 (17:19 +0000)]
[ICP] Do not attempt type matching for variable length arguments.
Summary:
When performing indirect call promotion, current implementation inspects "all" parameters of the callsite and attemps to match with the formal argument type of the callee function. However, it is not possible to find the type for variable length arguments, and the compiler crashes when it attemps to match the type for variable lenght argument.
It seems that the bug is introduced with D40658. Prior to that, the type matching is performed only for the parameters whose ID is less than callee->getFunctionNumParams(). The attached test case will crash without the patch.
Reviewers: mssimpso, davidxl, davide
Reviewed By: mssimpso
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330844
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