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Philippe Mathieu-Daudé [Thu, 5 Mar 2020 12:12:49 +0000 (13:12 +0100)]
hw/scsi/spapr_vscsi: Simplify a bit
We already have a 'iu' pointer, use it
(this simplifies the next commit).
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20200305121253.19078-4-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Philippe Mathieu-Daudé [Thu, 5 Mar 2020 12:12:48 +0000 (13:12 +0100)]
hw/scsi/spapr_vscsi: Use SRP_MAX_IU_LEN instead of sizeof flexible array
Replace sizeof() flexible arrays union srp_iu/viosrp_iu by the
SRP_MAX_IU_LEN definition, which is what this code actually meant
to use.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20200305121253.19078-3-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Philippe Mathieu-Daudé [Thu, 5 Mar 2020 12:12:47 +0000 (13:12 +0100)]
hw/scsi/viosrp: Add missing 'hw/scsi/srp.h' include
This header use the srp_* structures declared in "hw/scsi/srp.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20200305121253.19078-2-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
David Gibson [Fri, 29 Nov 2019 00:49:04 +0000 (11:49 +1100)]
spapr: Clean up RMA size calculation
Move the calculation of the Real Mode Area (RMA) size into a helper
function. While we're there clean it up and correct it in a few ways:
* Add comments making it clearer where the various constraints come from
* Remove a pointless check that the RMA fits within Node 0 (we've just
clamped it so that it does)
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Wed, 19 Feb 2020 09:53:13 +0000 (20:53 +1100)]
spapr: Don't clamp RMA to 16GiB on new machine types
In spapr_machine_init() we clamp the size of the RMA to 16GiB and the
comment saying why doesn't make a whole lot of sense. In fact, this was
done because the real mode handling code elsewhere limited the RMA in TCG
mode to the maximum value configurable in LPCR[RMLS], 16GiB.
But,
* Actually LPCR[RMLS] has been able to encode a 256GiB size for a very
long time, we just didn't implement it properly in the softmmu
* LPCR[RMLS] shouldn't really be relevant anyway, it only was because we
used to abuse the RMOR based translation mode in order to handle the
fact that we're not modelling the hypervisor parts of the cpu
We've now removed those limitations in the modelling so the 16GiB clamp no
longer serves a function. However, we can't just remove the limit
universally: that would break migration to earlier qemu versions, where
the 16GiB RMLS limit still applies, no matter how bad the reasons for it
are.
So, we replace the 16GiB clamp, with a clamp to a limit defined in the
machine type class. We set it to 16 GiB for machine types 4.2 and earlier,
but set it to 0 meaning unlimited for the new 5.0 machine type.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Thu, 28 Nov 2019 05:37:04 +0000 (16:37 +1100)]
spapr: Don't attempt to clamp RMA to VRMA constraint
The Real Mode Area (RMA) is the part of memory which a guest can access
when in real (MMU off) mode. Of course, for a guest under KVM, the MMU
isn't really turned off, it's just in a special translation mode - Virtual
Real Mode Area (VRMA) - which looks like real mode in guest mode.
The mechanics of how this works when using the hash MMU (HPT) put a
constraint on the size of the RMA, which depends on the size of the
HPT. So, the latter part of spapr_setup_hpt_and_vrma() clamps the RMA
we advertise to the guest based on this VRMA limit.
There are several things wrong with this:
1) spapr_setup_hpt_and_vrma() doesn't actually clamp, it takes the minimum
of Node 0 memory size and the VRMA limit. That will *often* work the
same as clamping, but there can be other constraints on RMA size which
supersede Node 0 memory size. We have real bugs caused by this
(currently worked around in the guest kernel)
2) Some callers of spapr_setup_hpt_and_vrma() are in a situation where
we're past the point that we can actually advertise an RMA limit to the
guest
3) But most fundamentally, the VRMA limit depends on host configuration
(page size) which shouldn't be visible to the guest, but this partially
exposes it. This can cause problems with migration in certain edge
cases, although we will mostly get away with it.
In practice, this clamping is almost never applied anyway. With 64kiB
pages and the normal rules for sizing of the HPT, the theoretical VRMA
limit will be 4x(guest memory size) and so never hit. It will hit with
4kiB pages, where it will be (guest memory size)/4. However all mainstream
distro kernels for POWER have used a 64kiB page size for at least 10 years.
So, simply replace this logic with a check that the RMA we've calculated
based only on guest visible configuration will fit within the host implied
VRMA limit. This can break if running HPT guests on a host kernel with
4kiB page size. As noted that's very rare. There also exist several
possible workarounds:
* Change the host kernel to use 64kiB pages
* Use radix MMU (RPT) guests instead of HPT
* Use 64kiB hugepages on the host to back guest memory
* Increase the guest memory size so that the RMA hits one of the fixed
limits before the RMA limit. This is relatively easy on POWER8 which
has a 16GiB limit, harder on POWER9 which has a 1TiB limit.
* Use a guest NUMA configuration which artificially constrains the RMA
within the VRMA limit (the RMA must always fit within Node 0).
Previously, on KVM, we also temporarily reduced the rma_size to 256M so
that the we'd load the kernel and initrd safely, regardless of the VRMA
limit. This was a) confusing, b) could significantly limit the size of
images we could load and c) introduced a behavioural difference between
KVM and TCG. So we remove that as well.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Thu, 28 Nov 2019 05:12:06 +0000 (16:12 +1100)]
spapr,ppc: Simplify signature of kvmppc_rma_size()
This function calculates the maximum size of the RMA as implied by the
host's page size of structure of the VRMA (there are a number of other
constraints on the RMA size which will supersede this one in many
circumstances).
The current interface takes the current RMA size estimate, and clamps it
to the VRMA derived size. The only current caller passes in an arguably
wrong value (it will match the current RMA estimate in some but not all
cases).
We want to fix that, but for now just keep concerns separated by having the
KVM helper function just return the VRMA derived limit, and let the caller
combine it with other constraints. We call the new function
kvmppc_vrma_limit() to more clearly indicate its limited responsibility.
The helper should only ever be called in the KVM enabled case, so replace
its !CONFIG_KVM stub with an assert() rather than a dummy value.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cedric Le Goater <clg@fr.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Tue, 10 Dec 2019 05:25:04 +0000 (16:25 +1100)]
spapr: Don't use weird units for MIN_RMA_SLOF
MIN_RMA_SLOF records the minimum about of RMA that the SLOF firmware
requires. It lets us give a meaningful error if the RMA ends up too small,
rather than just letting SLOF crash.
It's currently stored as a number of megabytes, which is strange for global
constants. Move that megabyte scaling into the definition of the constant
like most other things use.
Change from M to MiB in the associated message while we're at it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Thu, 27 Feb 2020 04:29:26 +0000 (15:29 +1100)]
target/ppc: Don't store VRMA SLBE persistently
Currently, we construct the SLBE used for VRMA translations when the LPCR
is written (which controls some bits in the SLBE), then use it later for
translations.
This is a bit complex and confusing - simplify it by simply constructing
the SLBE directly from the LPCR when we need it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Mon, 6 Jan 2020 06:26:24 +0000 (17:26 +1100)]
target/ppc: Only calculate RMLS derived RMA limit on demand
When the LPCR is written, we update the env->rmls field with the RMA limit
it implies. Simplify things by just calculating the value directly from
the LPCR value when we need it.
It's possible this is a little slower, but it's unlikely to be significant,
since this is only for real mode accesses in a translation configuration
that's not used very often, and the whole thing is behind the qemu TLB
anyway. Therefore, keeping the number of state variables down and not
having to worry about making sure it's always in sync seems the better
option.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Mon, 6 Jan 2020 06:18:54 +0000 (17:18 +1100)]
target/ppc: Correct RMLS table
The table of RMA limits based on the LPCR[RMLS] field is slightly wrong.
We're missing the RMLS == 0 => 256 GiB RMA option, which is available on
POWER8, so add that.
The comment that goes with the table is much more wrong. We *don't* filter
invalid RMLS values when writing the LPCR, and there's not really a
sensible way to do so. Furthermore, while in theory the set of RMLS values
is implementation dependent, it seems in practice the same set has been
available since around POWER4+ up until POWER8, the last model which
supports RMLS at all. So, correct that as well.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Mon, 6 Jan 2020 05:52:26 +0000 (16:52 +1100)]
target/ppc: Streamline calculation of RMA limit from LPCR[RMLS]
Currently we use a big switch statement in ppc_hash64_update_rmls() to work
out what the right RMA limit is based on the LPCR[RMLS] field. There's no
formula for this - it's just an arbitrary mapping defined by the existing
CPU implementations - but we can make it a bit more readable by using a
lookup table rather than a switch. In addition we can use the MiB/GiB
symbols to make it a bit clearer.
While there we add a bit of clarity and rationale to the comment about
what happens if the LPCR[RMLS] doesn't contain a valid value.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Mon, 6 Jan 2020 05:35:10 +0000 (16:35 +1100)]
target/ppc: Use class fields to simplify LPCR masking
When we store the Logical Partitioning Control Register (LPCR) we have a
big switch statement to work out which are valid bits for the cpu model
we're emulating.
As well as being ugly, this isn't really conceptually correct, since it is
based on the mmu_model variable, whereas the LPCR isn't (only) about the
MMU, so mmu_model is basically just acting as a proxy for the cpu model.
Handle this in a simpler way, by adding a suitable lpcr_mask to the QOM
class.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Mon, 6 Jan 2020 02:14:16 +0000 (13:14 +1100)]
target/ppc: Remove RMOR register from POWER9 & POWER10
Currently we create the Real Mode Offset Register (RMOR) on all Book3S cpus
from POWER7 onwards. However the translation mode which the RMOR controls
is no longer supported in POWER9, and so the register has been removed from
the architecture.
Remove it from our model on POWER9 and POWER10.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Mon, 6 Jan 2020 02:12:34 +0000 (13:12 +1100)]
spapr, ppc: Remove VPM0/RMLS hacks for POWER9
For the "pseries" machine, we use "virtual hypervisor" mode where we
only model the CPU in non-hypervisor privileged mode. This means that
we need guest physical addresses within the modelled cpu to be treated
as absolute physical addresses.
We used to do that by clearing LPCR[VPM0] and setting LPCR[RMLS] to a high
limit so that the old offset based translation for guest mode applied,
which does what we need. However, POWER9 has removed support for that
translation mode, which meant we had some ugly hacks to keep it working.
We now explicitly handle this sort of translation for virtual hypervisor
mode, so the hacks aren't necessary. We don't need to set VPM0 and RMLS
from the machine type code - they're now ignored in vhyp mode. On the cpu
side we don't need to allow LPCR[RMLS] to be set on POWER9 in vhyp mode -
that was only there to allow the hack on the machine side.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Wed, 11 Dec 2019 11:33:02 +0000 (22:33 +1100)]
target/ppc: Introduce ppc_hash64_use_vrma() helper
When running guests under a hypervisor, the hypervisor obviously needs to
be protected from guest accesses even if those are in what the guest
considers real mode (translation off). The POWER hardware provides two
ways of doing that: The old way has guest real mode accesses simply offset
and bounds checked into host addresses. It works, but requires that a
significant chunk of the guest's memory - the RMA - be physically
contiguous in the host, which is pretty inconvenient. The new way, known
as VRMA, has guest real mode accesses translated in roughly the normal way
but with some special parameters.
In POWER7 and POWER8 the LPCR[VPM0] bit selected between the two modes, but
in POWER9 only VRMA mode is supported and LPCR[VPM0] no longer exists. We
handle that difference in behaviour in ppc_hash64_set_isi().. but not in
other places that we blindly check LPCR[VPM0].
Correct those instances with a new helper to tell if we should be in VRMA
mode.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
David Gibson [Fri, 3 Jan 2020 04:27:24 +0000 (15:27 +1100)]
target/ppc: Correct handling of real mode accesses with vhyp on hash MMU
On ppc we have the concept of virtual hypervisor ("vhyp") mode, where we
only model the non-hypervisor-privileged parts of the cpu. Essentially we
model the hypervisor's behaviour from the point of view of a guest OS, but
we don't model the hypervisor's execution.
In particular, in this mode, qemu's notion of target physical address is
a guest physical address from the vcpu's point of view. So accesses in
guest real mode don't require translation. If we were modelling the
hypervisor mode, we'd need to translate the guest physical address into
a host physical address.
Currently, we handle this sloppily: we rely on setting up the virtual LPCR
and RMOR registers so that GPAs are simply HPAs plus an offset, which we
set to zero. This is already conceptually dubious, since the LPCR and RMOR
registers don't exist in the non-hypervisor portion of the CPU. It gets
worse with POWER9, where RMOR and LPCR[VPM0] no longer exist at all.
Clean this up by explicitly handling the vhyp case. While we're there,
remove some unnecessary nesting of if statements that made the logic to
select the correct real mode behaviour a bit less clear than it could be.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Wed, 11 Dec 2019 10:55:05 +0000 (21:55 +1100)]
ppc: Remove stub of PPC970 HID4 implementation
The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor capability.
However, it can be (and often was) strapped into "Apple mode", where the
hypervisor capabilities were disabled (essentially putting it always in
hypervisor mode).
That's actually the only mode of the 970 we support in qemu, and we're
unlikely to change that any time soon. However, we do have a partial
implementation of the 970's HID4 register which affects things only
relevant for hypervisor mode.
That stub is also really ugly, since it attempts to duplicate the effects
of HID4 by re-encoding it into the LPCR register used in newer CPUs, but
in a really confusing way.
Just get rid of it.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
David Gibson [Wed, 11 Dec 2019 06:07:44 +0000 (17:07 +1100)]
ppc: Remove stub support for 32-bit hypervisor mode
a4f30719a8cd, way back in 2007 noted that "PowerPC hypervisor mode is not
fundamentally available only for PowerPC 64" and added a 32-bit version
of the MSR[HV] bit.
But nothing was ever really done with that; there is no meaningful support
for 32-bit hypervisor mode 13 years later. Let's stop pretending and just
remove the stubs.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Philippe Mathieu-Daudé [Fri, 28 Feb 2020 12:33:03 +0000 (13:33 +0100)]
hw/ppc/pnv: Fix typo in comment
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20200228123303.14540-1-philmd@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Shivaprasad G Bhat [Thu, 27 Feb 2020 13:42:49 +0000 (07:42 -0600)]
spapr: Fix Coverity warning while validating nvdimm options
Fixes Coverity issue,
CID
1419883: Error handling issues (CHECKED_RETURN)
Calling "qemu_uuid_parse" without checking return value
nvdimm_set_uuid() already verifies if the user provided uuid is valid or
not. So, need to check for the validity during pre-plug validation again.
As this a false positive in this case, assert if not valid to be safe.
Also, error_abort if QOM accessor encounters error while fetching the uuid
property.
Reported-by: Coverity (CID 1419883)
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Message-Id: <
158281096564.89540.
4507375445765515529.stgit@lep8c.aus.stglabs.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Greg Kurz [Wed, 26 Feb 2020 18:59:38 +0000 (19:59 +0100)]
ppc: Officially deprecate the CPU "compat" property
Server class POWER CPUs have a "compat" property, which was obsoleted
by commit
7843c0d60d and replaced by a "max-cpu-compat" property on the
pseries machine type. A hack was introduced so that passing "compat" to
-cpu would still produce the desired effect, for the sake of backward
compatibility : it strips the "compat" option from the CPU properties
and applies internally it to the pseries machine. The accessors of the
"compat" property were updated to do nothing but warn the user about the
deprecated status when doing something like:
$ qemu-system-ppc64 -global POWER9-family-powerpc64-cpu.compat=power9
qemu-system-ppc64: warning: CPU 'compat' property is deprecated and has no
effect; use max-cpu-compat machine property instead
This was merged during the QEMU 2.10 timeframe, a few weeks before we
formalized our deprecation process. As a consequence, the "compat"
property fell through the cracks and was never listed in the officialy
deprecated features.
We are now eight QEMU versions later, it is largely time to mention it
in qemu-deprecated.texi. Also, since -global XXX-powerpc64-cpu.compat=
has been emitting warnings since QEMU 2.10 and the usual way of setting
CPU properties is with -cpu, completely remove the "compat" property.
Keep the hack so that -cpu XXX,compat= stays functional some more time,
as required by our deprecation process.
The now empty powerpc_servercpu_properties[] list which was introduced
for "compat" and never had any other use is removed on the way. We can
re-add it in the future if the need for a server class POWER CPU specific
property arises again.
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <
158274357799.140275.
12263135811731647490.stgit@bahia.lan>
[dwg: Convert from .texi to .rst to match upstream change]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Greg Kurz [Mon, 24 Feb 2020 19:23:43 +0000 (20:23 +0100)]
spapr: Handle pending hot plug/unplug requests at CAS
If a hot plug or unplug request is pending at CAS, we currently trigger
a CAS reboot, which severely increases the guest boot time. This is
because SLOF doesn't handle hot plug events and we had no way to fix
the FDT that gets presented to the guest.
We can do better thanks to recent changes in QEMU and SLOF:
- we now return a full FDT to SLOF during CAS
- SLOF was fixed to correctly detect any device that was either added or
removed since boot time and to update its internal DT accordingly.
The right solution is to process all pending hot plug/unplug requests
during CAS: convert hot plugged devices to cold plugged devices and
remove the hot unplugged ones, which is exactly what spapr_drc_reset()
does. Also clear all hot plug events that are currently queued since
they're no longer relevant.
Note that SLOF cannot currently populate hot plugged PCI bridges or PHBs
at CAS. Until this limitation is lifted, SLOF will reset the machine when
this scenario occurs : this will allow the FDT to be fully processed when
SLOF is started again (ie. the same effect as the CAS reboot that would
occur anyway without this patch).
Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <
158257222352.
4102917.
8984214333937947307.stgit@bahia.lan>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Alexey Kardashevskiy [Fri, 21 Feb 2020 03:18:25 +0000 (14:18 +1100)]
pseries: Update SLOF firmware image
This adds vTPM support, full-FDT-rebuild-on-CAS fixes and
basic ext4 support.
The full changelog is:
Alexey Kardashevskiy (10):
disk-label: Prepare for extenting
disk-label: Support Linux GPT partition type
ext2: Prepare for extending
ext2: Rename group-desc-size
ext2: Read size of group descriptors
ext2: Read all 64bit of inode number
ext2/4: Add basic extent tree support
elf64: Add LE64 ABIv1/2 support for loading images to given address
fdt: Fix creating new nodes at H_CAS
version: update to
20200221
Greg Kurz (2):
fdt: Fix update of "interrupt-controller" node at CAS
fdt: Delete nodes of devices removed between boot and CAS
Stefan Berger (8):
slof: Implement SLOF_get_keystroke() and SLOF_reset()
slof: Make linker script variables accessible
qemu: Make print_version variable accessible
tpm: Add TPM CRQ driver implementation
tpm: Add sha256 implementation
tcgbios: Add TPM 2.0 support and firmware API
tcgbios: Implement menu to clear TPM 2 and activate its PCR banks
tcgbios: Measure the GPT table
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Peter Maydell [Mon, 16 Mar 2020 14:55:59 +0000 (14:55 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/vga-
20200316-pull-request' into staging
vga: stdvga/bochs mmio fix.
# gpg: Signature made Mon 16 Mar 2020 12:48:10 GMT
# gpg: using RSA key
4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/vga-
20200316-pull-request:
stdvga+bochs-display: add dummy mmio handler
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Mon, 16 Mar 2020 13:06:14 +0000 (13:06 +0000)]
Merge remote-tracking branch 'remotes/kraxel/tags/audio-
20200316-pull-request' into staging
audio: float fixes
# gpg: Signature made Mon 16 Mar 2020 11:30:00 GMT
# gpg: using RSA key
4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138
* remotes/kraxel/tags/audio-
20200316-pull-request:
audio: add audiodev format=f32 option documentation
audio: fix saturation nonlinearity in clip_* functions
audio: change mixing engine float range to [-1.f, 1.f]
audio: consistency changes
audio: change naming scheme of FLOAT_CONV macros
qapi/audio: add documentation for AudioFormat
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Gerd Hoffmann [Mon, 9 Mar 2020 10:00:09 +0000 (11:00 +0100)]
stdvga+bochs-display: add dummy mmio handler
The bochs-display mmio bar has some sub-regions with the actual hardware
registers. What happens when the guest access something outside those
regions depends on the archirecture. On x86 those reads succeed (and
return 0xff I think). On risc-v qemu aborts.
This patch adds handlers for the parent region, to make the wanted
behavior explicit and to make things consistent across architectures.
v2:
- use existing unassigned_io_ops.
- also cover stdvga.
Cc: Alistair Francis <alistair23@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-id:
20200309100009.17624-1-kraxel@redhat.com
Volker Rümelin [Sun, 8 Mar 2020 19:33:21 +0000 (20:33 +0100)]
audio: add audiodev format=f32 option documentation
The documentaion for -audiodev format=f32 option was missing.
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-id:
20200308193321.20668-6-vr_qemu@t-online.de
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Volker Rümelin [Sun, 8 Mar 2020 19:33:20 +0000 (20:33 +0100)]
audio: fix saturation nonlinearity in clip_* functions
The current positive limit for the saturation nonlinearity is
only correct if the type of the result has 8 bits or less.
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-id:
20200308193321.20668-5-vr_qemu@t-online.de
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Volker Rümelin [Sun, 8 Mar 2020 19:33:19 +0000 (20:33 +0100)]
audio: change mixing engine float range to [-1.f, 1.f]
Currently the internal float range of the mixing engine is
[-.5f, .5f]. PulseAudio, SDL2 and libasound use a [-1.f, 1.f]
range. This means with float samples the audio playback volume
is 6dB too low and audio recording signals will be clipped in
most cases.
To avoid another scaling factor in the conv_natural_float_* and
clip_natural_float_* functions with FLOAT_MIXENG defined this
patch changes the mixing engine float range to [-1.f, 1.f].
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-id:
20200308193321.20668-4-vr_qemu@t-online.de
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Volker Rümelin [Sun, 8 Mar 2020 19:33:18 +0000 (20:33 +0100)]
audio: consistency changes
Change the clip_natural_float_from_mono() function in
audio/mixeng.c to be consistent with the clip_*_from_mono()
functions in audio/mixeng_template.h.
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-id:
20200308193321.20668-3-vr_qemu@t-online.de
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Volker Rümelin [Sun, 8 Mar 2020 19:33:17 +0000 (20:33 +0100)]
audio: change naming scheme of FLOAT_CONV macros
This patch changes the naming scheme of the FLOAT_CONV_TO and
FLOAT_CONV_FROM macros to the scheme used in mixeng_template.h.
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-id:
20200308193321.20668-2-vr_qemu@t-online.de
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Volker Rümelin [Sun, 8 Mar 2020 19:33:16 +0000 (20:33 +0100)]
qapi/audio: add documentation for AudioFormat
The review for patch
ed2a4a7941 "audio: proper support for
float samples in mixeng" suggested this would be a good idea.
Acked-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Tested-by: John Arbuckle <programmingkidx@gmail.com>
Message-id:
20200308193321.20668-1-vr_qemu@t-online.de
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Peter Maydell [Fri, 13 Mar 2020 10:33:04 +0000 (10:33 +0000)]
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-
20200313a' into staging
Migration pull 2020-03-13
zstd build fix
A new auto-converge parameter
Some COLO improvements
# gpg: Signature made Fri 13 Mar 2020 10:29:34 GMT
# gpg: using RSA key
45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7
# gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full]
# Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7
* remotes/dgilbert/tags/pull-migration-
20200313a:
migration: recognize COLO as part of activating process
ram/colo: only record bitmap of dirty pages in COLO stage
COLO: Optimize memory back-up process
migration/throttle: Add throttle-trig-thres migration parameter
configure: Improve zstd test
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
zhanghailiang [Mon, 24 Feb 2020 06:54:12 +0000 (14:54 +0800)]
migration: recognize COLO as part of activating process
We will migrate parts of dirty pages backgroud lively during the gap time
of two checkpoints, without this modification, it will not work
because ram_save_iterate() will check it before send RAM_SAVE_FLAG_EOS
at the end of it.
Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Message-Id: <
20200224065414.36524-7-zhang.zhanghailiang@huawei.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
zhanghailiang [Mon, 24 Feb 2020 06:54:11 +0000 (14:54 +0800)]
ram/colo: only record bitmap of dirty pages in COLO stage
It is only need to record bitmap of dirty pages while goes
into COLO stage.
Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Message-Id: <
20200224065414.36524-6-zhang.zhanghailiang@huawei.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
zhanghailiang [Mon, 24 Feb 2020 06:54:10 +0000 (14:54 +0800)]
COLO: Optimize memory back-up process
This patch will reduce the downtime of VM for the initial process,
Previously, we copied all these memory in preparing stage of COLO
while we need to stop VM, which is a time-consuming process.
Here we optimize it by a trick, back-up every page while in migration
process while COLO is enabled, though it affects the speed of the
migration, but it obviously reduce the downtime of back-up all SVM'S
memory in COLO preparing stage.
Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com>
Message-Id: <
20200224065414.36524-5-zhang.zhanghailiang@huawei.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
minor typo fixes
Keqian Zhu [Mon, 24 Feb 2020 02:31:42 +0000 (10:31 +0800)]
migration/throttle: Add throttle-trig-thres migration parameter
Currently, if the bytes_dirty_period is more than the 50% of
bytes_xfer_period, we start or increase throttling.
If we make this percentage higher, then we can tolerate higher
dirty rate during migration, which means less impact on guest.
The side effect of higher percentage is longer migration time.
We can make this parameter configurable to switch between mig-
ration time first or guest performance first.
The default value is 50 and valid range is 1 to 100.
Signed-off-by: Keqian Zhu <zhukeqian1@huawei.com>
Message-Id: <
20200224023142.39360-1-zhukeqian1@huawei.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Juan Quintela [Tue, 10 Mar 2020 11:14:31 +0000 (12:14 +0100)]
configure: Improve zstd test
There were one error on the test (missing an s for --exists).
But we really need a recent zstd (1.4.0).
Thanks to Michal Privoznik to provide the right vension.
Signed-off-by: Juan Quintela <quintela@redhat.com>
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <
20200310111431.173151-1-quintela@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Peter Maydell [Thu, 12 Mar 2020 17:34:34 +0000 (17:34 +0000)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-
20200312' into staging
target-arm queue:
* Fix various bugs that might result in an assert() due to
incorrect hflags for M-profile CPUs
* Fix Aspeed SMC Controller user-mode select handling
* Report correct (with-tag) address in fault address register
when TBI is enabled
* cubieboard: make sure SOC object isn't leaked
* fsl-imx25: Wire up eSDHC controllers
* fsl-imx25: Wire up USB controllers
* New board model: orangepi-pc (OrangePi PC)
* ARM/KVM: if user doesn't select GIC version and the
host kernel can only provide GICv3, use that, rather
than defaulting to "fail because GICv2 isn't possible"
* kvm: Only do KVM_SET_VCPU_EVENTS at the last stage of sync
# gpg: Signature made Thu 12 Mar 2020 16:43:46 GMT
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-
20200312: (36 commits)
target/arm: kvm: Inject events at the last stage of sync
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
hw/arm/virt: kvm: Restructure finalize_gic_version()
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
hw/arm/virt: Introduce finalize_gic_version()
hw/arm/virt: Introduce VirtGICType enum type
hw/arm/virt: Document 'max' value in gic-version property description
docs: add Orange Pi PC document
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
tests/boot_linux_console: Add a quick test for the OrangePi PC board
hw/arm/allwinner: add RTC device support
hw/arm/allwinner-h3: add SDRAM controller device
hw/arm/allwinner-h3: add Boot ROM support
hw/arm/allwinner-h3: add EMAC ethernet device
hw/arm/allwinner: add SD/MMC host controller
hw/arm/allwinner: add Security Identifier device
hw/arm/allwinner: add CPU Configuration module
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 12 Mar 2020 16:51:26 +0000 (16:51 +0000)]
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Block layer patches:
- Relax restrictions for blockdev-snapshot (allows libvirt to do live
storage migration with blockdev-mirror)
- luks: Delete created files when block_crypto_co_create_opts_luks fails
- Fix memleaks in qmp_object_add
# gpg: Signature made Wed 11 Mar 2020 15:38:59 GMT
# gpg: using RSA key
7F09B272C88F2FD6
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full]
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6
* remotes/kevin/tags/for-upstream:
qemu-iotests: adding LUKS cleanup for non-UTF8 secret error
crypto.c: cleanup created file when block_crypto_co_create_opts_luks fails
block.c: adding bdrv_co_delete_file
block: introducing 'bdrv_co_delete_file' interface
tests/qemu-iotests: Fix socket_scm_helper build path
qapi: Add '@allow-write-only-overlay' feature for 'blockdev-snapshot'
iotests: Add iothread cases to 155
block: Fix cross-AioContext blockdev-snapshot
iotests: Test mirror with temporarily disabled target backing file
iotests: Fix run_job() with use_log=False
block: Relax restrictions for blockdev-snapshot
block: Make bdrv_get_cumulative_perm() public
qom-qmp-cmds: fix two memleaks in qmp_object_add
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Beata Michalska [Thu, 12 Mar 2020 00:34:00 +0000 (00:34 +0000)]
target/arm: kvm: Inject events at the last stage of sync
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
As such this should be the last step of sync to avoid potential overwriting
of whatever changes KVM might have done.
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id:
20200312003401.29017-2-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Wed, 11 Mar 2020 13:16:18 +0000 (14:16 +0100)]
hw/arm/virt: kvm: allow gicv3 by default if v2 cannot work
At the moment if the end-user does not specify the gic-version along
with KVM acceleration, v2 is set by default. However most of the
systems now have GICv3 and sometimes they do not support GICv2
compatibility.
This patch keeps the default v2 selection in all cases except
in the KVM accelerated mode when either
- the host does not support GICv2 in-kernel emulation or
- number of VCPUS exceeds 8.
Those cases did not work anyway so we do not break any compatibility.
Now we get v3 selected in such a case.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id:
20200311131618.7187-7-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Wed, 11 Mar 2020 13:16:17 +0000 (14:16 +0100)]
hw/arm/virt: kvm: Restructure finalize_gic_version()
Restructure the finalize_gic_version with switch cases and
clearly separate the following cases:
- KVM mode / in-kernel irqchip
- KVM mode / userspace irqchip
- TCG mode
In KVM mode / in-kernel irqchip , we explictly check whether
the chosen version is supported by the host. If the end-user
explicitly sets v2/v3 and this is not supported by the host,
then the user gets an explicit error message. Note that for
old kernels where the CREATE_DEVICE ioctl doesn't exist then
we will now fail if the user specifically asked for gicv2,
where previously we (probably) would have succeeded.
In KVM mode / userspace irqchip we immediatly output an error
in case the end-user explicitly selected v3. Also we warn the
end-user about the unexpected usage of gic-version=host in
that case as only userspace GICv2 is supported.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id:
20200311131618.7187-6-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Wed, 11 Mar 2020 13:16:16 +0000 (14:16 +0100)]
target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
Convert kvm_arm_vgic_probe() so that it returns a
bitmap of supported in-kernel emulation VGIC versions instead
of the max version: at the moment values can be v2 and v3.
This allows to expose the case where the host GICv3 also
supports GICv2 emulation. This will be useful to choose the
default version in KVM accelerated mode.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200311131618.7187-5-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Wed, 11 Mar 2020 13:16:15 +0000 (14:16 +0100)]
hw/arm/virt: Introduce finalize_gic_version()
Let's move the code which freezes which gic-version to
be applied in a dedicated function. We also now set by
default the VIRT_GIC_VERSION_NO_SET. This eventually
turns into the legacy v2 choice in the finalize() function.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id:
20200311131618.7187-4-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Wed, 11 Mar 2020 13:16:14 +0000 (14:16 +0100)]
hw/arm/virt: Introduce VirtGICType enum type
We plan to introduce yet another value for the gic version (nosel).
As we already use exotic values such as 0 and -1, let's introduce
a dedicated enum type and let vms->gic_version take this
type.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id:
20200311131618.7187-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Eric Auger [Wed, 11 Mar 2020 13:16:13 +0000 (14:16 +0100)]
hw/arm/virt: Document 'max' value in gic-version property description
Mention 'max' value in the gic-version property description.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id:
20200311131618.7187-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:54 +0000 (23:18 +0100)]
docs: add Orange Pi PC document
The Xunlong Orange Pi PC machine is a functional ARM machine
based on the Allwinner H3 System-on-Chip. It supports mainline
Linux, U-Boot, NetBSD and is covered by acceptance tests.
This commit adds a documentation text file with a description
of the machine and instructions for the user.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-19-nieklinnenbank@gmail.com
[PMM: moved file into docs/system/arm to match the reorg
of the arm target part of the docs; tweaked heading to
match other boards]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 11 Mar 2020 22:18:53 +0000 (23:18 +0100)]
tests/boot_linux_console: Test booting NetBSD via U-Boot on OrangePi PC
This test boots U-Boot then NetBSD (stored on a SD card) on
a OrangePi PC board.
As it requires ~1.3GB of storage, it is disabled by default.
U-Boot is built by the Debian project [1], and the SD card image
is provided by the NetBSD organization [2].
Once the compressed SD card image is downloaded (304MB) and
extracted, this test is fast:
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
avocado --show=app,console run -t machine:orangepi-pc \
tests/acceptance/boot_linux_console.py
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
console: DRAM: 1024 MiB
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner Technology
console: CPU: Allwinner H3 (SUN8I 0000)
console: scanning bus usb@
1c1b000 for devices... 1 USB Device(s) found
console: scanning bus usb@
1c1d000 for devices... 1 USB Device(s) found
console: scanning usb for storage devices... 0 Storage Device(s) found
console: Hit any key to stop autoboot: 0
console: => setenv bootargs root=ld0a
console: => setenv kernel netbsd-GENERIC.ub
console: => setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
console: => boot
console: ## Booting kernel from Legacy Image at
42000000 ...
console: Image Name: NetBSD/earmv7hf 9.0_RC1
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompressed)
console: XIP Kernel Image (no loading done)
console: Loading Device Tree to
49ff6000, end
49fffe01 ... OK
console: Starting kernel ...
console: [ 1.
0000000] NetBSD/evbarm (fdt) booting ...
console: [ 1.
0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC 2020
console: [ 1.
0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/arch/evbarm/compile/GENERIC
console: [ 1.
0000000] total memory = 1024 MB
console: [ 1.
0000000] avail memory = 1003 MB
console: [ 1.
0000000] armfdt0 (root)
console: [ 1.
0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
console: [ 1.
0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
console: [ 1.
0000000] cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
console: [ 1.
0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
console: [ 1.
0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT Data cache
console: [ 1.
0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Unified cache
console: [ 1.
0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
...
console: [ 2.
3812082] sdmmc0: SD card status: 4-bit, C0
console: [ 2.
3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef:0x062>
console: [ 2.
4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes/sect x
2511872 sectors
console: [ 2.
5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
console: [ 3.
1068718] WARNING: 4 errors while detecting hardware; check system log.
console: [ 3.
1179868] boot device: ld0
console: [ 3.
1470623] root on ld0a dumps on ld0b
console: [ 3.
2464436] root file system type: ffs
console: [ 3.
2897123] kern.module.path=/stand/evbarm/9.0/modules
console: Mon Feb 17 20:33:35 UTC 2020
console: Starting root file system check:
PASS (35.96 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0
JOB TIME : 36.09 s
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
This test is based on a description from Niek Linnenbank from [4].
[1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootable_SD_Card_with_u-boot
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
[3] https://travis-ci.org/philmd/qemu/jobs/
638823612#L3778
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-18-nieklinnenbank@gmail.com
[NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc.base-year]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 11 Mar 2020 22:18:52 +0000 (23:18 +0100)]
tests/boot_linux_console: Add a SLOW test booting Ubuntu on OrangePi PC
This test boots Ubuntu Bionic on a OrangePi PC board.
As it requires 1GB of storage, and is slow, this test is disabled
on automatic CI testing.
It is useful for workstation testing. Currently Avocado timeouts too
quickly, so we can't run userland commands.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The Ubuntu image is downloaded from:
https://dl.armbian.com/orangepipc/Bionic_current
This test can be run using:
$ AVOCADO_ALLOW_LARGE_STORAGE=yes \
avocado --show=app,console run -t machine:orangepi-pc \
tests/acceptance/boot_linux_console.py
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
console: DRAM: 1024 MiB
console: Failed to set core voltage! Can't set CPU frequency
console: Trying to boot from MMC1
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner Technology
console: CPU: Allwinner H3 (SUN8I 0000)
console: Model: Xunlong Orange Pi PC
console: DRAM: 1 GiB
console: MMC: mmc@
1c0f000: 0
[...]
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.11.3 SMP Mon Nov 18 18:49:43 CET 2019
console: CPU: ARMv7 Processor [
410fc075] revision 5 (ARMv7), cr=
50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
[...]
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null)
console: done.
console: Begin: Running /scripts/local-bottom ... done.
console: Begin: Running /scripts/init-bottom ... done.
console: systemd[1]: systemd 237 running in system mode. (...)
console: systemd[1]: Detected architecture arm.
console: Welcome to Ubuntu 18.04.3 LTS!
console: systemd[1]: Set hostname to <orangepipc>.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-17-nieklinnenbank@gmail.com
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
[NL: changed test to boot from SD card via BootROM, added check for 7z]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 11 Mar 2020 22:18:51 +0000 (23:18 +0100)]
tests/boot_linux_console: Add a SD card test for the OrangePi PC board
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The SD image is from the kernelci.org project:
https://kernelci.org/faq/#the-code
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [
410fc075] revision 5 (ARMv7), cr=
50c5387d
[...]
console: sunxi-wdt
1c20ca0.watchdog: Watchdog enabled (timeout=16 sec, nowayout=0)
console: sunxi-mmc
1c0f000.mmc: Linked as a consumer to regulator.2
console: sunxi-mmc
1c0f000.mmc: Got CD GPIO
console: ledtrig-cpu: registered to indicate activity on CPUs
console: hidraw: raw HID events driver (C) Jiri Kosina
console: usbcore: registered new interface driver usbhid
console: usbhid: USB HID core driver
console: Initializing XFRM netlink socket
console: sunxi-mmc
1c0f000.mmc: initialized, max. request size: 16384 KB
console: NET: Registered protocol family 10
console: mmc0: host does not support reading read-only switch, assuming write-enable
console: mmc0: Problem switching card into high-speed mode!
console: mmc0: new SD card at address 4567
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
[...]
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subsystem
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (null)
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
console: Run /sbin/init as init process
console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user_xattr,acl
console: Starting syslogd: OK
console: Starting klogd: OK
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
console: /bin/sh: can't access tty; job control turned off
console: cat /proc/partitions
console: / # cat /proc/partitions
console: major minor #blocks name
console: 1 0 4096 ram0
console: 1 1 4096 ram1
console: 1 2 4096 ram2
console: 1 3 4096 ram3
console: 179 0 61440 mmcblk0
console: reboot
console: / # reboot
console: umount: devtmpfs busy - remounted read-only
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
console: The system is going down NOW!
console: Sent SIGTERM to all processes
console: Sent SIGKILL to all processes
console: Requesting system reboot
console: reboot: Restarting system
JOB TIME : 68.64 s
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-16-nieklinnenbank@gmail.com
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
[NL: extend test with ethernet device checks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 11 Mar 2020 22:18:50 +0000 (23:18 +0100)]
tests/boot_linux_console: Add initrd test for the Orange Pi PC board
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=console run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [
410fc075] revision 5 (ARMv7), cr=
50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
[...]
console: Trying to unpack rootfs image as initramfs...
console: Freeing initrd memory: 3256K
console: Freeing unused kernel memory: 1024K
console: Run /init as init process
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
console: Starting logging: OK
console: Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read)
console: done.
console: Starting network: OK
console: Found console ttyS0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: Boot successful.
console: cat /proc/cpuinfo
console: / # cat /proc/cpuinfo
console: processor : 0
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
[...]
console: processor : 3
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
console: Hardware : Allwinner sun8i Family
console: Revision : 0000
console: Serial :
0000000000000000
console: cat /proc/iomem
console: / # cat /proc/iomem
console:
01000000-
010fffff : clock@
1000000
console:
01c00000-
01c00fff : system-control@
1c00000
console:
01c02000-
01c02fff : dma-controller@
1c02000
[...]
console: reboot
console: / # reboot
console: / # Found console ttyS0
console: Stopping network: OK
console: hrtimer: interrupt took
21852064 ns
console: Saving random seed... random: dd: uninitialized urandom read (512 bytes read)
console: done.
console: Stopping logging: OK
console: umount: devtmpfs busy - remounted read-only
console: umount: can't unmount /: Invalid argument
console: The system is going down NOW!
console: Sent SIGTERM to all processes
console: Sent SIGKILL to all processes
console: Requesting system reboot
console: reboot: Restarting system
PASS (48.32 s)
JOB TIME : 49.16 s
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-15-nieklinnenbank@gmail.com
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Philippe Mathieu-Daudé [Wed, 11 Mar 2020 22:18:49 +0000 (23:18 +0100)]
tests/boot_linux_console: Add a quick test for the OrangePi PC board
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ make check-venv
$ ./tests/venv/bin/avocado --show=console,app run -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
JOB ID :
2e4d15eceb13c33672af406f08171e6e9de1414a
JOB LOG : ~/job-results/job-2019-12-17T05.46-
2e4d15e/job.log
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_orangepi:
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [
410fc075] revision 5 (ARMv7), cr=
50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
console: Memory policy: Data cache writealloc
console: OF: reserved mem: failed to allocate memory for node 'cma@
4a000000'
console: cma: Failed to reserve 128 MiB
console: psci: probing for conduit method from DT.
console: psci: PSCIv0.2 detected in firmware.
console: psci: Using standard PSCI v0.2 function IDs
console: psci: Trusted OS migration not required
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 with crng_init=0
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u73728
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
console: Kernel command line: printk.time=0 console=ttyS0,115200
PASS (8.59 s)
JOB TIME : 8.81 s
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-14-nieklinnenbank@gmail.com
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:48 +0000 (23:18 +0100)]
hw/arm/allwinner: add RTC device support
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
for non-volatile system date and time keeping. This commit adds a generic
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
The following RTC functionality and features are implemented:
* Year-Month-Day read/write
* Hour-Minute-Second read/write
* General Purpose storage
The following boards are extended with the RTC device:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-13-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:47 +0000 (23:18 +0100)]
hw/arm/allwinner-h3: add SDRAM controller device
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
adds emulation support of the Allwinner H3 SDRAM controller.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-12-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:46 +0000 (23:18 +0100)]
hw/arm/allwinner-h3: add Boot ROM support
A real Allwinner H3 SoC contains a Boot ROM which is the
first code that runs right after the SoC is powered on.
The Boot ROM is responsible for loading user code (e.g. a bootloader)
from any of the supported external devices and writing the downloaded
code to internal SRAM. After loading the SoC begins executing the code
written to SRAM.
This commits adds emulation of the Boot ROM firmware setup functionality
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
sizes larger than 32KiB. For reference, this behaviour is documented
by the Linux Sunxi project wiki at:
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-11-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:45 +0000 (23:18 +0100)]
hw/arm/allwinner-h3: add EMAC ethernet device
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
which provides 10M/100M/1000M Ethernet connectivity. This commit
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, etc),
including emulation for the following functionality:
* DMA transfers
* MII interface
* Transmit CRC calculation
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-10-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:44 +0000 (23:18 +0100)]
hw/arm/allwinner: add SD/MMC host controller
The Allwinner System on Chip families sun4i and above contain
an integrated storage controller for Secure Digital (SD) and
Multi Media Card (MMC) interfaces. This commit adds support
for the Allwinner SD/MMC storage controller with the following
emulated features:
* DMA transfers
* Direct FIFO I/O
* Short/Long format command responses
* Auto-Stop command (CMD12)
* Insert & remove card detection
The following boards are extended with the SD host controller:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20200311221854.30370-9-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:43 +0000 (23:18 +0100)]
hw/arm/allwinner: add Security Identifier device
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using a 128-bit
UUID value as input.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-8-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:42 +0000 (23:18 +0100)]
hw/arm/allwinner: add CPU Configuration module
Various Allwinner System on Chip designs contain multiple processors
that can be configured and reset using the generic CPU Configuration
module interface. This commit adds support for the Allwinner CPU
configuration interface which emulates the following features:
* CPU reset
* CPU status
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id:
20200311221854.30370-7-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:41 +0000 (23:18 +0100)]
hw/arm/allwinner-h3: add System Control module
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20200311221854.30370-6-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:40 +0000 (23:18 +0100)]
hw/arm/allwinner-h3: add USB host controller
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20200311221854.30370-5-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:39 +0000 (23:18 +0100)]
hw/arm/allwinner-h3: add Clock Control Unit
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20200311221854.30370-4-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:38 +0000 (23:18 +0100)]
hw/arm: add Xunlong Orange Pi PC machine
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
based embedded computer with mainline support in both U-Boot
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
various other I/O. This commit add support for the Xunlong
Orange Pi PC machine.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id:
20200311221854.30370-3-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Niek Linnenbank [Wed, 11 Mar 2020 22:18:37 +0000 (23:18 +0100)]
hw/arm: add Allwinner H3 System-on-Chip
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
processor cores. Features and specifications include DDR2/DDR3 memory,
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
various I/O modules. This commit adds support for the Allwinner H3
System on Chip.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20200311221854.30370-2-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Guenter Roeck [Tue, 10 Mar 2020 21:51:46 +0000 (14:51 -0700)]
hw/arm/fsl-imx25: Wire up USB controllers
i.MX25 supports two USB controllers. Let's wire them up.
With this patch, imx25-pdk can boot from both USB ports.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id:
20200310215146.19688-3-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Guenter Roeck [Tue, 10 Mar 2020 21:51:45 +0000 (14:51 -0700)]
hw/arm/fsl-imx25: Wire up eSDHC controllers
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives
provided on the command line to available eSDHC controllers.
This patch enables booting the imx25-pdk emulation from SD card.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id:
20200310215146.19688-2-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: made commit subject consistent with other patch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Igor Mammedov [Tue, 3 Mar 2020 09:12:54 +0000 (04:12 -0500)]
hw/arm/cubieboard: make sure SOC object isn't leaked
SOC object returned by object_new() is leaked in current code.
Set SOC parent explicitly to board and then unref to SOC object
to make sure that refererence returned by object_new() is taken
care of.
The SOC object will be kept alive by its parent (machine) and
will be automatically freed when MachineState is destroyed.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reported-by: Andrew Jones <drjones@redhat.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id:
20200303091254.22373-1-imammedo@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sun, 8 Mar 2020 01:29:46 +0000 (17:29 -0800)]
target/arm: Disable clean_data_tbi for system mode
We must include the tag in the FAR_ELx register when raising
an addressing exception. Which means that we should not clear
out the tag during translation.
We cannot at present comply with this for user mode, so we
retain the clean_data_tbi function for the moment, though it
no longer does what it says on the tin for system mode. This
function is to be replaced with MTE, so don't worry about the
slight misnaming.
Buglink: https://bugs.launchpad.net/qemu/+bug/1867072
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200308012946.16303-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sun, 8 Mar 2020 01:29:45 +0000 (17:29 -0800)]
target/arm: Check addresses for disabled regimes
We fail to validate the upper bits of a virtual address on a
translation disabled regime, as per AArch64.TranslateAddressS1Off.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200308012946.16303-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Cédric Le Goater [Thu, 6 Feb 2020 11:26:45 +0000 (12:26 +0100)]
aspeed/smc: Fix User mode select/unselect scheme
The Aspeed SMC Controller can operate in different modes : Read, Fast
Read, Write and User modes. When the User mode is configured, it
selects automatically the SPI slave device until the CE_STOP_ACTIVE
bit is set to 1. When any other modes are configured the device is
unselected. The HW logic handles the chip select automatically when
the flash is accessed through its AHB window.
When configuring the CEx Control Register, the User mode logic to
select and unselect the slave is incorrect and data corruption can be
seen on machines using two chips, witherspoon and romulus.
Rework the handler setting the CEx Control Register to fix this issue.
Fixes:
7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id:
20200206112645.21275-3-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Cédric Le Goater [Thu, 6 Feb 2020 11:26:44 +0000 (12:26 +0100)]
aspeed/smc: Add some tracing
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id:
20200206112645.21275-2-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 3 Mar 2020 17:49:50 +0000 (17:49 +0000)]
target/arm: Fix some comment typos
Fix a couple of comment typos.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200303174950.3298-5-peter.maydell@linaro.org
Peter Maydell [Tue, 3 Mar 2020 17:49:49 +0000 (17:49 +0000)]
target/arm: Recalculate hflags correctly after writes to CONTROL
A write to the CONTROL register can change our current EL (by
writing to the nPRIV bit). That means that we can't assume
that s->current_el is still valid in trans_MSR_v7m() when
we try to rebuild the hflags.
Add a new helper rebuild_hflags_m32_newel() which, like the
existing rebuild_hflags_a32_newel(), recalculates the current
EL from scratch, and use it in trans_MSR_v7m().
This fixes an assertion about an hflags mismatch when the
guest changes privilege by writing to CONTROL.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200303174950.3298-4-peter.maydell@linaro.org
Peter Maydell [Tue, 3 Mar 2020 17:49:48 +0000 (17:49 +0000)]
target/arm: Update hflags in trans_CPS_v7m()
For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
(it changes the NegPri bit). We update the hflags after calls
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
in trans_CPS_v7m().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200303174950.3298-3-peter.maydell@linaro.org
Peter Maydell [Tue, 3 Mar 2020 17:49:47 +0000 (17:49 +0000)]
hw/intc/armv7m_nvic: Rebuild hflags on reset
Some of an M-profile CPU's cached hflags state depends on state that's
in our NVIC object. We already do an hflags rebuild when the NVIC
registers are written, but we also need to do this on NVIC reset,
because there's no guarantee that this will happen before the
CPU reset.
This fixes an assertion due to mismatched hflags which happens if
the CPU is reset from inside a HardFault handler.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200303174950.3298-2-peter.maydell@linaro.org
Peter Maydell [Thu, 12 Mar 2020 16:00:31 +0000 (16:00 +0000)]
Merge remote-tracking branch 'remotes/vivier/tags/q800-for-5.0-pull-request' into staging
Fix Coverity CID
1412799 (Error handling issues)
# gpg: Signature made Thu 12 Mar 2020 15:15:01 GMT
# gpg: using RSA key
CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg: issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C
* remotes/vivier/tags/q800-for-5.0-pull-request:
q800: fix coverity warning CID
1412799
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Thu, 12 Mar 2020 15:20:52 +0000 (15:20 +0000)]
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-docs-
20200312' into staging
docs queue:
* Remove some no longer needed texinfo infrastructure
* Reorder the top level index docs to put most useful manuals first
* Split the Arm target-specific info into sub-pages
* Improve the Arm documentation a bit with info previously
only on the wiki page
# gpg: Signature made Thu 12 Mar 2020 11:42:10 GMT
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-docs-
20200312:
docs: Be consistent about capitalization of 'Arm'
docs: Move arm-cpu-features.rst into the system manual
docs/system/target-arm.rst: Add some introductory text
docs/system: Split target-arm.rst into sub-documents
Makefile: Allow for subdirectories in Sphinx manual dependencies
docs/qemu-option-trace.rst.inc: Remove redundant comment
docs/index.rst, docs/index.html.in: Reorder manuals
Makefile: Make all Sphinx documentation depend on the extensions
docs/sphinx/hxtool.py: Remove STEXI/ETEXI support
hxtool: Remove Texinfo generation support
Update comments in .hx files that mention Texinfo
Makefile: Remove redundant Texinfo related code
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Laurent Vivier [Mon, 10 Feb 2020 13:22:52 +0000 (14:22 +0100)]
q800: fix coverity warning CID
1412799
Check the return value of blk_write() and log an error if any
Fixes: Coverity CID
1412799 (Error handling issues)
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20200210132252.381343-1-laurent@vivier.eu>
Peter Maydell [Thu, 12 Mar 2020 14:47:42 +0000 (14:47 +0000)]
Merge remote-tracking branch 'remotes/gkurz/tags/9p-next-2020-03-10' into staging
Fix the proxy fsdev so that it honours "readonly" and "writeout".
# gpg: Signature made Tue 10 Mar 2020 15:16:39 GMT
# gpg: using RSA key
B4828BAF943140CEF2A3491071D4D5E5822F73D6
# gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full]
# gpg: aka "Gregory Kurz <gregory.kurz@free.fr>" [full]
# gpg: aka "[jpeg image of size 3330]" [full]
# Primary key fingerprint: B482 8BAF 9431 40CE F2A3 4910 71D4 D5E5 822F 73D6
* remotes/gkurz/tags/9p-next-2020-03-10:
9p/proxy: Fix export_flags
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Peter Maydell [Tue, 10 Mar 2020 15:21:41 +0000 (15:21 +0000)]
tests: Disable dbus-vmstate-test
The dbus-vmstate-test has been failing in some Patchew configs
since about the 6th March:
dbus-daemon[9321]: Could not get password database information for UID of current process: User "???" unknown or no memory to allocate password entry
**
ERROR:/tmp/qemu-test/src/tests/qtest/dbus-vmstate-test.c:114:get_connection: assertion failed (err == NULL): The connection is closed (g-io-error-quark, 18)
cleaning up pid 9321
ERROR - Bail out! ERROR:/tmp/qemu-test/src/tests/qtest/dbus-vmstate-test.c:114:get_connection: assertion failed (err == NULL): The connection is closed (g-io-error-quark, 18)
make: *** [/tmp/qemu-test/src/tests/Makefile.include:632: check-qtest-x86_64] Error 1
make: *** Waiting for unfinished jobs....
It's not clear why this is happening (perhaps a recently revealed
race condition or a change in the patchew build environment?).
For the moment, disable this test so that patchew test runs are
useful and don't email the list with spurious failure mails.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20200310152141.13959-1-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Mar 2020 21:58:18 +0000 (21:58 +0000)]
docs: Be consistent about capitalization of 'Arm'
The company 'Arm' went through a rebranding some years back
involving a recapitalization from 'ARM' to 'Arm'. As a result
our documentation is a bit inconsistent between the two forms.
It's not worth trying to update everywhere in QEMU, but it's
easy enough to make docs/ consistent.
Note that "ARMv8" and similar architecture names, and
older CPU names like "ARM926" still retain all-caps.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id:
20200309215818.2021-6-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Mar 2020 21:58:17 +0000 (21:58 +0000)]
docs: Move arm-cpu-features.rst into the system manual
Now we have somewhere to put arm-specific rst documentation,
we can move arm-cpu-features.rst from the docs/ top level
directory into docs/system/arm/.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id:
20200309215818.2021-5-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Mar 2020 21:58:16 +0000 (21:58 +0000)]
docs/system/target-arm.rst: Add some introductory text
Now we've moved the various bits of per-board documentation into
their own files, the top level document is a little bare. Add
some introductory information, including a note that many
of the board models we support are currently undocumented.
(Most sections of this new text were originally written by me
for the wiki page https://wiki.qemu.org/Documentation/Platforms/ARM)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id:
20200309215818.2021-4-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Mar 2020 21:58:15 +0000 (21:58 +0000)]
docs/system: Split target-arm.rst into sub-documents
Currently the documentation for Arm system emulator targets is in a
single target-arm.rst. This describes only some of the boards and
often in a fairly abbreviated fashion. Restructure it so that each
board has its own documentation file in the docs/system/arm/
subdirectory.
This will hopefully encourage us to write board documentation that
describes the board in detail, rather than a few brief paragraphs
in a single long page. The table of contents should also help users
to find the board they care about faster.
Once the structure is in place we'll be able to move microvm.rst
from the top-level docs/ directory.
All the text from the old page is retained, except for the final
paragraph ("A Linux 2.6 test image is available on the QEMU web site.
More information is available in the QEMU mailing-list archive."),
which is deleted. The git history shows this was originally added
in reference to the integratorcp board (at that time the only
Arm board that was supported), and has subsequently gradually been
further and further separated from the integratorcp documentation
by the insertion of other board documentation sections. It's
extremely out of date and no longer accurate, since AFAICT there
isn't an integratorcp kernel on the website any more; so better
deleted than retained.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id:
20200309215818.2021-3-peter.maydell@linaro.org
Peter Maydell [Mon, 9 Mar 2020 21:58:14 +0000 (21:58 +0000)]
Makefile: Allow for subdirectories in Sphinx manual dependencies
Currently we put 'docs/foo/*.rst' in the Make list of dependencies
for the Sphinx 'foo' manual, which means all the files must be
in the top level of that manual's directory. We'd like to be
able to have subdirectories inside some of the manuals, so add
'docs/foo/*/*.rst' to the dependencies too.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200309215818.2021-2-peter.maydell@linaro.org
Peter Maydell [Fri, 6 Mar 2020 17:17:49 +0000 (17:17 +0000)]
docs/qemu-option-trace.rst.inc: Remove redundant comment
The Texinfo version of the tracing options documentation has now
been deleted, so we can remove the now-redundant comment at the top
of the rST version that was reminding us that the two should be
kept in sync.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200306171749.10756-8-peter.maydell@linaro.org
Peter Maydell [Fri, 6 Mar 2020 17:17:48 +0000 (17:17 +0000)]
docs/index.rst, docs/index.html.in: Reorder manuals
Now that qemu-doc.html is no longer present, the ordering of manuals
within the top-level index page looks a bit odd. Reshuffle so that
the manuals the user is most likely to be interested in are at the
top of the list, and the reference material is at the bottom.
Similarly, we reorder the index.rst file used as the base of
the "all manuals in one" documentation for readthedocs.
The new order is:
* system
* user
* tools
* interop
* specs
* QMP reference (if present)
* Guest agent protocol reference (if present)
* devel (if present)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200306171749.10756-7-peter.maydell@linaro.org
Peter Maydell [Fri, 6 Mar 2020 17:17:47 +0000 (17:17 +0000)]
Makefile: Make all Sphinx documentation depend on the extensions
Add the Python source files of our Sphinx extensions to the
dependencies of the Sphinx manuals, so that if we edit the
extension source code the manuals get rebuilt.
Adding this dependency unconditionally means that we'll rebuild
a manual even if it happens to not use the extension whose
source file was changed, but this is simpler and less error
prone, and it's unlikely that we'll be making frequent changes
to the extensions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200306171749.10756-6-peter.maydell@linaro.org
Peter Maydell [Fri, 6 Mar 2020 17:17:46 +0000 (17:17 +0000)]
docs/sphinx/hxtool.py: Remove STEXI/ETEXI support
Now that none of our input .hx files have STEXI/ETEXI blocks,
we can remove the code in the Sphinx hxtool extension that
supported parsing them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200306171749.10756-5-peter.maydell@linaro.org
Peter Maydell [Fri, 6 Mar 2020 17:17:45 +0000 (17:17 +0000)]
hxtool: Remove Texinfo generation support
All the STEXI/ETEXI blocks and the Makfile rules that use them have now
been removed from the codebase. We can remove the code from the hxtool
script which handles the STEXI/ETEXI directives and the '-t' option.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200306171749.10756-4-peter.maydell@linaro.org
Peter Maydell [Fri, 6 Mar 2020 17:17:44 +0000 (17:17 +0000)]
Update comments in .hx files that mention Texinfo
Update the header comments in .hx files that mention STEXI/ETEXI
markup; this is now SRST/ERST as all these files have been
converted to rST.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200306171749.10756-3-peter.maydell@linaro.org
Peter Maydell [Fri, 6 Mar 2020 17:17:43 +0000 (17:17 +0000)]
Makefile: Remove redundant Texinfo related code
The recent conversion of qemu-doc.texi to rST forgot a few stray bits
of makefile code that are now redundant. Remove them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20200306171749.10756-2-peter.maydell@linaro.org
Peter Maydell [Wed, 11 Mar 2020 17:06:40 +0000 (17:06 +0000)]
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-03-11' into staging
Block patches for the 5.0 softfreeze:
- qemu-img measure for LUKS
- Improve block-copy's performance by reducing inter-request
dependencies
- Make curl's detection of accept-ranges more robust
- Memleak fixes
- iotest fix
# gpg: Signature made Wed 11 Mar 2020 13:19:01 GMT
# gpg: using RSA key
91BEB60A30DB3E8857D11829F407DB0061D5CF40
# gpg: issuer "mreitz@redhat.com"
# gpg: Good signature from "Max Reitz <mreitz@redhat.com>" [full]
# Primary key fingerprint: 91BE B60A 30DB 3E88 57D1 1829 F407 DB00 61D5 CF40
* remotes/maxreitz/tags/pull-block-2020-03-11:
block/block-copy: hide structure definitions
block/block-copy: reduce intersecting request lock
block/block-copy: rename start to offset in interfaces
block/block-copy: refactor interfaces to use bytes instead of end
block/block-copy: factor out find_conflicting_inflight_req
block/block-copy: use block_status
block/block-copy: specialcase first copy_range request
block/block-copy: fix progress calculation
job: refactor progress to separate object
block/qcow2-threads: fix qcow2_decompress
qemu-img: free memory before re-assign
block/qcow2: do free crypto_opts in qcow2_close()
iotests: Fix nonportable use of od --endian
block/curl: HTTP header field names are case insensitive
block/curl: HTTP header fields allow whitespace around values
iotests: add 288 luks qemu-img measure test
qemu-img: allow qemu-img measure --object without a filename
luks: implement .bdrv_measure()
luks: extract qcrypto_block_calculate_payload_offset()
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Daniel Henrique Barboza [Thu, 30 Jan 2020 21:39:07 +0000 (18:39 -0300)]
qemu-iotests: adding LUKS cleanup for non-UTF8 secret error
This patch adds a new test file to exercise the case where
qemu-img fails to complete for the LUKS format when a non-UTF8
secret is used.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20200130213907.
2830642-5-danielhb413@gmail.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Daniel Henrique Barboza [Thu, 30 Jan 2020 21:39:06 +0000 (18:39 -0300)]
crypto.c: cleanup created file when block_crypto_co_create_opts_luks fails
When using a non-UTF8 secret to create a volume using qemu-img, the
following error happens:
$ qemu-img create -f luks --object secret,id=vol_1_encrypt0,file=vol_resize_pool.vol_1.secret.qzVQrI -o key-secret=vol_1_encrypt0 /var/tmp/pool_target/vol_1 10240K
Formatting '/var/tmp/pool_target/vol_1', fmt=luks size=
10485760 key-secret=vol_1_encrypt0
qemu-img: /var/tmp/pool_target/vol_1: Data from secret vol_1_encrypt0 is not valid UTF-8
However, the created file '/var/tmp/pool_target/vol_1' is left behind in the
file system after the failure. This behavior can be observed when creating
the volume using Libvirt, via 'virsh vol-create', and then getting "volume
target path already exist" errors when trying to re-create the volume.
The volume file is created inside block_crypto_co_create_opts_luks(), in
block/crypto.c. If the bdrv_create_file() call is successful but any
succeeding step fails*, the existing 'fail' label does not take into
account the created file, leaving it behind.
This patch changes block_crypto_co_create_opts_luks() to delete
'filename' in case of failure. A failure in this point means that
the volume is now truncated/corrupted, so even if 'filename' was an
existing volume before calling qemu-img, it is now unusable. Deleting
the file it is not much worse than leaving it in the filesystem in
this scenario, and we don't have to deal with checking the file
pre-existence in the code.
* in our case, block_crypto_co_create_generic calls qcrypto_block_create,
which calls qcrypto_block_luks_create, and this function fails when
calling qcrypto_secret_lookup_as_utf8.
Reported-by: Srikanth Aithal <bssrikanth@in.ibm.com>
Suggested-by: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20200130213907.
2830642-4-danielhb413@gmail.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Daniel Henrique Barboza [Thu, 30 Jan 2020 21:39:05 +0000 (18:39 -0300)]
block.c: adding bdrv_co_delete_file
Using the new 'bdrv_co_delete_file' interface, a pure co_routine function
'bdrv_co_delete_file' inside block.c can can be used in a way similar of
the existing bdrv_create_file to to clean up a created file.
We're creating a pure co_routine because the only caller of
'bdrv_co_delete_file' will be already in co_routine context, thus there
is no need to add all the machinery to check for qemu_in_coroutine() and
create a separated co_routine to do the job.
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20200130213907.
2830642-3-danielhb413@gmail.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Daniel Henrique Barboza [Thu, 30 Jan 2020 21:39:04 +0000 (18:39 -0300)]
block: introducing 'bdrv_co_delete_file' interface
Adding to Block Drivers the capability of being able to clean up
its created files can be useful in certain situations. For the
LUKS driver, for instance, a failure in one of its authentication
steps can leave files in the host that weren't there before.
This patch adds the 'bdrv_co_delete_file' interface to block
drivers and add it to the 'file' driver in file-posix.c. The
implementation is given by 'raw_co_delete_file'.
Suggested-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <
20200130213907.
2830642-2-danielhb413@gmail.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Philippe Mathieu-Daudé [Fri, 6 Mar 2020 16:57:51 +0000 (17:57 +0100)]
tests/qemu-iotests: Fix socket_scm_helper build path
The socket_scm_helper path got corrupted during the mechanical
refactor moving the qtests files into their own sub-directory.
Fixes:
1e8a1fae7 ("test: Move qtests to a separate directory")
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <
20200306165751.18986-1-philmd@redhat.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>