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Simon Pilgrim [Sun, 27 Jan 2019 13:51:59 +0000 (13:51 +0000)]
[TTI] Add generic SADDSAT/SSUBSAT costs
Add generic costs calculation for SADDSAT/SSUBSAT intrinsics, this uses generic costs for sadd_with_overflow/ssub_with_overflow, an extra sign comparison + a selects based on the sign/overflow.
This completes PR40316
Differential Revision: https://reviews.llvm.org/D57239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352315
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Simon Pilgrim [Sun, 27 Jan 2019 12:39:38 +0000 (12:39 +0000)]
[X86] Regenerate reverse branch test to explicitly show branching and condition codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352314
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Simon Pilgrim [Sun, 27 Jan 2019 12:38:09 +0000 (12:38 +0000)]
[X86] Regenerate test to explicitly show branching and condition codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352313
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Amara Emerson [Sun, 27 Jan 2019 11:34:41 +0000 (11:34 +0000)]
Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""
I reverted it originally due to a bot failing. The underlying bug has been fixed
as of r352311.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352312
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Amara Emerson [Sun, 27 Jan 2019 10:56:20 +0000 (10:56 +0000)]
[AArch64][GlobalISel] Fix the G_EXTLOAD combiner creating non-extending illegal instructions.
This fixes loads like 's1 = load %p (load 1 from %p)' being combined with an
extend into an illegal 's8 = g_extload %p (load 1 from %p)' which doesn't do any
extension, by avoiding touching those < s8 size loads.
This bug was uncovered by a verifier update r351584, which I reverted it to keep
the bots green.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352311
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Thomas Preud'homme [Sun, 27 Jan 2019 09:02:46 +0000 (09:02 +0000)]
Revert "Add support for prefix-only CLI options"
This reverts commit r351038.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352310
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Thomas Preud'homme [Sun, 27 Jan 2019 09:02:19 +0000 (09:02 +0000)]
Revert "Detect incorrect FileCheck variable CLI definition"
This reverts commit r351039.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352309
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Thomas Preud'homme [Sun, 27 Jan 2019 09:02:05 +0000 (09:02 +0000)]
Revert "Fix defines.txt"
This reverts commit r351042.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352308
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Gabor Buella [Sun, 27 Jan 2019 06:15:39 +0000 (06:15 +0000)]
[X86] Add some missing blsr patterns
The add+and sequence followed by a branch can
happen e.g. when looping over the set bits of an integer:
```
while (x != 0) {
func(x & ~x);
x &= x - 1;
}
```
Reviewed By: ctopper
Differential Revision: https://reviews.llvm.org/D57296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352306
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Gabor Buella [Sun, 27 Jan 2019 06:05:40 +0000 (06:05 +0000)]
[NFC][X86] Add a few more blsr test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352305
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Craig Topper [Sun, 27 Jan 2019 03:37:05 +0000 (03:37 +0000)]
[X86] Add a pattern for (i64 (and (anyext def32:), 0x00000000FFFFFFFF)) to produce SUBREG_TO_REG
def32 here means the producing instruction zeroed bits 63:32. We already do this for zext, but it looks like we can get an and+anyext sometimes.
Spotted in the diffs from D33587.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352303
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Matt Arsenault [Sun, 27 Jan 2019 00:53:54 +0000 (00:53 +0000)]
GlobalISel: Fix typo in assert messages
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352301
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Matt Arsenault [Sun, 27 Jan 2019 00:52:51 +0000 (00:52 +0000)]
GlobalISel: Implement narrowScalar for mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352300
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Matt Arsenault [Sun, 27 Jan 2019 00:12:21 +0000 (00:12 +0000)]
GlobalISel: fewerElementsVector for intrinsic_trunc/intrinsic_round
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352298
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Matt Arsenault [Sat, 26 Jan 2019 23:54:53 +0000 (23:54 +0000)]
AMDGPU/GlobalISel: Use scalarize instead of clampMaxNumElements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352297
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Amara Emerson [Sat, 26 Jan 2019 23:47:09 +0000 (23:47 +0000)]
[GlobalISel][IRTranslator] Fix crash on translation of fneg.
When the fneg IR instruction was added the code to do translation wasn't
tested, and tried to get an invalid operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352296
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Matt Arsenault [Sat, 26 Jan 2019 23:47:07 +0000 (23:47 +0000)]
AMDGPU/GlobalISel: Legalize more bit ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352295
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Matt Arsenault [Sat, 26 Jan 2019 23:44:51 +0000 (23:44 +0000)]
AMDGPU/GlobalISel: Widen small uaddo/usubo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352294
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Johannes Doerfert [Sat, 26 Jan 2019 23:40:35 +0000 (23:40 +0000)]
[ValueTracking] Look through casts when determining non-nullness
Bitcast and certain Ptr2Int/Int2Ptr instructions will not alter the
value of their operand and can therefore be looked through when we
determine non-nullness.
Differential Revision: https://reviews.llvm.org/D54956
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352293
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Simon Pilgrim [Sat, 26 Jan 2019 21:29:16 +0000 (21:29 +0000)]
[X86] combineAddOrSubToADCOrSBB/combineCarryThroughADD - use oneuse for entire SDNode
Fix issue noted in D57281 that only tested the one use for the SDValue (the result flag), not the entire SUB.
I've added the getNode() to make it clearer what is intended than just the -> redirection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352291
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Simon Pilgrim [Sat, 26 Jan 2019 20:23:04 +0000 (20:23 +0000)]
[X86] combineCarryThroughADD - add support for X86::COND_A commutations (PR24545)
As discussed on PR24545, we should try to commute X86::COND_A 'icmp ugt' cases to X86::COND_B 'icmp ult' to more optimally bind the carry flag output to a SBB instruction.
Differential Revision: https://reviews.llvm.org/D57281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352289
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Simon Pilgrim [Sat, 26 Jan 2019 20:13:44 +0000 (20:13 +0000)]
[X86] Fold X86ISD::SBB(ISD::SUB(X,Y),0) -> X86ISD::SBB(X,Y) (PR25858)
We often generate X86ISD::SBB(X, 0) for carry flag arithmetic.
I had tried to create test cases for the ADC equivalent (which often uses the same pattern) but haven't managed to find anything yet.
Differential Revision: https://reviews.llvm.org/D57169
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352288
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Amaury Sechet [Sat, 26 Jan 2019 18:13:53 +0000 (18:13 +0000)]
Generate test results for combine-fcopysign.ll using update_llc_test_checks.py . NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352285
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Simon Pilgrim [Sat, 26 Jan 2019 16:40:03 +0000 (16:40 +0000)]
[X86][SSE] Generalized unsigned compares to support nonsplat constant vectors (PR39859)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352283
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Simon Pilgrim [Sat, 26 Jan 2019 16:27:48 +0000 (16:27 +0000)]
[X86] Add nonsplat increment/decrement constant vector with min/max test (PR39859)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352281
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Sanjay Patel [Sat, 26 Jan 2019 16:20:22 +0000 (16:20 +0000)]
[x86] add helper for creating a half-width shuffle; NFC
This reduces a bit of duplication between the combining and
lowering places that use it, but the primary motivation is
to make it easier to rearrange the lowering logic and solve
PR40434:
https://bugs.llvm.org/show_bug.cgi?id=40434
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352280
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Simon Pilgrim [Sat, 26 Jan 2019 13:56:53 +0000 (13:56 +0000)]
[X86] Add test case from PR34292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352274
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Simon Pilgrim [Sat, 26 Jan 2019 13:00:46 +0000 (13:00 +0000)]
[llvm-mca][X86] Add some missing DQI tests
Match more of the coverage of test\CodeGen\X86\avx512-schedule.ll as discussed on D57244
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352273
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Simon Pilgrim [Sat, 26 Jan 2019 12:51:52 +0000 (12:51 +0000)]
[X86] Add 'less_than_ideal' followup test case from PR24545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352272
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Craig Topper [Sat, 26 Jan 2019 06:27:04 +0000 (06:27 +0000)]
[X86] Autoupgrade some of the intrinsics used by stack folding tests that have been previously removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352271
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Craig Topper [Sat, 26 Jan 2019 06:27:01 +0000 (06:27 +0000)]
[X86] Remove and autoupgrade vpconflict intrinsics that take a mask and passthru argument.
We have unmasked versions as of r352172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352270
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Craig Topper [Sat, 26 Jan 2019 02:44:58 +0000 (02:44 +0000)]
Revert r352255 "[SelectionDAG][X86] Don't use SEXTLOAD for promoting masked loads in the type legalizer"
This might be breaking an lldb windows buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352268
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Craig Topper [Sat, 26 Jan 2019 02:41:54 +0000 (02:41 +0000)]
[X86] Remove GCCBuiltins from 512-bit cvt(u)qqtops, cvt(u)qqtopd, and cvt(u)dqtops intrinsics. Add new variadic uitofp/sitofp with rounding mode intrinsics.
Summary: See clang patch D56998 for a full description.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D56999
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352266
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Matt Arsenault [Sat, 26 Jan 2019 01:42:13 +0000 (01:42 +0000)]
GlobalISel: Fix address space limit in LLT
The IR enforced limit for the address space is 24-bits, but LLT was
only using 23-bits. Additionally, the argument to the constructor was
truncating to 16-bits.
A similar problem still exists for the number of vector elements. The
IR enforces no limit, so if you try to use a vector with > 65535
elements the IRTranslator asserts in the LLT constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352264
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Thomas Lively [Sat, 26 Jan 2019 01:25:37 +0000 (01:25 +0000)]
[WebAssembly][NFC] Group SIMD-related ISel configuration
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish
Differential Revision: https://reviews.llvm.org/D57263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352262
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Nemanja Ivanovic [Sat, 26 Jan 2019 01:18:48 +0000 (01:18 +0000)]
[PowerPC] Update Vector Costs for P9
For the power9 CPU, vector operations consume a pair of execution units rather
than one execution unit like a scalar operation. Update the target transform
cost functions to reflect the higher cost of vector operations when targeting
Power9.
Patch by RolandF.
Differential revision: https://reviews.llvm.org/D55461
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352261
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Craig Topper [Sat, 26 Jan 2019 01:17:09 +0000 (01:17 +0000)]
[X86] Add DAG combine to merge vzext_movl with the various fp<->int conversion operations that only write the lower 64-bits of an xmm register and zero the rest.
Summary: We have isel patterns for this, but we're missing some load patterns and all broadcast patterns. A DAG combine seems like a better fit for this.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D56971
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352260
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Vedant Kumar [Sat, 26 Jan 2019 00:33:15 +0000 (00:33 +0000)]
[llvm-nm] Print out N_COLD_FUNC as "cold func"
Per post-commit feedback from Mike, have llvm-nm print out this symbol
attribute as "[cold func]".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352258
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Artem Belevich [Sat, 26 Jan 2019 00:28:32 +0000 (00:28 +0000)]
[NVPTX] Some nvvm.read.ptx.sreg intrinsics should have IntrInaccessibleMemOnly attribute.
These intrinsics may return different values every time they are called
and should not be CSE'd. IntrInaccessibleMemOnly appears to be the right
attribute to model this behavior.
Differential Revision: https://reviews.llvm.org/D57259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352256
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Craig Topper [Sat, 26 Jan 2019 00:26:37 +0000 (00:26 +0000)]
[SelectionDAG][X86] Don't use SEXTLOAD for promoting masked loads in the type legalizer
Summary:
I'm not sure why we were using SEXTLOAD. EXTLOAD seems more appropriate since we don't care about the upper bits.
This patch changes this and then modifies the X86 post legalization combine to emit a extending shuffle instead of a sign_extend_vector_inreg. Could maybe use an any_extend_vector_inreg, but I just did what we already do in LowerLoad. I think we can actually get rid of this code entirely if we switch to -x86-experimental-vector-widening-legalization.
On AVX512 targets I think we might be able to use a masked vpmovzx and not have to expand this at all.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D57186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352255
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Hans Wennborg [Fri, 25 Jan 2019 22:45:17 +0000 (22:45 +0000)]
Build LLVM-C.dll by default on windows and enable in release package
With the fixes to the building of LLVM-C.dll in D56781 this should now
be safe to land. This will greatly simplify dealing with LLVM for people
that just want to use the C API on windows. This is a follow up from
D35077.
Patch by Jakob Bornecrantz!
Differential revision: https://reviews.llvm.org/D56774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352250
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Alexey Lapshin [Fri, 25 Jan 2019 21:59:53 +0000 (21:59 +0000)]
[NFC] Test commit : fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352248
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Alex Bradbury [Fri, 25 Jan 2019 21:55:48 +0000 (21:55 +0000)]
[RISCV] Add target DAG combine for bitcast fabs/fneg on RV32FD
DAGCombiner::visitBITCAST will perform:
fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
As shown in double-bitmanip-dagcombines.ll, this can be advantageous. But
RV32FD doesn't use bitcast directly (as i64 isn't a legal type), and instead
uses RISCVISD::SplitF64. This patch adds an equivalent DAG combine for
SplitF64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352247
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Mircea Trofin [Fri, 25 Jan 2019 21:49:54 +0000 (21:49 +0000)]
[llvm] Opt-in flag for X86DiscriminateMemOps
Summary:
Currently, if an instruction with a memory operand has no debug information,
X86DiscriminateMemOps will generate one based on the first line of the
enclosing function, or the last seen debug info.
This may cause confusion in certain debugging scenarios. The long term
approach would be to use the line number '0' in such cases, however, that
brings in challenges: the base discriminator value range is limited
(4096 values).
For the short term, adding an opt-in flag for this feature.
See bug 40319 (https://bugs.llvm.org/show_bug.cgi?id=40319)
Reviewers: dblaikie, jmorse, gbedwell
Reviewed By: dblaikie
Subscribers: aprantl, eraman, hiraditya
Differential Revision: https://reviews.llvm.org/D57257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352246
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Jessica Paquette [Fri, 25 Jan 2019 21:28:27 +0000 (21:28 +0000)]
[GlobalISel][AArch64][NFC] Fix incorrect comment in selectUnmergeValues
s/scalar/vector/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352243
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Alina Sbirlea [Fri, 25 Jan 2019 21:12:08 +0000 (21:12 +0000)]
Revert rL352238.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352241
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Alex Bradbury [Fri, 25 Jan 2019 21:06:47 +0000 (21:06 +0000)]
[RISCV] Add another potential combine to {double,float}-bitmanip-dagcombines.ll
(fcopysign a, (fneg b)) will be expanded to bitwise operations by
DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN if the floating point type isn't
legal. Arguably it might be worth doing a combine even if it is legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352240
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Alina Sbirlea [Fri, 25 Jan 2019 20:51:55 +0000 (20:51 +0000)]
[WarnMissedTransforms] Set default to 1.
Summary:
Set default value for retrieved attributes to 1, since the check is against 1.
Eliminates the warning noise generated when the attributes are not present.
Reviewers: sanjoy
Subscribers: jlebar, llvm-commits
Differential Revision: https://reviews.llvm.org/D57253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352238
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Ana Pazos [Fri, 25 Jan 2019 20:22:49 +0000 (20:22 +0000)]
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI
This reapplies commit r352010 with RISC-V test fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352237
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Guozhi Wei [Fri, 25 Jan 2019 19:45:13 +0000 (19:45 +0000)]
[MBP] Don't move bottom block before header if it can't reduce taken branches
If bottom of block BB has only one successor OldTop, in most cases it is profitable to move it before OldTop, except the following case:
-->OldTop<-
| . |
| . |
| . |
---Pred |
| |
BB-----
Move BB before OldTop can't reduce the number of taken branches, this patch detects this case and prevent the moving.
Differential Revision: https://reviews.llvm.org/D57067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352236
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Craig Topper [Fri, 25 Jan 2019 18:37:36 +0000 (18:37 +0000)]
[X86] Combine masked store and truncate into masked truncating stores.
We also need to combine to masked truncating with saturation stores, but I'm leaving that for a future patch.
This does regress some tests that used truncate wtih saturation followed by a masked store. Those now use a truncating store and use min/max to saturate.
Differential Revision: https://reviews.llvm.org/D57218
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352230
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Vedant Kumar [Fri, 25 Jan 2019 18:30:37 +0000 (18:30 +0000)]
[HotColdSplit] Introduce a cost model to control splitting behavior
The main goal of the model is to avoid *increasing* function size, as
that would eradicate any memory locality benefits from splitting. This
happens when:
- There are too many inputs or outputs to the cold region. Argument
materialization and reloads of outputs have a cost.
- The cold region has too many distinct exit blocks, causing a large
switch to be formed in the caller.
- The code size cost of the split code is less than the cost of a
set-up call.
A secondary goal is to prevent excessive overall binary size growth.
With the cost model in place, I experimented to find a splitting
threshold that works well in practice. To make warm & cold code easily
separable for analysis purposes, I moved split functions to a "cold"
section. I experimented with thresholds between [0, 4] and set the
default to the threshold which minimized geomean __text size.
Experiment data from building LNT+externals for X86 (N = 639 programs,
all sizes in bytes):
| Configuration | __text geom size | __cold geom size | TEXT geom size |
| **-Os** | 1736.3 | 0, n=0 | 10961.6 |
| -Os, thresh=0 | 1740.53 | 124.482, n=134 | 11014 |
| -Os, thresh=1 | 1734.79 | 57.8781, n=90 | 10978.6 |
| -Os, thresh=2 | ** 1733.85 ** | 65.6604, n=61 | 10977.6 |
| -Os, thresh=3 | 1733.85 | 65.3071, n=61 | 10977.6 |
| -Os, thresh=4 | 1735.08 | 67.5156, n=54 | 10965.7 |
| **-Oz** | 1554.4 | 0, n=0 | 10153 |
| -Oz, thresh=2 | ** 1552.2 ** | 65.633, n=61 | 10176 |
| **-O3** | 2563.37 | 0, n=0 | 13105.4 |
| -O3, thresh=2 | ** 2559.49 ** | 71.1072, n=61 | 13162.4 |
Picking thresh=2 reduces the geomean __text section size by 0.14% at
-Os, -Oz, and -O3 and causes ~0.2% growth in the TEXT segment. Note that
TEXT size is page-aligned, whereas section sizes are byte-aligned.
Experiment data from building LNT+externals for ARM64 (N = 558 programs,
all sizes in bytes):
| Configuration | __text geom size | __cold geom size | TEXT geom size |
| **-Os** | 1763.96 | 0, n=0 | 42934.9 |
| -Os, thresh=2 | ** 1760.9 ** | 76.6755, n=61 | 42934.9 |
Picking thresh=2 reduces the geomean __text section size by 0.17% at
-Os and causes no growth in the TEXT segment.
Measurements were done with D57082 (r352080) applied.
Differential Revision: https://reviews.llvm.org/D57125
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352228
91177308-0d34-0410-b5e6-
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Vedant Kumar [Fri, 25 Jan 2019 18:30:22 +0000 (18:30 +0000)]
[MC] Teach the MachO object writer about N_FUNC_COLD
N_FUNC_COLD is a new MachO symbol attribute. It's a hint to the linker
to order a symbol towards the end of its section, to improve locality.
Example:
```
void a1() {}
__attribute__((cold)) void a2() {}
void a3() {}
int main() {
a1();
a2();
a3();
return 0;
}
```
A linker that supports N_FUNC_COLD will order _a2 to the end of the text
section. From `nm -njU` output, we see:
```
_a1
_a3
_main
_a2
```
Differential Revision: https://reviews.llvm.org/D57190
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352227
91177308-0d34-0410-b5e6-
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Florian Hahn [Fri, 25 Jan 2019 17:48:31 +0000 (17:48 +0000)]
[opt-viewer] Add javascript to expand/hide full message for multiline remarks.
This patch adds support for displaying remarks with multiple
lines. For such remarks, it creates a hidden div
containing the message's lines except the first one in a <pre>
tag. It also prepends a link (with '+' as text) to the regular remark
line. This link can be used to show/hide the div containing the
full remark.
In combination with D57159, this allows for better displaying of
multiline remarks in the html pages generated by opt-viewer.
The Javascript is very simple and should be supported by any recent
major browser.
Reviewers: hfinkel, anemet, thegameg, serge-sans-paille
Reviewed By: anemet
Differential Revision: https://reviews.llvm.org/D57167
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352223
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 25 Jan 2019 17:00:41 +0000 (17:00 +0000)]
[x86] simplify logic in lowerShuffleWithUndefHalf(); NFCI
This seems unnecessarily complicated because we gave names to
opposite polarity bools and have code comments that don't really
line up with the logic.
Step 1: remove UndefUpper and assert that it is the opposite of
UndefLower after the initial early exit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352217
91177308-0d34-0410-b5e6-
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Florian Hahn [Fri, 25 Jan 2019 16:59:06 +0000 (16:59 +0000)]
[DiagnosticInfo] Add support for preserving newlines in remark arguments.
This patch adds a new type StringBlockVal which can be used to emit a
YAML block scalar, which preserves newlines in a multiline string. It
also updates MappingTraits<DiagnosticInfoOptimizationBase::Argument> to
use it for argument values with more than a single newline.
This is helpful for remarks that want to display more in-depth
information in a more structured way.
Reviewers: thegameg, anemet
Reviewed By: anemet
Subscribers: hfinkel, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D57159
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352216
91177308-0d34-0410-b5e6-
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Tom Weaver [Fri, 25 Jan 2019 16:29:35 +0000 (16:29 +0000)]
[TEST][COMMIT] - fix comment typo in AsmPrinter/DwarfDebug.cpp - NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352214
91177308-0d34-0410-b5e6-
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Javed Absar [Fri, 25 Jan 2019 16:17:57 +0000 (16:17 +0000)]
[TblGen][NFC] Fix documentation formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352212
91177308-0d34-0410-b5e6-
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Alex Bradbury [Fri, 25 Jan 2019 16:04:04 +0000 (16:04 +0000)]
[RISCV][NFC] s/f32/f64 in double-arith.ll
The intrinsic names erroneously used the .f32 variant. As the return and
argument types were still double the intrinsics calls worked properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352211
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 25 Jan 2019 15:58:28 +0000 (15:58 +0000)]
[X86] Simplify X86ISD::ADD/SUB if we don't use the result flag
Simplify to the generic ISD::ADD/SUB if we don't make use of the result flag.
This mainly helps with ADDCARRY/SUBBORROW intrinsics which get expanded to X86ISD::ADD/SUB but could be simplified further.
Noticed in some of the test cases in PR31754
Differential Revision: https://reviews.llvm.org/D57234
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352210
91177308-0d34-0410-b5e6-
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Sanjay Patel [Fri, 25 Jan 2019 15:37:42 +0000 (15:37 +0000)]
[x86] narrow a shuffle that doesn't use or set any high elements
This isn't the final fix for our reduction/horizontal codegen, but it takes care
of a lot of the problems. After we narrow the shuffle, existing combines for
insert/extract and binops kick in, and we end up with cheaper 128-bit ops.
The avg and mul reduction tests show an existing shuffle lowering hole for
AVX2/AVX512. I think in its most minimal form this is:
https://bugs.llvm.org/show_bug.cgi?id=40434
...but we might need multiple fixes to get it right.
Differential Revision: https://reviews.llvm.org/D57156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352209
91177308-0d34-0410-b5e6-
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Clement Courbet [Fri, 25 Jan 2019 15:25:52 +0000 (15:25 +0000)]
Revert r351954 "Add a value_type to ArrayRef."
This breaks arm self-hosted buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352206
91177308-0d34-0410-b5e6-
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Sam McCall [Fri, 25 Jan 2019 15:05:33 +0000 (15:05 +0000)]
[JSON] Work around excess-precision issue when comparing T_Integer numbers.
Reviewers: bkramer
Subscribers: kristina, llvm-commits
Differential Revision: https://reviews.llvm.org/D57237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352204
91177308-0d34-0410-b5e6-
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Nico Weber [Fri, 25 Jan 2019 14:53:30 +0000 (14:53 +0000)]
gn build: Merge r352149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352202
91177308-0d34-0410-b5e6-
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Nico Weber [Fri, 25 Jan 2019 14:52:50 +0000 (14:52 +0000)]
gn build: Revert r352200, commit message was wrong
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352201
91177308-0d34-0410-b5e6-
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Nico Weber [Fri, 25 Jan 2019 14:50:14 +0000 (14:50 +0000)]
gn build: Merge r352148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352200
91177308-0d34-0410-b5e6-
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Alex Bradbury [Fri, 25 Jan 2019 14:33:08 +0000 (14:33 +0000)]
[RISCV] Add tests to demonstrate bitcasted fneg/fabs dagcombines
This target-independent code won't trigger for cases such as RV32FD where
custom SelectionDAG nodes are generated. These new tests demonstrate such
cases. Additionally, float-arith.ll was updated so that fneg.s, fsgnjn.s, and
fabs.s selection patterns are actually exercised.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352199
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 25 Jan 2019 14:29:57 +0000 (14:29 +0000)]
Fix line endings and trim trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352198
91177308-0d34-0410-b5e6-
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Haojian Wu [Fri, 25 Jan 2019 14:05:18 +0000 (14:05 +0000)]
gitignore: ignore clangd index files.
Reviewers: kadircet
Subscribers: ilya-biryukov, ioeric, MaskRay, jkorous, arphaman, llvm-commits
Differential Revision: https://reviews.llvm.org/D57227
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352197
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 25 Jan 2019 12:26:27 +0000 (12:26 +0000)]
[X86] Add addcarry/subborrow combine tests
Show failure to simplify cases with zero op/flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352196
91177308-0d34-0410-b5e6-
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James Henderson [Fri, 25 Jan 2019 11:49:21 +0000 (11:49 +0000)]
[llvm-symbolizer] Add switch to adjust addresses by fixed offset
If a stack trace or similar has a list of addresses from an executable
or DSO loaded at a variable address (e.g. due to ASLR), the addresses
will not directly correspond to the addresses stored in the object file.
If a user wishes to use llvm-symbolizer, they have to subtract the load
address from every address. This is somewhat inconvenient, especially as
the output of --print-address will result in the adjusted address being
listed, rather than the address coming from the stack trace, making it
harder to map results between the two.
This change adds a new switch to llvm-symbolizer --adjust-vma which
takes an offset, which is then used to automatically do this
calculation. The printed address remains the input address (allowing for
easy mapping), whilst the specified offset is applied to the addresses
when performing the lookup.
The switch is conceptually similar to llvm-objdump's new switch of the
same name (see D57051), which in turn mirrors a GNU switch. There is no
equivalent switch in addr2line.
Reviewed by: grimar
Differential Revision: https://reviews.llvm.org/D57151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352195
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Max Kazantsev [Fri, 25 Jan 2019 11:47:16 +0000 (11:47 +0000)]
[NFC] One more crashing test on LoopSimplifyCFG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352194
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 25 Jan 2019 11:38:40 +0000 (11:38 +0000)]
Fix gcc -Wparentheses warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352193
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 25 Jan 2019 11:34:58 +0000 (11:34 +0000)]
Fix gcc -Wparentheses warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352191
91177308-0d34-0410-b5e6-
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Max Kazantsev [Fri, 25 Jan 2019 11:32:21 +0000 (11:32 +0000)]
[NFC] Add failing test on LCSSA forming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352190
91177308-0d34-0410-b5e6-
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Diana Picus [Fri, 25 Jan 2019 10:48:42 +0000 (10:48 +0000)]
[ARM GlobalISel] Support shifts for Thumb2
Same as ARM.
On this occasion we split some of the instruction select tests for more
complicated instructions into their own files, so we can reuse them for
ARM and Thumb mode. Likewise for the legalizer tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352188
91177308-0d34-0410-b5e6-
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Diana Picus [Fri, 25 Jan 2019 10:48:35 +0000 (10:48 +0000)]
[ARM GlobalISel] Remove rebase artifact from r351882. NFC
r351882 introduced some superfluous calls to mark G_INTTOPTR and
G_PTRTOINT as legal (looks like a rebase mishap). Remove them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352187
91177308-0d34-0410-b5e6-
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Javed Absar [Fri, 25 Jan 2019 10:25:25 +0000 (10:25 +0000)]
[TblGen] Extend !if semantics through new feature !cond
This patch extends TableGen language with !cond operator.
Instead of embedding !if inside !if which can get cumbersome,
one can now use !cond.
Below is an example to convert an integer 'x' into a string:
!cond(!lt(x,0) : "Negative",
!eq(x,0) : "Zero",
!eq(x,1) : "One,
1 : "MoreThanOne")
Reviewed By: hfinkel, simon_tatham, greened
Differential Revision: https://reviews.llvm.org/D55758
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352185
91177308-0d34-0410-b5e6-
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Douglas Yung [Fri, 25 Jan 2019 09:57:20 +0000 (09:57 +0000)]
[llvm-objcopy] Add support for -g as an alias for --strip-debug
This change adds an option -g to llvm-objcopy which is an alias for the existing option --strip-debug.
This fixes PR40003.
Reviewed by: alexshap
Differential Revision: https://reviews.llvm.org/D57217
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352182
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Fri, 25 Jan 2019 09:17:30 +0000 (09:17 +0000)]
[llvm-mca][X86] Add missing shuffle tests
Match the coverage of test\CodeGen\X86\avx512-shuffle-schedule.ll so we can get rid of -print-schedule (and fix PR37160) without losing schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352179
91177308-0d34-0410-b5e6-
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Anton Korobeynikov [Fri, 25 Jan 2019 09:14:05 +0000 (09:14 +0000)]
[MSP430] Fix absolute addressing mode printing in AsmPrinter
Align checks for absolute addressing mode with its current
implementation (SR is used as a base register).
This fixes https://bugs.llvm.org/show_bug.cgi?id=39993
Patch by Kristina Bessonova!
Differential Revision: https://reviews.llvm.org/D56785
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352178
91177308-0d34-0410-b5e6-
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Max Kazantsev [Fri, 25 Jan 2019 08:46:00 +0000 (08:46 +0000)]
[NFC] Add test with multiple loops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352176
91177308-0d34-0410-b5e6-
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Zi Xuan Wu [Fri, 25 Jan 2019 07:24:59 +0000 (07:24 +0000)]
[PowerPC] Enhance the fast selection of cmp instruction and clean up related asserts
Fast selection of llvm icmp and fcmp instructions is not handled well about VSX instruction support.
We'd use VSX float comparison instruction instead of non-vsx float comparison instruction
if the operand register class is VSSRC or VSFRC because i32 and i64 are mapped to VSSRC and
VSFRC correspondingly if VSX feature is opened.
If the target does not have corresponding VSX instruction comparison for some type,
just copy VSX-related register to common float register class and use non-vsx comparison instruction.
Differential Revision: https://reviews.llvm.org/D57078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352174
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Craig Topper [Fri, 25 Jan 2019 07:08:07 +0000 (07:08 +0000)]
[X86] Add non-masked versions of vpconflict intrinsics so we can use a select in the header file in clang.
I'll remove and autoupgrade the old intrinsics in a future commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352172
91177308-0d34-0410-b5e6-
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Alex Bradbury [Fri, 25 Jan 2019 05:11:34 +0000 (05:11 +0000)]
[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M
Follow the same custom legalisation strategy as used in D57085 for
variable-length shifts (see that patch summary for more discussion). Although
we may lose out on some late-stage DAG combines, I think this custom
legalisation strategy is ultimately easier to reason about.
There are some codegen changes in rv64m-exhaustive-w-insts.ll but they are all
neutral in terms of the number of instructions.
Differential Revision: https://reviews.llvm.org/D57096
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352171
91177308-0d34-0410-b5e6-
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Max Kazantsev [Fri, 25 Jan 2019 05:05:02 +0000 (05:05 +0000)]
[LoopSimplifyCFG] Fix inconsistency in blocks in loop markup
2nd part of D57095 with the same reason, just in another place. We never
fold branches that are not immediately in the current loop, but this check
is missing in `IsEdgeLive` As result, it may think that the edge in subloop is
dead while it's live. It's a pessimization in the current stance.
Differential Revision: https://reviews.llvm.org/D57147
Reviewed By: rupprecht
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352170
91177308-0d34-0410-b5e6-
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Alex Bradbury [Fri, 25 Jan 2019 05:04:00 +0000 (05:04 +0000)]
[RISCV] Custom-legalise 32-bit variable shifts on RV64
The previous DAG combiner-based approach had an issue with infinite loops
between the target-dependent and target-independent combiner logic (see
PR40333). Although this was worked around in rL351806, the combiner-based
approach is still potentially brittle and can fail to select the 32-bit shift
variant when profitable to do so, as demonstrated in the pr40333.ll test case.
This patch instead introduces target-specific SelectionDAG nodes for
SHLW/SRLW/SRAW and custom-lowers variable i32 shifts to them. pr40333.ll is a
good example of how this approach can improve codegen.
This adds DAG combine that does SimplifyDemandedBits on the operands (only
lower 32-bits of first operand and lower 5 bits of second operand are read).
This seems better than implementing SimplifyDemandedBitsForTargetNode as there
is no guarantee that would be called (and it's not for e.g. the anyext return
test cases). Also implements ComputeNumSignBitsForTargetNode.
There are codegen changes in atomic-rmw.ll and atomic-cmpxchg.ll but the new
instruction sequences are semantically equivalent.
Differential Revision: https://reviews.llvm.org/D57085
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352169
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 25 Jan 2019 04:54:00 +0000 (04:54 +0000)]
AMDGPU/GlobalISel: Remove leftover setAction
Also move G_GEP actions together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352168
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 25 Jan 2019 04:53:57 +0000 (04:53 +0000)]
AMDGPU/GlobalISel: Scalarize add/sub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352167
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 25 Jan 2019 04:37:33 +0000 (04:37 +0000)]
GlobalISel: fewerElementsVector for more cast types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352166
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 25 Jan 2019 04:03:38 +0000 (04:03 +0000)]
GlobalISel: fewerElementsVector for a few more trivial ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352165
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 25 Jan 2019 03:23:04 +0000 (03:23 +0000)]
AMDGPU/GlobalISel: Legalize smulh/umulh and scalarize mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352162
91177308-0d34-0410-b5e6-
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Vedant Kumar [Fri, 25 Jan 2019 03:22:38 +0000 (03:22 +0000)]
[HotColdSplit] Describe the pass in more detail, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352161
91177308-0d34-0410-b5e6-
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Vedant Kumar [Fri, 25 Jan 2019 03:22:23 +0000 (03:22 +0000)]
[HotColdSplit] Split more aggressively before/after cold invokes
While a cold invoke itself and its unwind destination can't be
extracted, code which unconditionally executes before/after the invoke
may still be profitable to extract.
With cost model changes from D57125 applied, this gives a 3.5% increase
in split text across LNT+externals on arm64 at -Os.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352160
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 25 Jan 2019 02:59:34 +0000 (02:59 +0000)]
GlobalISel: Support fewerElementsVector for icmp/fcmp
Also legalize 64-bit compares for AMDGPU
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352157
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 25 Jan 2019 02:36:32 +0000 (02:36 +0000)]
GlobalISel: Implement fewerElementsVector for extensions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352155
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Fri, 25 Jan 2019 02:08:46 +0000 (02:08 +0000)]
hwasan: If we split the entry block, move static allocas back into the entry block.
Otherwise they are treated as dynamic allocas, which ends up increasing
code size significantly. This reduces size of Chromium base_unittests
by 2MB (6.7%).
Differential Revision: https://reviews.llvm.org/D57205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352152
91177308-0d34-0410-b5e6-
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Peter Collingbourne [Fri, 25 Jan 2019 01:18:55 +0000 (01:18 +0000)]
gn build: Set is_clang to true in stage2 toolchains.
Differential Revision: https://reviews.llvm.org/D57202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352146
91177308-0d34-0410-b5e6-
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Matt Arsenault [Fri, 25 Jan 2019 00:51:00 +0000 (00:51 +0000)]
GlobalISel: Add convenience mutatations to scalarize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352143
91177308-0d34-0410-b5e6-
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Bob Haarman [Fri, 25 Jan 2019 00:33:05 +0000 (00:33 +0000)]
simplify COFF module assembly test and move it to Object
Reviewers: pcc, rnk
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D57192
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352142
91177308-0d34-0410-b5e6-
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