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Eric Engestrom [Mon, 11 Jun 2018 17:34:42 +0000 (18:34 +0100)]
README: wording fix for previous commit
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 11 Jun 2018 17:31:06 +0000 (18:31 +0100)]
README: add link to WhosWho for IRC nicks
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Fri, 8 Jun 2018 15:56:03 +0000 (16:56 +0100)]
add project README
Now that we're using GitLab, let's take advantage of the "landing page"
README feature with some minimal information, mostly to point people to
the right resources.
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Sun, 10 Jun 2018 17:42:45 +0000 (18:42 +0100)]
i965: fix resource leak
v2: intel_miptree_release() already takes care of the planes, no need
to hand-code the loop (Lionel)
Coverity ID:
1436909
Fixes:
3352f2d746d3959b22ca4 "i965: Create multiple miptrees for planar YUV images"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Rob Clark [Thu, 7 Jun 2018 19:44:28 +0000 (15:44 -0400)]
freedreno/ir3: use pipe_image_view's cpp
At least for PIPE_BUFFER, we could get the resource used as (for
example) R32F imageBuffer. So using cpp=1 from the rsc is wrong.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 7 Jun 2018 17:54:15 +0000 (13:54 -0400)]
freedreno/ir3: fix image dimensions offset
copy-pasta fail from how SSBO sizes are handled.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Tue, 5 Jun 2018 13:50:26 +0000 (09:50 -0400)]
freedreno/a5xx: correct image/ssbo offset
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 4 Jun 2018 20:40:52 +0000 (16:40 -0400)]
freedreno/ir3: use saml always if we have lod
In some cases we get plain tex opcodes (but w/ a lod argument).. in this
case always use the saml instruction.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 4 Jun 2018 17:31:47 +0000 (13:31 -0400)]
freedreno/ir3: don't cp absneg into meta:fi
If using a fanin (collect) to collect of consecutive registers together,
we can CP mov's into the fanin, but not (abs) or (neg). No places that
allow those modifiers are consuming a fanin anyways. But this caused an
absneg to be lost between a ldgb and stgb for shaders like:
outputs[n] = abs(input[n])
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 26 Apr 2018 18:54:24 +0000 (14:54 -0400)]
freedreno/ir3: rework size/type conversion instructions
With 8b and 16b, there are a lot more to handle.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 26 Apr 2018 18:52:09 +0000 (14:52 -0400)]
freedreno/ir3: propagate HALF flag across fanout
If we have a fanout (split) meta instruction to split the result of a
vector instruction, propagate the HALF flag back to the original
instruction. Otherwise result ends up in a full precision register
while instruction(s) that use the result look in a half-precision
register.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 1 Jun 2018 18:56:57 +0000 (14:56 -0400)]
freedreno/a5xx: add sample-id/sample-mask-in
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 1 Jun 2018 18:56:38 +0000 (14:56 -0400)]
freedreno/ir3: add sample-id/sample-mask-in
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 1 Jun 2018 15:59:04 +0000 (11:59 -0400)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 31 May 2018 23:17:30 +0000 (19:17 -0400)]
freedreno/ir3: image atomics use image-store path
image reads are handled via tex state, whereas image writes and atomics
are handled via SSBO state block. Previously we were only considering
image write, and not image atomics which also uses the SSBO state block.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Kyle Brenneman [Wed, 6 Jun 2018 15:08:47 +0000 (09:08 -0600)]
egl/glvnd: Fix a segfault in eglGetProcAddress.
If FindProcIndex in egldispatchstubs.c is called with a name that's less than
the first entry in the array, it would end up trying to store an index of -1 in
an unsigned integer, wrap around to 2^32, and then crash when it tries to look
that up.
Change FindProcIndex so that it uses bsearch(3) instead of implementing its own
binary search, like the GLX equivalent FindGLXFunction does.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Jordan Justen [Wed, 6 Jun 2018 08:57:15 +0000 (01:57 -0700)]
mesa/program_binary: add implicit UseProgram after successful ProgramBinary
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106810
Fixes:
b4c37ce2140 "i965: Add ARB_get_program_binary support using nir_serialization"
Ref:
3fe8d04a6d6 "mesa: don't always set _NEW_PROGRAM when linking"
Ref:
c505d6d8522 "mesa: use gl_program for CurrentProgram rather than gl_shader_program"
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Dave Airlie [Mon, 11 Jun 2018 00:49:14 +0000 (10:49 +1000)]
features.txt: update virgl GL4.1 status.
All the features for GL4.1 are done (64-bit attribs were part of
the fp64 enable).
Once tessellation shaders land this will be advertised
Dave Airlie [Mon, 21 May 2018 04:00:37 +0000 (14:00 +1000)]
virgl: enable ARB_gpu_shader_fp64
This enables ARB_gpu_shader_fp64 if the host provides it.
Tested-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Samuel Pitoiset [Fri, 8 Jun 2018 09:38:01 +0000 (11:38 +0200)]
radv: add a workaround for DXVK hangs by setting amdgpu-skip-threshold
Workaround for bug in llvm that causes the GPU to hang in presence
of nested loops because there is an exec mask issue. The proper
solution is to fix LLVM but this might require a bunch of work.
This fixes a bunch of GPU hangs that happen with DXVK.
Vega10:
Totals from affected shaders:
SGPRS: 110456 -> 110456 (0.00 %)
VGPRS: 122800 -> 122800 (0.00 %)
Spilled SGPRs: 7478 -> 7478 (0.00 %)
Spilled VGPRs: 36 -> 36 (0.00 %)
Code Size:
9901104 ->
9922928 (0.22 %) bytes
Max Waves: 7143 -> 7143 (0.00 %)
Code size slightly increases because it inserts more branch
instructions but that's expected. I don't see any real performance
changes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105613
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 8 Jun 2018 15:59:49 +0000 (17:59 +0200)]
radv: fix missing ZRANGE_PRECISION(1) for GFX9+
ZRANGE_PRECISION(1) seems to be the default optimal value, but
it was only set for VI and older chips.
This fixes a rendering issue with Banished through DXVK, and
might fix more than that.
There is still the ZRANGE_PRECISION bug that we need to handle
but that can be fixed later.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Gustavo Lima Chaves [Tue, 20 Mar 2018 06:06:45 +0000 (23:06 -0700)]
anv: enable VK_EXT_shader_stencil_export
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Gustavo Lima Chaves [Mon, 12 Feb 2018 02:26:40 +0000 (18:26 -0800)]
spirv: add/hookup SpvCapabilityStencilExportEXT
v2:
An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior
also follows, with the interpretation to said mode being we prevent
writes to the built-in FragStencilRefEXT variable when the execution
mode isn't set.
v3:
A more cautious reading of
1db44252d01bf7539452ccc2b5210c74b8dcd573 led
me to a missing change that would stop (what I later discovered were)
GPU hangs on the CTS test written to exercise this.
v4:
Turn FragStencilRefEXT decoration usage without StencilRefReplacingEXT
mode into a warning, instead of trying to make the variable read-only.
If we are to follow the originating extension on GL, the built-in
variable in question should never be readable anyway.
v5/v6: rebases.
v7:
Fix check for gen9 lost in rebase. (Ilia)
Reduce the scope of the bool used to track whether
SpvExecutionModeStencilRefReplacingEXT was used. Was in shader_info,
moved to vtn_builder. (Jason)
v8:
Assert for fragment shader handling StencilRefReplacingEXT execution
mode. (Caio)
Remove warning logic, since an entry point might not have
StencilRefReplacingEXT execution mode, but the global output variable
might still exist for another entry point in the module. (Jason)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Anholt [Mon, 4 Jun 2018 22:32:14 +0000 (15:32 -0700)]
travis: Add the v3d driver to the automake build.
Hopefully this reduces the number of fixup commits we need for the
automake build.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Anholt [Tue, 5 Jun 2018 15:18:51 +0000 (08:18 -0700)]
travis: Do our automake build tests with srcdir != builddir.
This will catch many automake bugs that end-users get to experience first,
otherwise.
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Engestrom [Thu, 7 Jun 2018 14:45:01 +0000 (15:45 +0100)]
autotools/meson: compile against wayland-egl-*backend*
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106861
Fixes:
1db4ec05462914096b1f "egl: rewire the build systems to use libwayland-egl"
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Andreas Hartmetz <ahartmetz@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Cameron Kumar [Fri, 1 Jun 2018 11:16:19 +0000 (12:16 +0100)]
vulkan/wsi: Destroy swapchain images after terminating FIFO queues
The queue_manager thread can access the images from x11_present_to_x11,
hence this reorder prevents dereferencing of dangling pointers.
Cc: "18.1" <mesa-stable@lists.freedesktop.org>
Fixes:
e73d136a023080 ("vulkan/wsi/x11: Implement FIFO mode.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Sonny Jiang [Thu, 7 Jun 2018 16:13:53 +0000 (12:13 -0400)]
radeonsi: emit_dpbb_state packets optimization
Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Thu, 7 Jun 2018 16:13:52 +0000 (12:13 -0400)]
radeonsi: emit_clip_state packets optimization
Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Thu, 7 Jun 2018 16:13:51 +0000 (12:13 -0400)]
radeonsi: emit_msaa_sample_locs packets optimization
Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Thu, 7 Jun 2018 16:13:50 +0000 (12:13 -0400)]
radeonsi: emit_msaa_config packets optimization
Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Thu, 7 Jun 2018 16:13:49 +0000 (12:13 -0400)]
radeonsi: emit_cb_render_state packets optimization
Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Thu, 7 Jun 2018 16:13:48 +0000 (12:13 -0400)]
radeonsi: emit_db_render_state packets optimization
Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Jan Vesely [Thu, 7 Jun 2018 21:24:59 +0000 (17:24 -0400)]
drisw: Fix invalid pointer arithmetic
Use of void * in pointer arithmetic is illegal, use char * instead.
Fixes:
cf54bd5e8381dba18d52fe438acda20cc1685bf3 ("drisw: use shared memory when possible")
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Timothy Arceri [Thu, 7 Jun 2018 01:03:10 +0000 (11:03 +1000)]
radeonsi: fix possible truncation on renderer string
Fixes truncation warning in gcc 8.1
Fixes:
8539c9bf3158 ("gallium/radeon: add the kernel version into the renderer string")
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Timothy Arceri [Thu, 7 Jun 2018 00:30:01 +0000 (10:30 +1000)]
ac: fix possible truncation of intrinsic name
Fixes the gcc warning:
snprintf’ output between 26 and 33 bytes into a destination of size 32
Fixes:
d5f7ebda3ec0 ("ac: add LLVM build functions for subgroup instrinsics")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bas Nieuwenhuizen [Tue, 5 Jun 2018 23:42:17 +0000 (01:42 +0200)]
amd/common: Fix number of coords for getlod.
The LLVM 6 code reduced it to a non-array call. We need to do that
with the new code too.
This fixes dEQP-VK.glsl.texture_functions.query.texturequerylod.*array* for radv.
Fixes:
a9a79934412 "amd/common: use the dimension-aware image intrinsics on LLVM 7+"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 7 Jun 2018 00:41:53 +0000 (10:41 +1000)]
features: add virgl to the GL features list
This hopefully adds virgl to the correct places and current statuses
of various extensions.
virgl of course relies on two external things
a) host driver that can support the features
b) up to date host virglrenderer library that can support the features.
This list will be maintained as latest (a) + (b) + mesa.
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Matt Turner [Thu, 7 Jun 2018 03:25:09 +0000 (20:25 -0700)]
meson: Add support for read-only text segment on x86
Port of
6dfc5e28f7d0 (configure.ac: Add support to enable read-only text
segment on x86.) to Meson.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Dylan Baker [Thu, 7 Jun 2018 17:48:38 +0000 (10:48 -0700)]
meson: work around gentoo applying -m32 to host compiler in cross builds
Gentoo's ebuild system always adds -m32 to the compiler for doing x86_64
-> x86 cross builds, while meson expects it not to do that. This
results in an x86 -> x86 cross build, and assembly gets disabled.
Fixes:
2d62fc06465281d3d45b8a7c7fd2b17ef718448c
("meson: disable x86 asm in fewer cases.")
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Wed, 6 Jun 2018 17:36:08 +0000 (10:36 -0700)]
i965/screen: Sanity check that all formats we advertise are useable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 5 Jun 2018 18:42:37 +0000 (11:42 -0700)]
i965/screen: Use RGBA non-sRGB formats for images
Not all of the MESA_FORMAT and ISL_FORMAT helpers we use can properly
handle RGBX formats. Also, we don't want to make decisions based on
those in the first place because we can't render to RGBA and we use the
non-sRGB version to determine whether or not to allow CCS_E.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 6 Jun 2018 17:24:01 +0000 (10:24 -0700)]
i965/screen: Return false for unsupported formats in query_modifiers
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 5 Jun 2018 18:13:40 +0000 (11:13 -0700)]
i965/screen: Refactor query_dma_buf_formats
This reworks it to work like query_dma_buf_modifiers and, in particular,
makes it more flexible so that we can disallow a non-static set of
formats.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 6 Jun 2018 16:59:25 +0000 (09:59 -0700)]
intel/isl: Add bounds-checking assertions for the format_info table
We follow the same convention as isl_format_get_layout in having two
assertions to ensure that only valid formats are passed in. We also
check against the array size of the table because some valid formats
such as CCS formats will may be past the end of the table. This fixes
some potential out-of-bounds array access even in valid cases.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 6 Jun 2018 16:54:17 +0000 (09:54 -0700)]
intel/isl: Add bounds-checking assertions in isl_format_get_layout
We add two assertions instead of one because the first assertion that
format != ISL_FORMAT_UNSUPPORTED is more descriptive and checks for a
real but unsupported enumerant while the second ensures that they don't
pass in garbage values. We also update some other helpers to use
isl_format_get_layout instead of using the table directly so that they
get bounds checking too.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Dylan Baker [Thu, 7 Jun 2018 15:38:07 +0000 (08:38 -0700)]
meson: Clarify why asm cannot be used in cross compile
This makes the reasoning for why a cross compile is not using asm
clearer (hopefully).
v2: - fix typos
Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Tue, 29 May 2018 14:24:53 +0000 (15:24 +0100)]
docs: talk about Wayland instead of libwayland
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Jason Ekstrand [Sat, 26 May 2018 19:08:22 +0000 (12:08 -0700)]
anv: Set fence/semaphore types to NONE in impl_cleanup
There were some places that were calling anv_semaphore_impl_cleanup and
neither deleting the semaphore nor setting the type back to NONE. Just
set it to NONE in impl_cleanup to avoid these issues.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106643
Fixes:
031f57eba "anv: Add a basic implementation of VK_KHX_external..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Plamena Manolova [Fri, 25 May 2018 21:49:47 +0000 (22:49 +0100)]
nir: Add global invocation id intrinsic.
Add the missing nir intrinsic for the gl_GlobalInvocationID
compute shader variable.
Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Eric Engestrom [Tue, 29 May 2018 15:19:59 +0000 (16:19 +0100)]
travis: bump libwayland to the first version with libwayland-egl
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Kenneth Graunke [Tue, 10 Apr 2018 08:27:56 +0000 (01:27 -0700)]
i965: Require softpin support for Cannonlake and later.
This isn't strictly necessary, but anyone running Cannonlake will
already have Kernel 4.5 or later, so there's no reason to support
the relocation model on Gen10+.
This will let us avoid dealing with them for new features.
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 10 Apr 2018 08:18:25 +0000 (01:18 -0700)]
i965: Allocate VMA in userspace for full-PPGTT systems.
This patch enables soft-pinning of all buffers, allowing us to skip
relocation processing entirely. All systems with full PPGTT and > 4GB
of VMA should gain these benefits. This should be most Gen8+.
Unfortunately, this excludes a few systems:
- Cherryview (only has 32-bit addressing, despite 48-bit pointers)
- Broadwell with a 32-bit kernel
- Anybody running pre-4.5 kernel.
We may enable it for Cherryview in the future, but it would require
some tweaks to the memory zone.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 31 May 2018 23:39:16 +0000 (16:39 -0700)]
intel/blorp: Emit VF cache invalidates for 48-bit bugs with softpin.
commit
92f01fc5f914fd500497d0c3aed75f3ac8dc054d made i965 start emitting
VF cache invalidates when the high bits of vertex buffers change. But
we were not tracking vertex buffers emitted by BLORP. This was papered
over by a mistake where I emitted VF cache invalidates all the time,
which Chris fixed in commit
3ac5fbadfd8644d30fce9ff267cb811ad157996a.
This patch adds a new hook which allows the driver to track addresses
and request a VF cache invalidate as appropriate.
v2: Make the driver do the PIPE_CONTROL so it can apply workarounds
(caught by Jason Ekstrand). Rebase on anv bug fix.
v3: Don't screw up the boolean (caught by Jason Ekstrand).
Fixes:
92f01fc5f914 ("i965: Emit VF cache invalidates for 48-bit addressing bugs with softpin.")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Timothy Arceri [Fri, 1 Jun 2018 05:37:28 +0000 (15:37 +1000)]
nir: add opt_if_loop_terminator()
This pass detects potential loop terminators and moves intructions
from the non breaking branch after the if-statement.
This enables both the new opt_if_simplification() pass and loop
unrolling to potentially progress further.
Unexpectedly this change speed up shader-db run times by ~3%
Ivy Bridge shader-db results (all changes in dolphin/ubershaders):
total instructions in shared programs:
9995662 ->
9995338 (-0.00%)
instructions in affected programs: 87845 -> 87521 (-0.37%)
helped: 27
HURT: 0
total cycles in shared programs:
230931495 ->
230925015 (-0.00%)
cycles in affected programs:
56391385 ->
56384905 (-0.01%)
helped: 27
HURT: 0
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Fri, 1 Jun 2018 05:37:27 +0000 (15:37 +1000)]
nir: move ends_in_break() helper to nir_loop_analyze.h
We will use the helper while simplifying potential loop terminators
in the following patch.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Timothy Arceri [Wed, 6 Jun 2018 23:49:37 +0000 (09:49 +1000)]
radv: fix Coverity no effect control flow issue
swizzle is unsigned so "desc->swizzle[c] < 0" is never true.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jason Ekstrand [Tue, 5 Jun 2018 00:27:53 +0000 (17:27 -0700)]
intel/blorp: Don't vertex fetch directly from clear values
On gen8+, we have to VF cache flush whenever a vertex binding aliases a
previous binding at the same index modulo 4GiB. We deal with this in
Vulkan by ensuring that vertex buffers and the dynamic state (from which
BLORP pulls its vertex buffers) are in the same 4GiB region of the
address space. That doesn't work if we're reading clear colors with the
VF unit. In order to work around this we switch to using MI commands to
copy the clear value into the vertex buffer we allocate for the normal
constant data.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Wed, 6 Jun 2018 11:57:18 +0000 (12:57 +0100)]
dri: add missing 16bits formats mapping
i965 advertises the 16-bit R and RG formats through
eglQueryDmaBufFormatsEXT but falls over when a client tries to use or
asks more information about such a format because
driImageFormatToGLFormat returns MESA_FORMAT_NONE.
Found by Eero Tamminen.
v2: Add G16R16 formats (Lionel)
v3: Fix G16R16 mapping to mesa format (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106642
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com> (v2)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Anholt [Fri, 30 Mar 2018 23:04:34 +0000 (16:04 -0700)]
nir: Look into uniform structs for samplers when counting num_textures.
mesa/st decides whether to update samplers after a program change based on
whether num_textures is nonzero. By not counting samplers in a uniform
struct, we would segfault in
KHR-GLES3.shaders.struct.uniform.sampler_vertex if it was run in the same
context after a non-vertex-shader-uniform testcase (as is the case during
a full conformance run).
v2: Implement using two separate pure functions instead of updating
pointers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Anholt [Wed, 2 May 2018 18:45:07 +0000 (11:45 -0700)]
v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.
This doesn't seem to have done anything to my test results. However,
given that we've still got a class of GPU hangs, following the workarounds
that the closed driver does so that we get the same command sequences
seems like a good idea.
Eric Anholt [Wed, 2 May 2018 21:17:07 +0000 (14:17 -0700)]
v3d: Enable the new NIR bitfield operation lowering paths.
These together get the GLSL 3.00 unorm/snorm pack functions and
MESA_shader_integer operations working.
v2: Fix commit message typo.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Tue, 8 May 2018 20:04:37 +0000 (13:04 -0700)]
nir: Add lowering for nir_op_bit_count.
This is basically the same as the GLSL lowering path.
v2: Fix typo in the link
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Tue, 8 May 2018 19:47:48 +0000 (12:47 -0700)]
nir: Add lowering for nir_op_bitfield_reverse.
This is basically the same as the GLSL lowering path.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Tue, 8 May 2018 18:24:40 +0000 (11:24 -0700)]
nir: Add an ALU lowering pass for mul_high.
This is based on the glsl/lower_instructions.cpp implementation, but
should be much more readable.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Fri, 4 May 2018 21:02:55 +0000 (14:02 -0700)]
nir: Add lowering for find_lsb.
There is a fairly simple relation to turn this into ufind_msb.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Fri, 4 May 2018 20:33:47 +0000 (13:33 -0700)]
nir: Add lowering for ifind_msb to ufind_msb.
ufind_msb is easily expressed in terms of clz, and we can reduce ifind_msb
to that.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Wed, 2 May 2018 20:02:21 +0000 (13:02 -0700)]
nir: Add lowering from ibitfield_extract/ubitfield_extract to shifts.
V3D doesn't have opcodes for ibfe/ubfe, so we need to lower similarly to
glsl/lower_instructions.cpp.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Anholt [Wed, 2 May 2018 21:13:23 +0000 (14:13 -0700)]
nir: Add lowering for bitfieldInsert without using bfi.
If you don't have HW to do bfi, then lowering bitfieldInsert to bfi makes
things harder than keeping the "bits" argument around.
This still uses bfm, but I've added the obvious lowering of bfm if you
need it.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Eric Engestrom [Tue, 29 May 2018 14:41:30 +0000 (15:41 +0100)]
docs: add note about moving to libwayland-egl in 18.2.0
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Daniel Stone <daniels@collabora.com>
Cc: Andres Gomez <agomez@igalia.com>
Cc: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Tue, 29 May 2018 14:41:29 +0000 (15:41 +0100)]
egl: remove wayland-egl now that we're using libwayland-egl
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Daniel Stone <daniels@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Tue, 29 May 2018 14:41:28 +0000 (15:41 +0100)]
egl: rewire the build systems to use libwayland-egl
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Daniel Stone <daniels@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
zhaowei yuan [Mon, 4 Jun 2018 21:33:59 +0000 (05:33 +0800)]
glsl: Take 'double' as reserved after GLSL ES 1.0
GLSL ES 1.0.17 specifies that "double" is a keyword reserved
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106823
Signed-off-by: zhaowei yuan <zhaowei.yuan@samsung.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Marek Olšák [Tue, 5 Jun 2018 00:39:07 +0000 (20:39 -0400)]
r300g/swtcl: make pipe_context uploaders use malloc'd memory as before
Discovered by Roland Scheidegger.
The resource_create code uses GPU memory for PIPE_BIND_CUSTOM, but
malloc'd memory otherwise. Vertex and index buffers should use malloc'd
memory.
Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 5 Jun 2018 21:33:12 +0000 (14:33 -0700)]
intel/eu: Use a struct copy instead of a memcpy
The memcpy had the wrong size and this was causing crashes on 32-bit
builds of the driver.
Fixes:
6a9525bf6729a8 "intel/eu: Switch to a logical state stack"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106830
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Philip Rebohle [Mon, 28 May 2018 12:10:41 +0000 (14:10 +0200)]
radv: Use correct color format for fast clears
Using the image format is incorrect when the view has a different
format than the image. Instead, the view format needs to be used.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106687
Eric Anholt [Tue, 5 Jun 2018 15:50:55 +0000 (08:50 -0700)]
v3d: Be more explicit about include directory from our generated code.
You'd need src/broadcom/cle/ in the -I previously, for srcdir != builddir.
nir was fine at that, but automake didn't have it.
Bugzilla: https://github.com/anholt/mesa/issues/104
Bas Nieuwenhuizen [Mon, 4 Jun 2018 22:52:34 +0000 (00:52 +0200)]
radv: Do not hardcode fast clear formats.
except for the odd one out.
This should support many more formats.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Scott D Phillips [Tue, 5 Jun 2018 16:33:49 +0000 (09:33 -0700)]
intel/tools: add intel_sanitize_gpu to EXTRA_DIST
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106778
Fixes:
cc41603d6d ("intel/tools: new intel_sanitize_gpu tool")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Scott D Phillips [Tue, 5 Jun 2018 16:29:43 +0000 (09:29 -0700)]
util/tests/vma: Fix warning c++11-narrowing
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106801
Fixes:
943fecc569 ("util: Add a randomized test for the virtual memory allocator")
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Scott D Phillips [Fri, 1 Jun 2018 23:26:56 +0000 (16:26 -0700)]
util: tests: vma test depends on C++11 support
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106776
Fixes:
943fecc569 ("util: Add a randomized test for the virtual memory allocator")
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Michel Dänzer [Fri, 1 Jun 2018 16:59:36 +0000 (18:59 +0200)]
glx: Fix number of property values to read in glXImportContextEXT
We were trying to read twice as many as the X server sent us, which
upset XCB:
[xcb] Too much data requested from _XRead
[xcb] This is most likely caused by a broken X extension library
[xcb] Aborting, sorry about that.
glx-free-context: ../../src/xcb_io.c:732: _XRead: Assertion `!xcb_xlib_too_much_data_requested' failed.
Fixing this takes 3 GLX piglit tests from crash to pass.
Fixes:
085216295033 "glx: Be more tolerant in glXImportContext (v2)"
Reviewed-by: Adam Jackson <ajax@redhat.com>
Eric Engestrom [Mon, 4 Jun 2018 11:08:15 +0000 (12:08 +0100)]
configure: radv depends on mako
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106784
Fixes:
17201a2eb0b1b85387136 "radv: port to using updated anv
entrypoint/extension generator."
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Tue, 5 Jun 2018 10:42:02 +0000 (11:42 +0100)]
travis: use correct form for array options
I'd like to eventually drop support for the confusing "an array of
a single empty string is meant to be interpreted as an empty array", so
let's start by not using it anymore.
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Lionel Landwerlin [Mon, 4 Jun 2018 08:54:29 +0000 (09:54 +0100)]
anv: intel: add softpin flag on imported BOs
Looks like we forgot to update this bit of the driver for softpin.
Fixes:
4affeba1e9eb42 ("anv: Soft-pin everything else")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Mon, 4 Jun 2018 17:06:30 +0000 (18:06 +0100)]
autotools: add missing android file to package
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=106779
Fixes:
ff904978a1d299a36b587 "gallium/util: Android backtrace support"
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 4 Jun 2018 10:26:10 +0000 (11:26 +0100)]
meson: fix platforms check for `-D egl=true`
Fixes:
0ed6a87a106b6e2266e0 "meson: fix platforms=[]"
Reported-by: Christoph Haag <haagch@frickel.club>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Mathias Fröhlich [Fri, 1 Jun 2018 17:10:08 +0000 (19:10 +0200)]
mesa: Make sure that imm draws are flushed before other draws execute.
The recent patch
mesa: Remove FLUSH_VERTICES from VAO state changes.
Pending draw calls on immediate mode or display list calls do
not depend on changes of the VAO state. So, remove calls to
FLUSH_VERTICES and flag _NEW_ARRAY as appropriate.
uncovered a problem that non immediate mode draw calls do only
flush outstanding immediate mode draws if FLUSH_UPDATE_CURRENT
is set in ctx->Driver.NeedFlush.
In that case, due to the sequence of _mesa_set_draw_vao commands
we could end up with the VAO from the FLUSH_VERTICES call set
into gl_context::Array._DrawVAO when the array draw is executed.
So the change pulls FLUSH_CURRENT out of _mesa_validate_* calls
into the array draw calls being validated.
The change introduces a new macro FLUSH_FOR_DRAW beside FLUSH_VERTICES
and FLUSH_CURRENT that flushes on changed current attributes as well
as on outstanding immediate mode draw calls. Use FLUSH_FOR_DRAW
in the non immediate mode draw code paths.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106594
Signed-off-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
gurchetansingh@chromium.org [Mon, 4 Jun 2018 17:25:20 +0000 (10:25 -0700)]
virgl: use bits in caps set v2
Let's add another field to caps v2, that can help report boolean
values.
Suggested-by: Gert Wollny <gert.wollny@collabora.com>
Suggested-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
gurchetansingh@chromium.org [Mon, 4 Jun 2018 16:03:37 +0000 (09:03 -0700)]
virgl: add shader offset alignment to to v2 caps struct
This is the SSBO analogue to fe0647. User supplied data must
be a multiple of GL_SHADER_STORAGE_BUFFER_OFFSET_ALIGNMENT.
This fixes 44 GLES31 tests on airlied@'s GLES31 sketch branches with
Nvidia hardware, but this patch standalone can applied to master. The
alignment restriction on Nvidia is 32, hence the default value.
Example tests:
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.0
dEQP-GLES31.functional.ssbo.layout.multi_basic_types.single_buffer.std430
v2: Move to a better place in case statement
v3: Rebase
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Thu, 5 Apr 2018 08:37:31 +0000 (01:37 -0700)]
i965: Prepare batchbuffer module for softpin support.
If EXEC_OBJECT_PINNED is set, we don't want to emit any relocations.
We simply want to add the BO to the validation list, and possibly mark
it as writeable. The new brw_use_pinned_bo() interface does just that.
To avoid having to make every caller consider both the relocation and
softpin cases, we make emit_reloc() call brw_use_pinned_bo() when given
a softpinned buffer.
We also can't grow buffers that are softpinned - the mechanism places a
larger BO at the same offset as the original, which requires moving BOs
around in the VMA. With softpin, we only allocate enough VMA for the
original size of the BO.
v2: Assert that BOs aren't pinned if the kernel says we should move them
(feedback from Chris Wilson)
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Kenneth Graunke [Tue, 10 Apr 2018 07:39:40 +0000 (00:39 -0700)]
i965: Add virtual memory allocator infrastructure to brw_bufmgr.
This introduces a new fast virtual memory allocator integrated with our
BO cache bucketing. For larger objects, it falls back to the simple
free-list allocator (util_vma).
This puts the allocators in place but doesn't enable softpin yet.
v2:
(feedback from Chris Wilson)
- Check (bo->kflags & EXEC_OBJECT_PINNED) instead of a global flag
- Avoid vma_free(0ull) on the err_free path.
- Only enable if the kernel says we have full PPGTT support
- Make bucketing allocators more resistant to failing to grow arrays
(feedback from Scott Phillips)
- Don't use node after popping it from the list.
- Avoid undefined behavior in canonicalization by reusing new helper
- Comment updates
(feedback from myself)
- Avoid __vma_alloc vs. vma_alloc by making a zero_high_bits helper
to return a non-canonical address with the high bits zeroed.
- Don't shadow loop variable 'i' when destroying things (ugly; worked)
v3:
- Replace zero_high_bits with new common gen_48b_address helper.
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Fri, 1 Jun 2018 00:00:35 +0000 (17:00 -0700)]
i965: Disable internal CCS for shadows of multi-sampled windows
If window system supports Y-tiling but not CCS_E, we currently create an
internal CCS for any window system buffers and then resolve right before
handing it off to X or Wayland. In the case of the single-sampled
shadow of a multi-sampled window system buffer, this is pointless
because the only thing we do with it is use it as a MSAA resolve target
so we do MSAA resolve -> CCS resolve -> hand to the window system.
Instead, just disable CCS for the shadow and then the MSAA resolve will
write uncompressed directly into it. If the window system supports
CCS_E, we will still use CCS_E, we just won't do internal CCS.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 31 May 2018 18:42:17 +0000 (11:42 -0700)]
i965/miptree: Rename a parameter to create_for_dri_image
Instead of having it be a general "is this a winsys image" boolean, make
it more specific to the actual purpose.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 29 May 2018 21:37:35 +0000 (14:37 -0700)]
intel/eu: Switch to a logical state stack
Instead of the state stack that's based on copying a dummy instruction
around, we start using a logical stack of brw_insn_states. This uses a
bit less memory and is way less conceptually bogus.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 29 May 2018 22:28:36 +0000 (15:28 -0700)]
intel/eu: Set flag [sub]register number differently for 3src
Prior to gen8, the flag [sub]register number is in a different spot on
3src instructions than on other instructions. Starting with Broadwell,
they made it consistent. This commit fixes bugs that occur when a
conditional modifier gets propagated into a 3src instruction such as a
MAD.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 29 May 2018 20:45:57 +0000 (13:45 -0700)]
intel/eu: Copy fields manually in brw_next_insn
Instead of doing a memcpy, this moves us to start with a blank
instruction (memset to zero) and copy the fields over one at a time.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Tue, 29 May 2018 21:50:46 +0000 (14:50 -0700)]
intel/eu: Add some brw_get_default_ helpers
This is much cleaner than everything that wants a default value poking
at the bits of p->current directly.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jose Fonseca [Thu, 24 May 2018 15:51:38 +0000 (16:51 +0100)]
trace: Fix parsing of recent traces.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Thu, 24 May 2018 15:50:58 +0000 (16:50 +0100)]
trace: Fix trace_context_transfer_unmap methods.
The emitted buffer_subdata/texture_subdata call didn't match the
respective signatures.
v2: Actually emit buffer_subdata call.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>