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Aaron Ballman [Wed, 2 May 2018 18:57:14 +0000 (18:57 +0000)]
Move the TestPlugin project into the Tests folder in CMake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331387
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Simon Pilgrim [Wed, 2 May 2018 18:48:23 +0000 (18:48 +0000)]
[X86] Split WriteShuffle/WriteVarShuffle + WriteBlend/WriteVarBlend into XMM and YMM/ZMM scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331386
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Martin Storsjo [Wed, 2 May 2018 18:24:37 +0000 (18:24 +0000)]
[COFF, ARM64] Hook up a few remaining relocations
Differential Revision: https://reviews.llvm.org/D46355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331384
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Farhana Aleen [Wed, 2 May 2018 18:16:39 +0000 (18:16 +0000)]
[AMDGPU] A trivial fix for a buildbot failure caused by "commit
224a839fcbbead221f872cd32a1dd0c308d37299".
Author: FarhanaAleen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331383
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Daniel Sanders [Wed, 2 May 2018 17:59:16 +0000 (17:59 +0000)]
[reassociate] Fix excessive revisits when processing long chains of reassociatable instructions.
Summary:
Some of our internal testing detected a major compile time regression which I've
tracked down to:
r278938 - Revert "Reassociate: Reprocess RedoInsts after each inst".
It appears that processing long chains of reassociatable instructions causes
non-linear (potentially exponential) growth in the number of times an
instruction is revisited. For example, the included test revisits instructions
220 times in a 20-instruction test.
It appears that r278938 reversed the order instructions were visited and that
this is preventing scheduled revisits from being cancelled as a result of
visiting the instructions naturally during normal processing. However, simply
reversing the order also harmed the generated code. Upon closer inspection, it
was discovered that revisits occurred in the opposite order to the first pass
(Thanks to escha for spotting that).
This patch makes the revisit order consistent with the first pass which allows
more revisits to be cancelled. This does appear to have a small impact on the
generated code in few cases but it significantly reduces compile-time.
After this patch, our internal test that was most affected by the regression
dropped from ~2 million revisits to ~4k resulting in Reassociate having 0.46%
of the runtime it had before (99.54% improvement).
Here's the summaries reported by lnt for the LLVM test-suite with --benchmarking-only:
| metric | geomean before patch | geomean after patch | delta |
| ----- | ----- | ----- | ----- |
| compile time | 0.1956 | 0.1261 | -35.54% |
| execution time | 0.3240 | 0.3237 | - |
| code size | 7365.4459 | 7365.6079 | - |
The results have a few wins and losses on compile-time, mostly in the +/- 2.5% range. There was one outlier though:
| Performance Regressions - compile_time | Δ | Previous | Current |
| MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 9.82% | 2.0473 | 2.2483 |
Reviewers: javed.absar, dberlin
Reviewed By: dberlin
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331381
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Simon Pilgrim [Wed, 2 May 2018 17:58:50 +0000 (17:58 +0000)]
[X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes with more common default values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331380
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Krzysztof Parzyszek [Wed, 2 May 2018 17:20:22 +0000 (17:20 +0000)]
Add assertion to padding size calculation, NFC
The size of an object cannot be less than the emitted size of all the
contained elements. This would cause an overflow in padding size
calculation. Add an assert to catch this.
Patch by Suyog Sarda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331376
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Farhana Aleen [Wed, 2 May 2018 16:48:52 +0000 (16:48 +0000)]
Revert "[AMDGPU] performAddCombine should run after DAG is legalized."
This reverts commit
6b97d2995566b4dddd6bf0d75579ff44501d4494.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331371
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Simon Pilgrim [Wed, 2 May 2018 16:25:41 +0000 (16:25 +0000)]
[X86] Convert most remaining XOP uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331369
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Farhana Aleen [Wed, 2 May 2018 16:24:10 +0000 (16:24 +0000)]
[AMDGPU] performAddCombine should run after DAG is legalized.
Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization
in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with
illegal types.
Author: FarhanaAleen
Reviewed By: rampitec
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D46337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331368
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Simon Pilgrim [Wed, 2 May 2018 16:16:24 +0000 (16:16 +0000)]
Fix line-endings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331367
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Clement Courbet [Wed, 2 May 2018 14:35:48 +0000 (14:35 +0000)]
Re-land rL331357 "[X86] Fix scheduling info for VMPSADBWYrmi."
Without the rebase mess.
https://reviews.llvm.org/D46356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331362
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Simon Pilgrim [Wed, 2 May 2018 14:25:32 +0000 (14:25 +0000)]
[X86] Cleanup WriteFMul scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331360
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Simon Pilgrim [Wed, 2 May 2018 14:22:30 +0000 (14:22 +0000)]
Fix '32-bit shift implicitly converted to 64 bits' warning by using APInt::setBit instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331359
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Clement Courbet [Wed, 2 May 2018 13:54:38 +0000 (13:54 +0000)]
Revert rL331355 "[X86] Fix scheduling info for VMPSADBWYrmi."
It contains unrelated changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331357
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Clement Courbet [Wed, 2 May 2018 13:46:14 +0000 (13:46 +0000)]
[X86] Fix scheduling info for (V?)SQRTPDm on silvermont.
https://reviews.llvm.org/D46356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331356
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Clement Courbet [Wed, 2 May 2018 13:40:48 +0000 (13:40 +0000)]
[X86] Fix scheduling info for VMPSADBWYrmi.
https://reviews.llvm.org/D46356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331355
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Clement Courbet [Wed, 2 May 2018 13:37:28 +0000 (13:37 +0000)]
[MIPS] Fix DIV/DIVU scheduling classes.
https://reviews.llvm.org/D46356.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331354
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Simon Pilgrim [Wed, 2 May 2018 13:32:56 +0000 (13:32 +0000)]
[X86] Convert most remaining AVX512 uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
We've dealt with the majority already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331353
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Sander de Smalen [Wed, 2 May 2018 13:32:39 +0000 (13:32 +0000)]
[AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D46270
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331352
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Simon Tatham [Wed, 2 May 2018 13:17:26 +0000 (13:17 +0000)]
[TableGen] Don't quote variable name when printing !foreach.
An input !foreach expression such as !foreach(a, lst, !add(a, 1))
would be re-emitted by llvm-tblgen -print-records with the first
argument in quotes, giving !foreach("a", lst, !add(a, 1)), which isn't
valid TableGen input syntax.
Reviewers: nhaehnle
Reviewed By: nhaehnle
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46352
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331351
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Sander de Smalen [Wed, 2 May 2018 13:00:30 +0000 (13:00 +0000)]
[AArch64][SVE] Asm: Support for scatter ST1 store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46248
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331349
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Simon Dardis [Wed, 2 May 2018 12:35:29 +0000 (12:35 +0000)]
Revert "[mips] Correct the predicates of sign extension instructions"
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.
This reverts r331346.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331348
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Simon Pilgrim [Wed, 2 May 2018 12:27:54 +0000 (12:27 +0000)]
[X86] Convert most remaining uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
We've dealt with the majority already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331347
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Simon Dardis [Wed, 2 May 2018 12:25:33 +0000 (12:25 +0000)]
[mips] Correct the predicates of sign extension instructions
And eliminate the duplication of those instructions for microMIPS32r6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331346
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Sander de Smalen [Wed, 2 May 2018 11:48:49 +0000 (11:48 +0000)]
[AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D46269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331343
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Florian Hahn [Wed, 2 May 2018 10:53:04 +0000 (10:53 +0000)]
[LoopInterchange] Update some loops to use range base for loops (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331342
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Simon Dardis [Wed, 2 May 2018 09:55:49 +0000 (09:55 +0000)]
[mips] Correct the predicates for shifts.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D46123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331341
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Simon Pilgrim [Wed, 2 May 2018 09:18:49 +0000 (09:18 +0000)]
[X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.
Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331340
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Sander de Smalen [Wed, 2 May 2018 08:49:08 +0000 (08:49 +0000)]
[AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331339
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Piotr Padlewski [Wed, 2 May 2018 08:22:07 +0000 (08:22 +0000)]
Mark invariant.group.barrier as inaccessiblememonly
It turned out that readonly argmemonly is not enough.
store 42, %p
%b = barrier(%p)
store 43, %b
the first store is dead, but because barrier was marked as
reading argument memory, it was considered alive. With
inaccessiblememonly it doesn't read the argument, but
it also can't be CSEd.
based on: https://reviews.llvm.org/D32006
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331338
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Bjorn Pettersson [Wed, 2 May 2018 06:56:38 +0000 (06:56 +0000)]
[SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)
Summary:
This is a follow up to rL331182. A PHI node can be split up into
several MIR PHI nodes when being selected. When there is a
dbg.value intrinsic that uses the result of such a PHI node we
need to select several DBG_VALUE instructions, with fragment
expressions, in order to do a correct selection.
Reviewers: rnk, aprantl, vsk
Reviewed By: vsk
Subscribers: mattd, llvm-commits, JDevlieghere, aprantl, gbedwell, rnk
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D46329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331337
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Dean Michael Berris [Wed, 2 May 2018 00:43:17 +0000 (00:43 +0000)]
[XRay][tools] Rename llvm-xray filenames from .cc -> .cpp (NFC)
Summary:
This brings the filenames in accordance to the style guide and LLVM
conventions for C++ filenames.
As suggested by rnk@ in D46068.
Reviewers: rnk
Subscribers: mgorny, mgrang, llvm-commits
Differential Revision: https://reviews.llvm.org/D46301
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331321
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Sam Clegg [Wed, 2 May 2018 00:10:28 +0000 (00:10 +0000)]
Fix release build breakage
This function was added in rL331220 but wasn't
testing in release configurations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331320
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Sam Clegg [Tue, 1 May 2018 23:28:27 +0000 (23:28 +0000)]
[WebAssembly] Fix debug printing of symbol types
The Info.Kind field is a uint8_t which the OS was
trying to print as an ascii char.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331317
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Matt Davis [Tue, 1 May 2018 23:04:01 +0000 (23:04 +0000)]
[llvm-mca] Lift the logic of the RetireControlUnit from the Dispatch translation unit into its own translation unit. NFC
The logic remains the same. Eventually, I see the RCU acting as its own separate stage in the instruction pipeline.
Differential Revision: https://reviews.llvm.org/D46331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331316
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Farhana Aleen [Tue, 1 May 2018 21:41:12 +0000 (21:41 +0000)]
[AMDGPU] Support horizontal vectorization.
Author: FarhanaAleen
Reviewed By: rampitec, arsenm
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D46213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331313
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David Bolvansky [Tue, 1 May 2018 21:35:32 +0000 (21:35 +0000)]
[CFLGraph][NFC] Simplify/reorder switch in visitConstantExpr
Reviewers: hfinkel, efriedma, spatel, dsanders, Danil, rjmccall
Reviewed By: rjmccall
Subscribers: dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D46259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331312
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Sanjay Patel [Tue, 1 May 2018 21:02:09 +0000 (21:02 +0000)]
[AggressiveInstCombine] convert a chain of 'or-shift' bits into masked compare
and (or (lshr X, C), ...), 1 --> (X & C') != 0
I initially thought about implementing the minimal pattern in instcombine as mentioned here:
https://bugs.llvm.org/show_bug.cgi?id=37098#c6
...but we need to do better to catch the more general sequence from the motivating test
(more than 2 bits in the compare). And a test-suite run with statistics showed that this
pattern only happened 2 times currently. It would potentially happen more often if
reassociation worked better (D45842), but it's probably still not too frequent?
This is small enough that I didn't see a need to create a whole new class/file within
AggressiveInstCombine. There are likely other relatively small matchers like what was
discussed in D44266 that would slide under foldUnusualPatterns() (name suggestions welcome).
We could potentially also consolidate matchers for ctpop, bswap, etc under here.
Differential Revision: https://reviews.llvm.org/D45986
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331311
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Sanjay Patel [Tue, 1 May 2018 20:55:03 +0000 (20:55 +0000)]
[AggressiveInstCombine] add more bitfield test patterns; NFC
Add another baseline for D45986 and a pattern that won't be
matched with that patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331309
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Sanjay Patel [Tue, 1 May 2018 20:53:44 +0000 (20:53 +0000)]
[PhaseOrdering] add tests for bittest patterns from bitfields; NFC
As mentioned in D45986, there's a potential ordering dependency
between instcombine and aggressive-instcombine for detecting these,
so I'm adding a few tests to confirm that the expected folds occur
using -O3 (because aggressive-instcombine only runs at -O3 currently).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331308
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Jessica Paquette [Tue, 1 May 2018 20:49:42 +0000 (20:49 +0000)]
Create a MachineBasicBlock for created IR-level BasicBlock
While running the lit tests for the most recent version of D45916
(https://reviews.llvm.org/D45916), I found that a couple tests for this pass
suddenly started segfaulting. Since the outliner wasn't actually doing anything
to the code in either of these tests I got curious.
I found that the pass doesn’t completely create the machine-level constructs
necessary to actually add a MachineFunction and MachineBasicBlock to the
module. This patch adds in those missing bits. After this, adding the
outliner before this pass won’t cause it to segfault.
You can recreate this behaviour by adding the MachineOutliner directly before
the pass and having it return false immediately.
https://reviews.llvm.org/D46330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331307
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Eli Friedman [Tue, 1 May 2018 20:00:14 +0000 (20:00 +0000)]
[AArch64] Add more tests for 64-bit immediate lowering.
This adds a some more tests, and adds some notes to tests which are using
a suboptimal lowering.
The constants with suboptimal lowerings seem to be relatively rare in
practice, but it might be a fun project to work on improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331304
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Vedant Kumar [Tue, 1 May 2018 19:51:15 +0000 (19:51 +0000)]
[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)
The logic for this combine is almost identical to the logic for a
(sext (sextload x)) combine.
This commit factors out the logic so it can be shared by both combines,
and corrects the SDLoc assigned in the zext version of the combine.
Prior to this patch, for the given test case, we would apply the
location associated with the udiv instruction to instructions which
perform the load.
Part of: llvm.org/PR37262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331303
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Vedant Kumar [Tue, 1 May 2018 19:51:15 +0000 (19:51 +0000)]
[DAGCombiner] Fix SDLoc in a (sext (sextload x)) combine (3/N)
Prior to this patch, for the given test case, we would apply the
location associated with the sdiv instruction to instructions which
perform the load.
Part of: llvm.org/PR37262.
Differential Revision: https://reviews.llvm.org/D46222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331302
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Vedant Kumar [Tue, 1 May 2018 19:29:15 +0000 (19:29 +0000)]
[DAGCombiner] Change the SDLoc on split extloads (2/N)
In DAGCombiner, we try to simplify this pattern:
([s|z]ext (load ...))
Conceptually, a new extload which is created while splitting the load
should have the same debug location as the load.
Making this change affects the IROrder of the new load, causing some
test case churn.
In practice, the new location is never different from the location of
the [s|z]ext, at least not during check-llvm or a stage2 build.
Part of: llvm.org/PR37262
Differential Revision: https://reviews.llvm.org/D46156
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331301
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Vedant Kumar [Tue, 1 May 2018 19:26:15 +0000 (19:26 +0000)]
[DAGCombiner] Set the right SDLoc on a newly-created zextload (1/N)
Setting the right SDLoc on a newly-created zextload fixes a line table
bug which resulted in non-linear stepping behavior.
Several backend tests contained CHECK lines which relied on the IROrder
inherited from the wrong SDLoc. This patch breaks that dependence where
feasbile and regenerates test cases where not.
In some cases, changing a node's IROrder may alter register allocation
and spill behavior. This can affect performance. I have chosen not to
prevent this by applying a "known good" IROrder to SDLocs, as this may
hide a more general bug in the scheduler, or cause regressions on other
test inputs.
rdar://
33755881, Part of: llvm.org/PR37262
Differential Revision: https://reviews.llvm.org/D45995
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331300
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Konstantin Zhuravlyov [Tue, 1 May 2018 18:47:48 +0000 (18:47 +0000)]
AMDGPU: Remove remnants of gfx901 (it was deprecated some time ago)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331298
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Roman Lebedev [Tue, 1 May 2018 18:39:31 +0000 (18:39 +0000)]
[X86][AMD][Bulldozer] Fix Bulldozer Model 2 detection.
Summary:
I have discovered an issue by accident.
```
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 8
On-line CPU(s) list: 0-7
Thread(s) per core: 2
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: AuthenticAMD
CPU family: 21
Model: 2
Model name: AMD FX(tm)-8350 Eight-Core Processor
Stepping: 0
CPU MHz: 3584.018
CPU max MHz: 4000.0000
CPU min MHz: 1400.0000
BogoMIPS: 8027.22
Virtualization: AMD-V
L1d cache: 16K
L1i cache: 64K
L2 cache: 2048K
L3 cache: 8192K
NUMA node0 CPU(s): 0-7
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr tbm topoext perfctr_core perfctr_nb cpb hw_pstate vmmcall bmi1 arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold
```
So this is model-2 bulldozer AMD CPU.
GCC agrees:
```
$ echo | gcc -E - -march=native -###
<...>
/usr/lib/gcc/x86_64-linux-gnu/7/cc1 -E -quiet -imultiarch x86_64-linux-gnu - "-march=bdver2" -mmmx -mno-3dnow -msse -msse2 -msse3 -mssse3 -msse4a -mcx16 -msahf -mno-movbe -maes -mno-sha -mpclmul -mpopcnt -mabm -mlwp -mfma -mfma4 -mxop -mbmi -mno-sgx -mno-bmi2 -mtbm -mavx -mno-avx2 -msse4.2 -msse4.1 -mlzcnt -mno-rtm -mno-hle -mno-rdrnd -mf16c -mno-fsgsbase -mno-rdseed -mprfchw -mno-adx -mfxsr -mxsave -mno-xsaveopt -mno-avx512f -mno-avx512er -mno-avx512cd -mno-avx512pf -mno-prefetchwt1 -mno-clflushopt -mno-xsavec -mno-xsaves -mno-avx512dq -mno-avx512bw -mno-avx512vl -mno-avx512ifma -mno-avx512vbmi -mno-avx5124fmaps -mno-avx5124vnniw -mno-clwb -mno-mwaitx -mno-clzero -mno-pku -mno-rdpid --param "l1-cache-size=16" --param "l1-cache-line-size=64" --param "l2-cache-size=2048" "-mtune=bdver2"
<...>
```
But clang does not: (look for `bdver1`)
```
$ echo | clang -E - -march=native -###
clang version 7.0.0- (trunk)
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir: /usr/local/bin
"/usr/lib/llvm-7/bin/clang" "-cc1" "-triple" "x86_64-pc-linux-gnu" "-E" "-disable-free" "-disable-llvm-verifier" "-discard-value-names" "-main-file-name" "-" "-mrelocation-model" "static" "-mthread-model" "posix" "-mdisable-fp-elim" "-fmath-errno" "-masm-verbose" "-mconstructor-aliases" "-munwind-tables" "-fuse-init-array" "-target-cpu" "bdver1" "-target-feature" "+sse2" "-target-feature" "+cx16" "-target-feature" "+sahf" "-target-feature" "+tbm" "-target-feature" "-avx512ifma" "-target-feature" "-sha" "-target-feature" "-gfni" "-target-feature" "+fma4" "-target-feature" "-vpclmulqdq" "-target-feature" "+prfchw" "-target-feature" "-bmi2" "-target-feature" "-cldemote" "-target-feature" "-fsgsbase" "-target-feature" "-xsavec" "-target-feature" "+popcnt" "-target-feature" "+aes" "-target-feature" "-avx512bitalg" "-target-feature" "-xsaves" "-target-feature" "-avx512er" "-target-feature" "-avx512vnni" "-target-feature" "-avx512vpopcntdq" "-target-feature" "-clwb" "-target-feature" "-avx512f" "-target-feature" "-clzero" "-target-feature" "-pku" "-target-feature" "+mmx" "-target-feature" "+lwp" "-target-feature" "-rdpid" "-target-feature" "+xop" "-target-feature" "-rdseed" "-target-feature" "-waitpkg" "-target-feature" "-ibt" "-target-feature" "+sse4a" "-target-feature" "-avx512bw" "-target-feature" "-clflushopt" "-target-feature" "+xsave" "-target-feature" "-avx512vbmi2" "-target-feature" "-avx512vl" "-target-feature" "-avx512cd" "-target-feature" "+avx" "-target-feature" "-vaes" "-target-feature" "-rtm" "-target-feature" "+fma" "-target-feature" "+bmi" "-target-feature" "-rdrnd" "-target-feature" "-mwaitx" "-target-feature" "+sse4.1" "-target-feature" "+sse4.2" "-target-feature" "-avx2" "-target-feature" "-wbnoinvd" "-target-feature" "+sse" "-target-feature" "+lzcnt" "-target-feature" "+pclmul" "-target-feature" "-prefetchwt1" "-target-feature" "+f16c" "-target-feature" "+ssse3" "-target-feature" "-sgx" "-target-feature" "-shstk" "-target-feature" "+cmov" "-target-feature" "-avx512vbmi" "-target-feature" "-movbe" "-target-feature" "-xsaveopt" "-target-feature" "-avx512dq" "-target-feature" "-adx" "-target-feature" "-avx512pf" "-target-feature" "+sse3" "-dwarf-column-info" "-debugger-tuning=gdb" "-resource-dir" "/usr/lib/llvm-7/lib/clang/7.0.0" "-internal-isystem" "/usr/local/include" "-internal-isystem" "/usr/lib/llvm-7/lib/clang/7.0.0/include" "-internal-externc-isystem" "/usr/include/x86_64-linux-gnu" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-fdebug-compilation-dir" "/build/llvm-build-Clang-release" "-ferror-limit" "19" "-fmessage-length" "271" "-fobjc-runtime=gcc" "-fdiagnostics-show-option" "-fcolor-diagnostics" "-o" "-" "-x" "c" "-"
```
So clang, unlike gcc, considers this to be `bdver1`.
After some digging, i've come across `getAMDProcessorTypeAndSubtype()` in `Host.cpp`.
I have added the following debug printf after the call to that function in `sys::getHostCPUName()`:
```
errs() << "Family " << Family << " Model " << Model << " Type " << Type "\n";
```
Which produced:
```
Family 21 Model 2 Type 5
```
Which matches the `lscpu` output.
As it was pointed in the review by @craig.topper:
>>! In D46314#
1084123, @craig.topper wrote:
> I dont' think this is right. Here is what I found on wikipedia. https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures.
>
> AMD Bulldozer Family 15h - the successor of 10h/K10. Bulldozer is designed for processors in the 10 to 220W category, implementing XOP, FMA4 and CVT16 instruction sets. Orochi was the first design which implemented it. For Bulldozer, CPUID model numbers are 00h and 01h.
> AMD Piledriver Family 15h (2nd-gen) - successor to Bulldozer. CPUID model numbers are 02h (earliest "Vishera" Piledrivers) and 10h-1Fh.
> AMD Steamroller Family 15h (3rd-gen) - third-generation Bulldozer derived core. CPUID model numbers are 30h-3Fh.
> AMD Excavator Family 15h (4th-gen) - fourth-generation Bulldozer derived core. CPUID model numbers are 60h-6Fh, later updated revisions have model numbers 70h-7Fh.
>
>
> So there's a weird exception where model 2 should go with 0x10-0x1f.
Though It does not help that the code can't be tested at the moment.
With this logical change, the `bdver2` is properly detected.
```
$ echo | /build/llvm-build-Clang-release/bin/clang -E - -march=native -###
clang version 7.0.0 (trunk 331249) (llvm/trunk 331256)
Target: x86_64-unknown-linux-gnu
Thread model: posix
InstalledDir: /build/llvm-build-Clang-release/bin
"/build/llvm-build-Clang-release/bin/clang-7" "-cc1" "-triple" "x86_64-unknown-linux-gnu" "-E" "-disable-free" "-main-file-name" "-" "-mrelocation-model" "static" "-mthread-model" "posix" "-mdisable-fp-elim" "-fmath-errno" "-masm-verbose" "-mconstructor-aliases" "-munwind-tables" "-fuse-init-array" "-target-cpu" "bdver2" "-target-feature" "+sse2" "-target-feature" "+cx16" "-target-feature" "+sahf" "-target-feature" "+tbm" "-target-feature" "-avx512ifma" "-target-feature" "-sha" "-target-feature" "-gfni" "-target-feature" "+fma4" "-target-feature" "-vpclmulqdq" "-target-feature" "+prfchw" "-target-feature" "-bmi2" "-target-feature" "-cldemote" "-target-feature" "-fsgsbase" "-target-feature" "-xsavec" "-target-feature" "+popcnt" "-target-feature" "+aes" "-target-feature" "-avx512bitalg" "-target-feature" "-movdiri" "-target-feature" "-xsaves" "-target-feature" "-avx512er" "-target-feature" "-avx512vnni" "-target-feature" "-avx512vpopcntdq" "-target-feature" "-clwb" "-target-feature" "-avx512f" "-target-feature" "-clzero" "-target-feature" "-pku" "-target-feature" "+mmx" "-target-feature" "+lwp" "-target-feature" "-rdpid" "-target-feature" "+xop" "-target-feature" "-rdseed" "-target-feature" "-waitpkg" "-target-feature" "-movdir64b" "-target-feature" "-ibt" "-target-feature" "+sse4a" "-target-feature" "-avx512bw" "-target-feature" "-clflushopt" "-target-feature" "+xsave" "-target-feature" "-avx512vbmi2" "-target-feature" "-avx512vl" "-target-feature" "-avx512cd" "-target-feature" "+avx" "-target-feature" "-vaes" "-target-feature" "-rtm" "-target-feature" "+fma" "-target-feature" "+bmi" "-target-feature" "-rdrnd" "-target-feature" "-mwaitx" "-target-feature" "+sse4.1" "-target-feature" "+sse4.2" "-target-feature" "-avx2" "-target-feature" "-wbnoinvd" "-target-feature" "+sse" "-target-feature" "+lzcnt" "-target-feature" "+pclmul" "-target-feature" "-prefetchwt1" "-target-feature" "+f16c" "-target-feature" "+ssse3" "-target-feature" "-sgx" "-target-feature" "-shstk" "-target-feature" "+cmov" "-target-feature" "-avx512vbmi" "-target-feature" "-movbe" "-target-feature" "-xsaveopt" "-target-feature" "-avx512dq" "-target-feature" "-adx" "-target-feature" "-avx512pf" "-target-feature" "+sse3" "-dwarf-column-info" "-debugger-tuning=gdb" "-resource-dir" "/build/llvm-build-Clang-release/lib/clang/7.0.0" "-internal-isystem" "/usr/local/include" "-internal-isystem" "/build/llvm-build-Clang-release/lib/clang/7.0.0/include" "-internal-externc-isystem" "/usr/include/x86_64-linux-gnu" "-internal-externc-isystem" "/include" "-internal-externc-isystem" "/usr/include" "-fdebug-compilation-dir" "/build/llvm-build-Clang-release" "-ferror-limit" "19" "-fmessage-length" "271" "-fobjc-runtime=gcc" "-fdiagnostics-show-option" "-fcolor-diagnostics" "-o" "-" "-x" "c" "-"
```
Reviewers: craig.topper, GBuella, RKSimon, asbirlea, echristo, bkramer, spatel, andreadb, GGanesh
Reviewed By: craig.topper
Subscribers: sdardis, aprantl, arichardson, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D46314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331294
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 1 May 2018 18:22:53 +0000 (18:22 +0000)]
[X86] Split WriteFMul/WriteFDiv into XMM and YMM/ZMM scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331293
91177308-0d34-0410-b5e6-
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David Blaikie [Tue, 1 May 2018 18:08:45 +0000 (18:08 +0000)]
llvm-symbolizer: Handle function definitions nested within other functions
LLVM always puts function definition DIEs at the top level, but under
some circumstances GCC does not (at least in this case with member
functions of a function-local type).
To ensure that doesn't appear as though the local type's member function
is unduly inlined within the outer function - ensure the inline
discovery DIE parent walk stops at the first DW_TAG_subprogram.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331291
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 1 May 2018 18:06:07 +0000 (18:06 +0000)]
[X86] Split WriteFRcp/WriteFRsqrt/WriteFSqrt into XMM and YMM/ZMM scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331290
91177308-0d34-0410-b5e6-
96231b3b80d8
Wei Mi [Tue, 1 May 2018 17:19:25 +0000 (17:19 +0000)]
Use no-op opt run to eliminate the difference in bb pred comment, per chandler's suggestion. It is better than using sed on portability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331286
91177308-0d34-0410-b5e6-
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Konstantin Zhuravlyov [Tue, 1 May 2018 17:05:44 +0000 (17:05 +0000)]
AMDGPU: Add missing gfx904 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331284
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 1 May 2018 16:50:16 +0000 (16:50 +0000)]
[X86] Split WriteFCmp into XMM and YMM/ZMM scheduler classes
Removes more WriteFCmp InstRW overrides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331283
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Tue, 1 May 2018 16:46:05 +0000 (16:46 +0000)]
Support: assume `std::is_final` with MSVC
According to MSDN, Visual Studio 2015 included support for
std::is_final. Additionally, a bug in the Visual Studio compiler results
in the incorrect definition of __cplusplus. Due to the conditions in the
else case not holding either, we end up with no definition of
LLVM_IS_FINAL when building with MSVC. This has not yet been a problem
with LLVM/clang, however, the uses of LLVM_IS_FINAL is more prevalent in
swift, which uses the ADT library and causes issues when building lldb
with Visual Studio.
Workaround the issue by always assuming that the definition of
std::is_final is available with Visual Studio. Since we currently
require VS 2015+ for building LLVM, this condition should always hold
for the users in LLVM/clang (and for swift).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331282
91177308-0d34-0410-b5e6-
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Daniel Neilson [Tue, 1 May 2018 16:40:45 +0000 (16:40 +0000)]
[LV] Move test/Transforms/LoopVectorize/pr23997.ll
Summary:
This fixes a build break with r331269.
test/Transforms/LoopVectorize/pr23997.ll
should be in:
test/Transforms/LoopVectorize/X86/pr23997.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331281
91177308-0d34-0410-b5e6-
96231b3b80d8
Wei Mi [Tue, 1 May 2018 16:37:27 +0000 (16:37 +0000)]
Fix the sed command in test which doesn't work well on BSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331280
91177308-0d34-0410-b5e6-
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Sam Clegg [Tue, 1 May 2018 16:35:16 +0000 (16:35 +0000)]
[WebAssembly] llvm-readobj: display symbols names in relocations
Differential Revision: https://reviews.llvm.org/D46296
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331279
91177308-0d34-0410-b5e6-
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Konstantin Zhuravlyov [Tue, 1 May 2018 16:34:29 +0000 (16:34 +0000)]
AMDGPU/NFC: Use enum values for first/last machs instead of numbers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331278
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 1 May 2018 16:13:42 +0000 (16:13 +0000)]
[X86] Split WriteFAdd into XMM and YMM/ZMM scheduler classes
Removes more WriteFAdd InstRW overrides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331276
91177308-0d34-0410-b5e6-
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Adrian Prantl [Tue, 1 May 2018 16:10:38 +0000 (16:10 +0000)]
Remove @brief commands from doxygen comments, too.
This is a follow-up to r331272.
We've been running doxygen with the autobrief option for a couple of
years now. This makes the \brief markers into our comments
redundant. Since they are a visual distraction and we don't want to
encourage more \brief markers in new code either, this patch removes
them all.
Patch produced by
for i in $(git grep -l '\@brief'); do perl -pi -e 's/\@brief //g' $i & done
https://reviews.llvm.org/D46290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331275
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Matthew Simpson [Tue, 1 May 2018 15:59:26 +0000 (15:59 +0000)]
[SLP] Add additional test for transposable binary operations with reuse
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331274
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 1 May 2018 15:57:17 +0000 (15:57 +0000)]
[X86] Convert all uses of WriteFAdd to X86SchedWriteWidths.
In preparation of splitting WriteFAdd by vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331273
91177308-0d34-0410-b5e6-
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Adrian Prantl [Tue, 1 May 2018 15:54:18 +0000 (15:54 +0000)]
Remove \brief commands from doxygen comments.
We've been running doxygen with the autobrief option for a couple of
years now. This makes the \brief markers into our comments
redundant. Since they are a visual distraction and we don't want to
encourage more \brief markers in new code either, this patch removes
them all.
Patch produced by
for i in $(git grep -l '\\brief'); do perl -pi -e 's/\\brief //g' $i & done
Differential Revision: https://reviews.llvm.org/D46290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331272
91177308-0d34-0410-b5e6-
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Sanjay Patel [Tue, 1 May 2018 15:43:36 +0000 (15:43 +0000)]
[DAG] add test to show FMF mismatch between IR and DAG; NFC
D45710 proposes to change this, but we have no test coverage
for the first step in this process.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331271
91177308-0d34-0410-b5e6-
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Daniel Neilson [Tue, 1 May 2018 15:35:08 +0000 (15:35 +0000)]
[LV] Preserve inbounds on created GEPs
Summary:
This is a fix for PR23997.
The loop vectorizer is not preserving the inbounds property of GEPs that it creates.
This is inhibiting some optimizations. This patch preserves the inbounds property in
the case where a load/store is being fed by an inbounds GEP.
Reviewers: mkuper, javed.absar, hsaito
Reviewed By: hsaito
Subscribers: dcaballe, hsaito, llvm-commits
Differential Revision: https://reviews.llvm.org/D46191
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331269
91177308-0d34-0410-b5e6-
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Wei Mi [Tue, 1 May 2018 14:47:24 +0000 (14:47 +0000)]
Fix the issue that ComputeValueKnownInPredecessors only handles the case when
phi is on lhs of a comparison op.
For the following testcase,
L1:
%t0 = add i32 %m, 7
%t3 = icmp eq i32* %t2, null
br i1 %t3, label %L3, label %L2
L2:
%t4 = load i32, i32* %t2, align 4
br label %L3
L3:
%t5 = phi i32 [ %t0, %L1 ], [ %t4, %L2 ]
%t6 = icmp eq i32 %t0, %t5
br i1 %t6, label %L4, label %L5
We know if we go through the path L1 --> L3, %t6 should always be true. However
currently, if the rhs of the eq comparison is phi, JumpThreading fails to
evaluate %t6 to true. And we know that Instcombine cannot guarantee always
canonicalizing phi to the left hand side of the comparison operation according
to the operand priority comparison mechanism in instcombine. The patch handles
the case when rhs of the comparison op is a phi.
Differential Revision: https://reviews.llvm.org/D46275
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331266
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Omer Paparo Bivas [Tue, 1 May 2018 14:27:10 +0000 (14:27 +0000)]
[InstCombine] new testcases for OverflowingBinaryOperators and PossiblyExactOperators transformations; NFC
instcombine should transform the relevant cases if the OverflowingBinaryOperator/PossiblyExactOperator can be proven to be safe.
Change-Id: I7aec62a31a894e465e00eb06aed80c3ea0c9dd45
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331265
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 1 May 2018 14:25:01 +0000 (14:25 +0000)]
[X86] Split WriteFShuffle into XMM and YMM/ZMM scheduler classes
Removes more WriteFShuffle InstRW overrides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331264
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 1 May 2018 14:14:42 +0000 (14:14 +0000)]
[X86] Convert all uses of WriteFShuffle to X86SchedWriteWidths.
In preparation of splitting WriteFShuffle by vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331262
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Sander de Smalen [Tue, 1 May 2018 13:36:03 +0000 (13:36 +0000)]
[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46121
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331260
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Simon Dardis [Tue, 1 May 2018 13:06:49 +0000 (13:06 +0000)]
Reland r331175: "[mips] Fix the predicates of jump and branch and link instructions"
The previous version of this patch restricted the 'jal' instruction to MIPS and
microMIPSr3. microMIPS32r6 does not have this instruction and instead uses jal
as an alias for balc.
Original commit message:
> Reviewers: smaksimovic, atanasyan, abeserminji
>
> Differential Revision: https://reviews.llvm.org/D46114
>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331259
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Simon Pilgrim [Tue, 1 May 2018 12:39:17 +0000 (12:39 +0000)]
[X86] Split WriteVecLogic into XMM and YMM/ZMM scheduler classes
This removes all the WriteVecLogic InstRW overrides.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331258
91177308-0d34-0410-b5e6-
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Omer Paparo Bivas [Tue, 1 May 2018 12:25:46 +0000 (12:25 +0000)]
[InstCombine] Adjusting bswap pattern matching to hold for And/Shift mixed case
Differential Revision: https://reviews.llvm.org/D45731
Change-Id: I85d4226504e954933c41598327c91b2d08192a9d
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331257
91177308-0d34-0410-b5e6-
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Simon Pilgrim [Tue, 1 May 2018 12:15:29 +0000 (12:15 +0000)]
[X86] Convert all uses of WriteFLogic/WriteVecLogic to X86SchedWriteWidths.
In preparation of splitting WriteVecLogic by vector width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331256
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Florian Hahn [Tue, 1 May 2018 11:18:31 +0000 (11:18 +0000)]
[MC] Add llvm_unreachable to toString to fix compile time warning.
Without this change, GCC 7 raises the warning below:
control reaches end of non-void function
Reviewers: sbc100, andreadb
Reviewed By: andreadb
Differential Revision: https://reviews.llvm.org/D46304
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331255
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Simon Pilgrim [Tue, 1 May 2018 11:05:42 +0000 (11:05 +0000)]
[X86] Tag PSLLDQ/PSRLDQ as WriteShuffle scheduler classes instead of shifts.
Although they are encoded similar to bit shifts, the byte shifts behave like shuffles from a scheduling point of view.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331253
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Andrea Di Biagio [Tue, 1 May 2018 10:29:38 +0000 (10:29 +0000)]
[X86] Correct spill slot size.
This patch fixes a bug introduced by revision 330778 (originally reviewed at:
https://reviews.llvm.org/D44782), where function isFrameLoadOpcode returned
the wrong number of bytes read for opcodes VMOVSSrm and VMOVSDrm.
This corrects that mistake, and extends the regression test to catch cases where
the dead stores should be removed.
Patch by Jeremy Morse.
Differential Revision: https://reviews.llvm.org/D46256
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331252
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Gabor Buella [Tue, 1 May 2018 10:21:10 +0000 (10:21 +0000)]
NFC, Avoid a warning in WasmObjectWriter
The warning was (introduced in r331220):
lib/MC/WasmObjectWriter.cpp:51:1: warning: control reaches end of non-void function [-Wreturn-type]
}
^
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331251
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Gabor Buella [Tue, 1 May 2018 10:01:16 +0000 (10:01 +0000)]
[X86] movdiri and movdir64b instructions
Reviewers: spatel, craig.topper, RKSimon
Reviewed By: craig.topper, RKSimon
Differential Revision: https://reviews.llvm.org/D45983
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331248
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Chandler Carruth [Tue, 1 May 2018 09:54:39 +0000 (09:54 +0000)]
[PM/LoopUnswitch] Remove the last manual domtree update code from loop
unswitch and replace it with the amazingly simple update API code.
This addresses piles of FIXMEs around the update logic here and makes
everything substantially simpler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331247
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Chandler Carruth [Tue, 1 May 2018 09:42:09 +0000 (09:42 +0000)]
[PM/LoopUnswitch] Add back a successor set that was removed based on
code review.
It turns out this *is* necessary, and I read the comment on the API
correctly the first time. ;]
The `applyUpdates` routine requires that updates are "balanced". This is
in order to cleanly handle cycles like inserting, removing, nad then
re-inserting the same edge. This precludes inserting the same edge
multiple times in a row as handling that would cause the insertion logic
to become *ordered* instead of *unordered* (which is what the API
provides).
It happens that in this specific case nothing (other than an assert and
contract violation) goes wrong because we're never inserting and
removing the same edge. The implementation *happens* to do the right
thing to eliminate redundant insertions in that case.
But the requirement is there and there is an assert to catch it.
Somehow, after the code review I never did another asserts-clang build
testing loop-unswich for a long time. As a consequence, I didn't notice
this despite a bunch of testing going on, but it shows up immediately
with an asserts build of clang itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331246
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Craig Topper [Tue, 1 May 2018 04:42:00 +0000 (04:42 +0000)]
[X86] Remove 'opaque ptr' from the intel syntax parser and printer.
Previously for instructions like fxsave we would print "opaque ptr" as part of the memory operand. Now we print nothing.
We also no longer accept "opaque ptr" in the parser. We still accept any size to be specified for these instructions, but we may want to consider only parsing when no explicit size is specified. This what gas does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331243
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Eric Christopher [Tue, 1 May 2018 00:10:13 +0000 (00:10 +0000)]
Temporarily revert "[DEBUG] Initial adaptation of NVPTX target for debug info emission."
This appears to have some issues associated with the file directive output
causing multiple global symbols with the name "file" to be emitted into a
startup section. I'm investigating more specific causes and working with the
original author.
This reverts commit r330271.
Also Revert "[DEBUGINFO, NVPTX] Add the test for the debug info of the local"
This reverts commit r330592 and the follow up of 330779 as the testcase is dependent upon r330271.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331237
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Sanjay Patel [Mon, 30 Apr 2018 21:28:18 +0000 (21:28 +0000)]
[InstCombine] fix test to restore intent
This test had values that differed in only in capitalization,
and that causes problems for the auto-generating check line
script. So I changed that in rL331226, but I accidentally
forgot to change a subsequent use of a param.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331228
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Sanjay Patel [Mon, 30 Apr 2018 21:03:36 +0000 (21:03 +0000)]
[InstCombine] add tests, update checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331226
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Nico Weber [Mon, 30 Apr 2018 20:19:48 +0000 (20:19 +0000)]
Stop setting LLVM_ON_WIN32 in config.h and llvm-config.h.
See thread "Replacing LLVM_ON_WIN32 with just _WIN32" on llvm-dev and cfe-dev.
I replaced all uses of LLVM_ON_WIN32 with _WIN32 in r331127 (llvm),
r331069 (clang), r329697 (lldb), r329696 (lld), r329696 (clang-tools-extra).
If your out-of-tree program used LLVM_ON_WIN32, just use _WIN32 instead, which
is set at exactly the same time to exactly the same value.
https://reviews.llvm.org/D46264
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331224
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Alina Sbirlea [Mon, 30 Apr 2018 20:11:13 +0000 (20:11 +0000)]
[ModRefInfo] Rename local variable IsMustAlias to avoid shadowing MustAlias enum entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331222
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Florian Hahn [Mon, 30 Apr 2018 20:10:53 +0000 (20:10 +0000)]
[SimplifyCFG] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.
Reviewers: aprantl, vsk, hans, danielcdh
Reviewed By: hans
Differential Revision: https://reviews.llvm.org/D46252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331221
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Sam Clegg [Mon, 30 Apr 2018 19:40:57 +0000 (19:40 +0000)]
[WebAssembly] MC: Improve debug output
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331220
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Krzysztof Parzyszek [Mon, 30 Apr 2018 19:38:47 +0000 (19:38 +0000)]
[LivePhysRegs] Remove registers clobbered by regmasks from the live set
Dead defs were being removed from the live set (in stepForward), but
registers clobbered by regmasks weren't (more specifically, they were
actually removed by removeRegsInMask, but then they were added back in).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331219
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Nirav Dave [Mon, 30 Apr 2018 19:22:40 +0000 (19:22 +0000)]
[MC] Change AsmParser to leverage Assembler during evaluation
Teach AsmParser to check with Assembler for when evaluating constant
expressions. This improves the handing of preprocessor expressions
that must be resolved at parse time. This idiom can be found as
assembling-time assertion checks in source-level assemblers. Note that
this relies on the MCStreamer to keep sufficient tabs on Section /
Fragment information which the MCAsmStreamer does not. As a result the
textual output may fail where the equivalent object generation would
pass. This can most easily be resolved by folding the MCAsmStreamer
and MCObjectStreamer together which is planned for in a separate
patch.
Currently, this feature is only enabled for assembly input, keeping IR
compilation consistent between assembly and object generation.
Reviewers: echristo, rnk, probinson, espindola, peter.smith
Reviewed By: peter.smith
Subscribers: eraman, peter.smith, arichardson, jyknight, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331218
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Florian Hahn [Mon, 30 Apr 2018 19:19:36 +0000 (19:19 +0000)]
[LoopSimplify] Use BB::instructionsWithoutDebug to skip DbgInfo (NFC).
This patch updates some code responsible the skip debug info to use
BasicBlock::instructionsWithoutDebug. I think this makes things slightly
simpler and more direct.
Reviewers: aprantl, vsk, chandlerc
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D46253
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331217
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Matt Arsenault [Mon, 30 Apr 2018 19:08:16 +0000 (19:08 +0000)]
AMDGPU: Add Vega12 and Vega20
Changes by
Matt Arsenault
Konstantin Zhuravlyov
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331215
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Roman Tereshin [Mon, 30 Apr 2018 18:58:57 +0000 (18:58 +0000)]
[MIR] Reset unique MBB numbering in MachineFunction::reset()
No need to waste space nor number MBBs differently if MF gets recreated.
Reviewers: qcolombet, stoklund, t.p.northover, bogner, javed.absar
Reviewed By: qcolombet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331213
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Sanjay Patel [Mon, 30 Apr 2018 18:20:33 +0000 (18:20 +0000)]
[DAGCombiner] rename function attribute for disabling ftrunc transform
This is the matching name change for the Clang patch at:
D46236
rL331209
Differential Revision: https://reviews.llvm.org/D46237
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331210
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Simon Pilgrim [Mon, 30 Apr 2018 18:18:38 +0000 (18:18 +0000)]
[X86] Introduce X86SchedWriteWidths schedule wrapper for different vector widths.
We need to split most of the scheduler classes by vector width to remove more of the InstRW overrides, this patch should make this easier/tidier by allowing us to pass the X86SchedWriteWidths wrapper to multi-width multiclasses and then split as required.
I've included fields for Scl (scalar float/double), MMX (MMX integer), XMM, YMM and ZMM widths. These fields mostly share the same classes but it should give us the flexibility that we may need in the future.
This patch has replaced a set of example SSE/AVX512 instruction cases but isn't exhaustive as it gets very noisy before we really need the functionality.
Differential Revision: https://reviews.llvm.org/D46266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331208
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Roman Lebedev [Mon, 30 Apr 2018 17:59:33 +0000 (17:59 +0000)]
[InstCombine] Unfold masked merge with constant mask
Summary:
As discussed in D45733, we want to do this in InstCombine.
https://rise4fun.com/Alive/LGk
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: chandlerc, xbolva00, llvm-commits
Differential Revision: https://reviews.llvm.org/D45867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331205
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Roman Lebedev [Mon, 30 Apr 2018 17:59:26 +0000 (17:59 +0000)]
[InstCombine][NFC] Add tests for unfolding masked merge with constant mask
Summary: As discussed in D45733, we want to do this in InstCombine.
Differential Revision: https://reviews.llvm.org/D45866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331204
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