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Simon Pilgrim [Mon, 23 Oct 2017 14:19:46 +0000 (14:19 +0000)]
[X86][AVX2] Regenerate AVX2 intrinsics tests on 32 + 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316326
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Simon Pilgrim [Mon, 23 Oct 2017 14:17:59 +0000 (14:17 +0000)]
[X86][AVX] Regenerate AVX intrinsics tests on 32 + 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316325
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Simon Pilgrim [Mon, 23 Oct 2017 14:15:24 +0000 (14:15 +0000)]
[X86][F16C] Regenerate F16C schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316324
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Artur Gainullin [Mon, 23 Oct 2017 13:25:49 +0000 (13:25 +0000)]
Test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316322
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George Rimar [Mon, 23 Oct 2017 11:24:14 +0000 (11:24 +0000)]
[llvm-dwarfdump] - Teach tool about few GNU call_sites constants.
This teaches tool about following consants:
DW_TAG_GNU_call_site,
DW_TAG_GNU_call_site_parameter,
DW_AT_GNU_call_site_value,
DW_AT_GNU_all_call_sites.
Constants documented here: https://sourceware.org/elfutils/DwarfExtensions
Differential revision: https://reviews.llvm.org/D39119
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316321
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Ayman Musa [Mon, 23 Oct 2017 10:24:19 +0000 (10:24 +0000)]
[X86] Add test for opportunity to use bzhi X86 instruction instead of load+and instructions.
Transformation uploaded for CR in https://reviews.llvm.org/D34141.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316320
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Andrew V. Tischenko [Mon, 23 Oct 2017 09:36:33 +0000 (09:36 +0000)]
Fix for Bug 30718 - Failure to disassemble certain MOV with rex.R. The issue was in illegal segment register index.
Differential Revision: https://reviews.llvm.org/D38786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316319
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Martin Storsjo [Mon, 23 Oct 2017 09:08:13 +0000 (09:08 +0000)]
[COFF] Improve the check for functions that should get an extra underscore
This fixes exporting functions starting with an underscore, and
fully decorated fastcall/vectorcall functions.
Tests will be added in the lld repo.
Differential Revision: https://reviews.llvm.org/D39168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316316
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Haojian Wu [Mon, 23 Oct 2017 09:02:59 +0000 (09:02 +0000)]
Fix a -Wpedantic warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316315
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Sam Parker [Mon, 23 Oct 2017 08:05:14 +0000 (08:05 +0000)]
[ARM] Allow unrolling of multi-block loops.
Before, loop unrolling was only enabled for loops with a single
block. This restriction has been removed and replaced by:
- allow a maximum of two exiting blocks,
- a four basic block limit for cores with a branch predictor.
Differential Revision: https://reviews.llvm.org/D38952
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316313
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Craig Topper [Mon, 23 Oct 2017 03:42:35 +0000 (03:42 +0000)]
[X86] Update a doxygen comment in the disassembler tablegen code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316309
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Craig Topper [Mon, 23 Oct 2017 02:26:24 +0000 (02:26 +0000)]
[X86] Fix disassembly of EVEX rounding control and SAE instructions.
Fixes PR31955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316308
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Saleem Abdulrasool [Sun, 22 Oct 2017 20:51:25 +0000 (20:51 +0000)]
ExecutionEngine: make COFF Thumb2 assertions non-tautological
The overflow detection assertions were tautological due to truncation.
Adjust them to no longer be tautological.
Patch by Alex Langford!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316303
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Yichao Yu [Sun, 22 Oct 2017 20:28:17 +0000 (20:28 +0000)]
Fix invalid ptrtoint in InstCombine
Summary:
It's unclear if this is the only thing we can do but at least this is consistent with the check
of address space agreement in `isBitCastable`.
The code is used at least in both instcombine and jumpthreading though
I could only find a way to trigger the invalid cast in instcombine.
Reviewers: loladiro, sanjoy, majnemer
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D34335
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316302
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Benjamin Kramer [Sun, 22 Oct 2017 20:16:28 +0000 (20:16 +0000)]
Create fewer copies of StringMaps. No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316301
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Benjamin Kramer [Sun, 22 Oct 2017 19:16:31 +0000 (19:16 +0000)]
[X86] Add missing override. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316299
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Sanjay Patel [Sun, 22 Oct 2017 19:10:07 +0000 (19:10 +0000)]
[SimplifyCFG] delay switch condition forwarding to -latesimplifycfg
As discussed in D39011:
https://reviews.llvm.org/D39011
...replacing constants with a variable is inverting the transform done
by other IR passes, so we definitely don't want to do this early.
In fact, it's questionable whether this transform belongs in SimplifyCFG
at all. I'll look at moving this to codegen as a follow-up step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316298
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Fangrui Song [Sun, 22 Oct 2017 18:43:23 +0000 (18:43 +0000)]
[utils] Support -mtriple=powerpc64
Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported.
Subscribers: nemanjai
Differential Revision: https://reviews.llvm.org/D39164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316297
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Simon Pilgrim [Sun, 22 Oct 2017 18:38:57 +0000 (18:38 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316296
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Marina Yatsina [Sun, 22 Oct 2017 17:59:38 +0000 (17:59 +0000)]
Add logic to greedy reg alloc to avoid bad eviction chains
This fixes bugzilla 26810
https://bugs.llvm.org/show_bug.cgi?id=26810
This is intended to prevent sequences like:
movl %ebp, 8(%esp) # 4-byte Spill
movl %ecx, %ebp
movl %ebx, %ecx
movl %edi, %ebx
movl %edx, %edi
cltd
idivl %esi
movl %edi, %edx
movl %ebx, %edi
movl %ecx, %ebx
movl %ebp, %ecx
movl 16(%esp), %ebp # 4 - byte Reload
Such sequences are created in 2 scenarios:
Scenario #1:
vreg0 is evicted from physreg0 by vreg1
Evictee vreg0 is intended for region splitting with split candidate physreg0 (the reg vreg0 was evicted from)
Region splitting creates a local interval because of interference with the evictor vreg1 (normally region spliiting creates 2 interval, the "by reg" and "by stack" intervals. Local interval created when interference occurs.)
one of the split intervals ends up evicting vreg2 from physreg1
Evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills
Scenario #2
vreg0 is evicted from physreg0 by vreg1
vreg2 is evicted from physreg2 by vreg3 etc
Evictee vreg0 is intended for region splitting with split candidate physreg1
Region splitting creates a local interval because of interference with the evictor vreg1
one of the split intervals ends up evicting back original evictor vreg1 from physreg0 (the reg vreg0 was evicted from)
Another evictee vreg2 is intended for region splitting with split candidate physreg1
one of the split intervals ends up evicting vreg3 from physreg2 etc.. until someone spills
As compile time was a concern, I've added a flag to control weather we do cost calculations for local intervals we expect to be created (it's on by default for X86 target, off for the rest).
Differential Revision: https://reviews.llvm.org/D35816
Change-Id: Id9411ff7bbb845463d289ba2ae97737a1ee7cc39
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316295
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Craig Topper [Sun, 22 Oct 2017 17:22:29 +0000 (17:22 +0000)]
[X86] More correctly support LIG and WIG for EVEX instructions in the disassembler tables.
This is similar to how we generate the VEX tables.
More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316294
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Sanjay Patel [Sun, 22 Oct 2017 16:51:03 +0000 (16:51 +0000)]
[SimplifyCFG] try harder to forward switch condition to phi (PR34471)
The missed canonicalization/optimization in the motivating test from PR34471 leads to very different codegen:
int switcher(int x) {
switch(x) {
case 17: return 17;
case 19: return 19;
case 42: return 42;
default: break;
}
return 0;
}
int comparator(int x) {
if (x == 17) return 17;
if (x == 19) return 19;
if (x == 42) return 42;
return 0;
}
For the first example, we use a bit-test optimization to avoid a series of compare-and-branch:
https://godbolt.org/g/BivDsw
Differential Revision: https://reviews.llvm.org/D39011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316293
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Momchil Velikov [Sun, 22 Oct 2017 11:56:35 +0000 (11:56 +0000)]
[ARM] Dynamic stack alignment for 16-bit Thumb
This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When
targeting processors, which support only the 16-bit Thumb instruction set
the compiler ignores the alignment attributes of automatic variables and may
silently generate incorrect code.
Differential revision: https://reviews.llvm.org/D38143
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316289
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Guy Blank [Sun, 22 Oct 2017 11:43:08 +0000 (11:43 +0000)]
[X86] Add a pass to convert instruction chains between domains.
The pass scans the function to find instruction chains that define
registers in the same domain (closures).
It then calculates the cost of converting the closure to another domain.
If found profitable, the instructions are converted to instructions in
the other domain and the register classes are changed accordingly.
This commit adds the pass infrastructure and a simple conversion from
the GPR domain to the Mask domain.
Differential Revision:
https://reviews.llvm.org/D37251
Change-Id: Ic2cf1d76598110401168326d411128ae2580a604
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316288
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Nitesh Jain [Sun, 22 Oct 2017 09:47:41 +0000 (09:47 +0000)]
[mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld.
Reviewers: sdardis
Subscribers: jaydeep, bhushan, llvm-commits
Differential Revision: https://reviews.llvm.org/D38314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316287
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Craig Topper [Sun, 22 Oct 2017 06:18:26 +0000 (06:18 +0000)]
[X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored.
Fixes PR11304.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316285
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Craig Topper [Sun, 22 Oct 2017 06:18:23 +0000 (06:18 +0000)]
[X86] Add VEX_WIG to applicable AVX512 instructions.
This should be NFC. Will be used in future patches to fix disassembler bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316284
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Craig Topper [Sun, 22 Oct 2017 06:18:20 +0000 (06:18 +0000)]
[X86] Add VEX_WIG to VROUNDSSrr/VROUNDSSrm/VROUNDSDrr/VROUNDSDrm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316283
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Craig Topper [Sun, 22 Oct 2017 04:32:30 +0000 (04:32 +0000)]
[X86] Don't allow gather/scatter to disassembler if memory operand does not use a SIB byte.
Fixes PR34998.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316282
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Simon Pilgrim [Sat, 21 Oct 2017 20:40:49 +0000 (20:40 +0000)]
Strip trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316277
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Aaron Ballman [Sat, 21 Oct 2017 20:38:15 +0000 (20:38 +0000)]
Reverting r316270 due to failing build bots.
http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/12899
http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/7951
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316276
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Simon Pilgrim [Sat, 21 Oct 2017 20:19:48 +0000 (20:19 +0000)]
[X86][SSE] Add extractps/pextrd equivalence to domain tables
Differential Revision: https://reviews.llvm.org/D39135
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316274
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Craig Topper [Sat, 21 Oct 2017 20:03:20 +0000 (20:03 +0000)]
[X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register.
This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB.
This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type.
This fixes PR32807.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316273
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Simon Pilgrim [Sat, 21 Oct 2017 17:23:04 +0000 (17:23 +0000)]
Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316271
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Fangrui Song [Sat, 21 Oct 2017 16:59:40 +0000 (16:59 +0000)]
[PPC CodeGen] Fix the bitreverse.i64 intrinsic.
Summary: The two 32-bit words were swapped.
Subscribers: nemanjai, kbarton
Differential Revision: https://reviews.llvm.org/D38705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316270
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Craig Topper [Sat, 21 Oct 2017 16:35:41 +0000 (16:35 +0000)]
[ValueTracking] Remove unnecessary temporary APInt from computeNumSignBitsVectorConstant.
We can just use getNumSignBits instead of inverting negative numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316266
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Craig Topper [Sat, 21 Oct 2017 16:35:39 +0000 (16:35 +0000)]
[ValueTracking] Simplify the known bits code for constant vectors a little.
Neither of these cases really require a temporary APInt outside the loop. For the ConstantDataSequential case the APInt will never be larger than 64-bits so its fine to just call getElementAsAPInt. For ConstantVector we can get the APInt by reference and only make a copy where the inversion is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316265
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Simon Pilgrim [Sat, 21 Oct 2017 14:35:09 +0000 (14:35 +0000)]
[X86][SSE] Add missing extractps scheduling test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316262
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David Green [Sat, 21 Oct 2017 13:58:37 +0000 (13:58 +0000)]
[LoopInterchange] Fix phi node ordering miscompile.
The way that splitInnerLoopHeader splits blocks requires that
the induction PHI will be the first PHI in the inner loop
header. This makes sure that is actually the case when there
are both IV and reduction phis.
Differential Revision: https://reviews.llvm.org/D38682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316261
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Florian Hahn [Sat, 21 Oct 2017 05:37:10 +0000 (05:37 +0000)]
[SelectionDAG] Use dyn_cast without cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316258
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Florian Hahn [Sat, 21 Oct 2017 04:57:03 +0000 (04:57 +0000)]
[SelectionDAG] Use isa to silence unused variable warning (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316257
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Craig Topper [Sat, 21 Oct 2017 03:22:13 +0000 (03:22 +0000)]
[SelectionDAG] Don't subject ConstantSDNodes to the depth limit in computeKnownBits and ComputeNumSignBits.
We don't need to do any additional recursion, we just need to analyze the APInt stored in the node. This matches what the ValueTracking versions do for IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316256
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Craig Topper [Sat, 21 Oct 2017 02:27:19 +0000 (02:27 +0000)]
[SelectionDAG] Don't subject ISD:Constant to the depth limit in TargetLowering::SimplifyDemandedBits.
Summary:
We shouldn't recurse any further but it doesn't mean we shouldn't be able to give the known bits for a constant. The caller would probably like that we always return the right answer for a constant RHS. This matches what InstCombine does in this case.
I don't have a test case because this showed up while trying to revive D31724.
Reviewers: RKSimon, spatel
Reviewed By: RKSimon
Subscribers: arsenm, llvm-commits
Differential Revision: https://reviews.llvm.org/D38967
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316255
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Craig Topper [Sat, 21 Oct 2017 02:26:00 +0000 (02:26 +0000)]
[X86] Do not generate __multi3 for mul i128 on X86
Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function. This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test.
Patch by Riyaz V Puthiyapurayil
Reviewers: craig.topper, schweitz
Reviewed By: craig.topper, schweitz
Subscribers: RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D38668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316254
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Eugene Zelenko [Sat, 21 Oct 2017 00:57:46 +0000 (00:57 +0000)]
[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316253
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Krzysztof Parzyszek [Fri, 20 Oct 2017 22:08:40 +0000 (22:08 +0000)]
[Packetizer] Add function to check for aliasing between instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316243
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Sanjay Patel [Fri, 20 Oct 2017 21:55:23 +0000 (21:55 +0000)]
[utils, x86] add regex for retl/retq to reduce duplicated FileChecking (PR35003)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316242
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Eugene Zelenko [Fri, 20 Oct 2017 21:47:29 +0000 (21:47 +0000)]
[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316241
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Sam Clegg [Fri, 20 Oct 2017 21:28:38 +0000 (21:28 +0000)]
[WebAssembly] MC: Fix crash when -g specified.
At this point we don't output any debug sections or thier
relocations.
Differential Revision: https://reviews.llvm.org/D39076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316240
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Daniel Sanders [Fri, 20 Oct 2017 20:55:29 +0000 (20:55 +0000)]
[globalisel][tablegen] Fix small spelling nits. NFC
ComplexRendererFn -> ComplexRendererFns
Corrected a couple lingering references to tied operands that were missed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316237
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Krzysztof Parzyszek [Fri, 20 Oct 2017 20:24:44 +0000 (20:24 +0000)]
[Hexagon] Report error instead of crashing on wrong inline-asm constraints
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316236
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Peter Collingbourne [Fri, 20 Oct 2017 19:48:26 +0000 (19:48 +0000)]
COFF: Add type server pdb files to linkrepro tar file.
Differential Revision: https://reviews.llvm.org/D38977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316233
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Krzysztof Parzyszek [Fri, 20 Oct 2017 19:33:12 +0000 (19:33 +0000)]
[Hexagon] Reorganize and update instruction patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316228
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Simon Pilgrim [Fri, 20 Oct 2017 19:29:01 +0000 (19:29 +0000)]
[X86][SSE] Add missing _mm_extract_ps fast-isel test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316226
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Sanjay Patel [Fri, 20 Oct 2017 18:35:32 +0000 (18:35 +0000)]
[x86] avoid FileCheck assert duplication with retl/retq regex; NFC
This was suggested in PR35003:
https://bugs.llvm.org/show_bug.cgi?id=35003
32-bit checks may be identical to 64-bit (if we avoid those pesky scalar params!).
I'll check in the script change shortly assuming this doesn't anger any bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316223
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Simon Pilgrim [Fri, 20 Oct 2017 18:07:50 +0000 (18:07 +0000)]
[X86][SSE] getTargetShuffleMask - check shuffle input value types. NFCI.
To help identify shuffle combine issues
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316222
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Sam Clegg [Fri, 20 Oct 2017 17:41:12 +0000 (17:41 +0000)]
[WebAssembly] MC: Handle (ignore) MCSA_Protected symbol attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316220
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Dave Lee [Fri, 20 Oct 2017 17:04:43 +0000 (17:04 +0000)]
Make x86 __ehhandler comdat if parent function is
Summary:
This change comes from using lld for i686-windows-msvc. Before this change, lld
emits an error of:
error: relocation against symbol in discarded section: .xdata
It's possible that this could be addressed in lld, but I think this change is
reasonable on its own.
At a high level, this is being generated:
A (.text comdat) -> B (.text) -> C (.xdata comdat)
Where A is a C++ inline function, which references B, an exception handler
thunk, which references C, the exception handling info.
With this structure, lld will error when applying relocations to B if the C it
references has been discarded (some other C has been selected).
This change checks if A is comdat, and if so places the exception registration
thunk (B) in the comdata group of A (and B).
It appears that MSVC makes the __ehhandler function comdat.
Is it possible that duplicate thunks are being emitted into the final binary
with other linkers, or are they stripping the unused thunks?
Reviewers: rnk, majnemer, compnerd, smeenai
Reviewed By: rnk, compnerd
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D38940
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316219
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Krzysztof Parzyszek [Fri, 20 Oct 2017 16:56:33 +0000 (16:56 +0000)]
[Hexagon] Allow redefinition with immediates for hw loop conversion
Normally, if the registers holding the induction variable's bounds
are redefined inside of the loop's body, the loop cannot be converted
to a hardware loop. However, if the redefining instruction is actually
loading an immediate value into the register, this conversion is both
possible and legal (since the immediate itself will be used in the
loop setup in the preheader).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316218
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Simon Pilgrim [Fri, 20 Oct 2017 16:55:51 +0000 (16:55 +0000)]
[X86] Check all CPU target names.
We ignore the 32-bit/64-bit triple but I've tried to use i686 triples for CPUs that don't support x86_64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316217
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Zvi Rackover [Fri, 20 Oct 2017 15:32:14 +0000 (15:32 +0000)]
X86 Tests: Add tests for vector permutes with variable indices. NFC.
Basic tests which are the equivalent of single-source shufflevector with variable mask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316216
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Aleksandar Beserminji [Fri, 20 Oct 2017 14:35:41 +0000 (14:35 +0000)]
Revert "[mips] Reordering callseq* nodes to be linear"
This reverts commit r314507, because the original patch is causing test
failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316215
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Eugene Leviant [Fri, 20 Oct 2017 14:29:17 +0000 (14:29 +0000)]
[ARM] Use post-RA MI scheduler when +use-misched is set
Differential revision: https://reviews.llvm.org/D39100
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316214
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Simon Pilgrim [Fri, 20 Oct 2017 14:13:02 +0000 (14:13 +0000)]
[X86][AVX512] Regenerate regcall tests.
As part of tracking down machine verifier issues (PR27481)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316213
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Nikolai Bozhenov [Fri, 20 Oct 2017 10:08:47 +0000 (10:08 +0000)]
[ValueTracking] Enabling ValueTracking patch by default
(recommit #2 after checking for timeout issue).
The original patch was an improvement to IR ValueTracking on
non-negative integers. It has been checked in to trunk (D18777,
r284022). But was disabled by default due to performance regressions.
Perf impact has improved. The patch would be enabled by default.
Reviewers: reames, hfinkel
Differential Revision: https://reviews.llvm.org/D34101
Patch by: Olga Chupina <olga.chupina@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316208
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Max Kazantsev [Fri, 20 Oct 2017 06:40:48 +0000 (06:40 +0000)]
Add test case for LoopSink pass
This test checks that load from constant memory will be sunk regardless of
aliasing stores in the loop.
Patch by Daniil Suchkov!
Differential Revision: https://reviews.llvm.org/D39113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316207
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Dylan McKay [Fri, 20 Oct 2017 04:17:14 +0000 (04:17 +0000)]
[AVR] Fix the select-mbb-placement-bug.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316205
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Lang Hames [Fri, 20 Oct 2017 01:18:00 +0000 (01:18 +0000)]
[ExecutionEngine] Temporarily remove the ExecutionEngine tls tests.
Will re-enable once I figure out why the necessary runtime functions are
missing on some bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316203
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Lang Hames [Fri, 20 Oct 2017 00:53:16 +0000 (00:53 +0000)]
[ExecutionEngine] After a heroic dev-meeting hack session, the JIT supports TLS.
Turns on EmulatedTLS support by default in EngineBuilder. ;)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316200
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Nemanja Ivanovic [Fri, 20 Oct 2017 00:36:46 +0000 (00:36 +0000)]
Disabling the transformation introduced in r315888
The commit at https://reviews.llvm.org/rL315888 is causing some failures
with internal testing. Disabling this code until we can resolve the issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316199
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Keith Wyss [Thu, 19 Oct 2017 22:35:09 +0000 (22:35 +0000)]
[XRay] [docs] Document how to generate flamegraphs from xray traces.
Summary:
Updated the XRayExample docs with instructions for using the llvm-xray stacks
command.
Reviewers: dberris
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39106
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316192
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Eugene Zelenko [Thu, 19 Oct 2017 22:07:16 +0000 (22:07 +0000)]
[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316190
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Alex Bradbury [Thu, 19 Oct 2017 21:43:29 +0000 (21:43 +0000)]
[RISCV] Add missing hunk from r316188
r316188 didn't set guessInstructionProperties=1 as it should have done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316189
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Alex Bradbury [Thu, 19 Oct 2017 21:37:38 +0000 (21:37 +0000)]
[RISCV] Initial codegen support for ALU operations
This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc
follow in future patches.
Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is
reviewed and lands.
Differential Revision: https://reviews.llvm.org/D29933
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316188
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Eugene Zelenko [Thu, 19 Oct 2017 21:21:30 +0000 (21:21 +0000)]
[Transforms] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316187
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Craig Topper [Thu, 19 Oct 2017 20:59:41 +0000 (20:59 +0000)]
[SelectionDAG] Add a check to getVectorShuffle to ensure that the only negative index we allow is -1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316183
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Craig Topper [Thu, 19 Oct 2017 20:59:40 +0000 (20:59 +0000)]
[X86] Remove LowerEXTRACT_SUBVECTOR handler. All EXTRACT_SUBVECTORs are marked as legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316182
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Simon Pilgrim [Thu, 19 Oct 2017 19:05:04 +0000 (19:05 +0000)]
[X86][AES] Test AES intrinsics on 32/64-bit targets with/without VEX encoding
Don't just test on 32-bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316176
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Graham Yiu [Thu, 19 Oct 2017 18:16:31 +0000 (18:16 +0000)]
The cost of splitting a large vector instruction is not being taken into account by the getUserCost function. This was leading to some loops being over unrolled. The cost of a vector instruction is now being multiplied by the cost of the type legalization. This will return a more accurate cost.
Committing on behalf on Brad Nemanich (brad.nemanich@ibm.com)
Differential Revision: https://reviews.llvm.org/D38961
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316174
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Konstantin Zhuravlyov [Thu, 19 Oct 2017 17:12:55 +0000 (17:12 +0000)]
AMDGPU/Docs: Fix unreadable characters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316171
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Krzysztof Parzyszek [Thu, 19 Oct 2017 16:59:22 +0000 (16:59 +0000)]
[Hexagon] Fix store conversion from rr to io in optimize addressing modes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316170
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Saleem Abdulrasool [Thu, 19 Oct 2017 16:57:40 +0000 (16:57 +0000)]
ExecutionEngine: adjust COFF i386 tautological asserts
Modify static_casts to not be tautological in some COFF i386
relocations.
Patch by Alex Langford!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316169
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Alex Bradbury [Thu, 19 Oct 2017 16:22:51 +0000 (16:22 +0000)]
[RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expected
This is necessary to avoid an assertion in the included test case and similar
assembler inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316168
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Alex Bradbury [Thu, 19 Oct 2017 16:09:20 +0000 (16:09 +0000)]
[RISCV][NFC] Drop unused parameter from createImm helper in RISCVAsmParser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316167
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Nikolai Bozhenov [Thu, 19 Oct 2017 15:36:18 +0000 (15:36 +0000)]
Revert r315992 because of a found miscompilation failure
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316164
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Simon Pilgrim [Thu, 19 Oct 2017 15:02:24 +0000 (15:02 +0000)]
[X86] Replace custom scalar integer absolute matching with ISD::ABS lowering.
x86 has its own copy of integer absolute pattern matching to combine directly to a SUB+CMOV.
This patch removes the x86 combine and adds custom lowering support for ISD::ABS instead, allowing us to use the DAGCombiner version.
Additional test cases are already covered by iabs.ll (rL315706 and rL315711).
Differential Revision: https://reviews.llvm.org/D38895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316162
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Simon Pilgrim [Thu, 19 Oct 2017 15:00:31 +0000 (15:00 +0000)]
Fix MSVC signed/unsigned comparison warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316161
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Simon Pilgrim [Thu, 19 Oct 2017 14:59:26 +0000 (14:59 +0000)]
[X86] Add scalar (abs (abs x)) -> (abs x) combine test.
Before landing D38895
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316160
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Alex Bradbury [Thu, 19 Oct 2017 14:29:03 +0000 (14:29 +0000)]
[RISCV] Prepare for the use of variable-sized register classes
While parameterising by XLen, also take the opportunity to clean up the
formatting of the RISCV .td files.
This commit unifies the in-tree code with my patchset at
<https://github.com/lowrisc/riscv-llvm>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316159
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Max Kazantsev [Thu, 19 Oct 2017 12:22:39 +0000 (12:22 +0000)]
Revert rL316156 due to failure on APFloatTest.fromToStringSpecials
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316158
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Serguei Katkov [Thu, 19 Oct 2017 11:16:03 +0000 (11:16 +0000)]
Fix APFloat from string conversion for Inf
The method IEEEFloat::convertFromStringSpecials() does not recognize
the "+Inf" and "-Inf" strings but these strings are printed for
the double Infinities by the IEEEFloat::toString().
This patch adds the "+Inf" and "-Inf" strings to the list of recognized
patterns in IEEEFloat::convertFromStringSpecials().
Reviewers: sberg, bogner, majnemer, timshen, rnk, skatkov, gottesmm, bkramer, scanon
Reviewed By: skatkov
Subscribers: apilipenko, reames, llvm-commits
Differential Revision: https://reviews.llvm.org/D38030
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316156
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Diana Picus [Thu, 19 Oct 2017 09:28:19 +0000 (09:28 +0000)]
[ARM GlobalISel] Fix liveins in test. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316155
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Diana Picus [Thu, 19 Oct 2017 08:50:28 +0000 (08:50 +0000)]
[ARM GlobalISel] Remove redundant tests
These test cases don't really add anything that isn't covered by other
tests as well, so we can safely remove them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316154
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Vassil Vassilev [Thu, 19 Oct 2017 08:44:19 +0000 (08:44 +0000)]
Revert 316150 which reinstated r316025.
It fails on some bots and now we know how to reproduce it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316153
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Sam McCall [Thu, 19 Oct 2017 08:13:49 +0000 (08:13 +0000)]
Const fix for YAMLParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316151
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Vassil Vassilev [Thu, 19 Oct 2017 08:04:22 +0000 (08:04 +0000)]
Reinstate r316025, reverted in r316029.
Original commit message:
"[cmake] Use find_package to discover zlib
This allows us to use standard cmake utilities to point to non-system zlib
locations.
Patch by Oksana Shadura and me (D39002)."
The new patch brings back the old behavior in the cases where find_package
cannot find zlib.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316150
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Vedant Kumar [Thu, 19 Oct 2017 06:16:23 +0000 (06:16 +0000)]
[Coverage] Simplify r316141. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316147
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Max Kazantsev [Thu, 19 Oct 2017 05:33:28 +0000 (05:33 +0000)]
[NFC][IRCE] Filter out empty ranges early
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316146
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whitequark [Thu, 19 Oct 2017 04:47:48 +0000 (04:47 +0000)]
[MergeFunctions] Don't blindly RAUW a GlobalValue with a ConstantExpr.
MergeFunctions uses (through FunctionComparator) a map of GlobalValues
to identifiers because it needs to compare functions and globals
do not have an inherent total order. Thus, FunctionComparator
(through GlobalNumberState) has a ValueMap<GlobalValue *>.
r315852 added a RAUW on globals that may have been previously
encountered by the FunctionComparator, which would replace
a GlobalValue * key with a ConstantExpr *, which is illegal.
This commit adjusts that code path to remove the function being
replaced from the ValueMap as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316145
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Rafael Espindola [Thu, 19 Oct 2017 01:32:18 +0000 (01:32 +0000)]
Simplify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316144
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