OSDN Git Service
Neil Roberts [Fri, 10 Apr 2015 16:20:21 +0000 (17:20 +0100)]
i965/skl: Use an exec size of 8 to initialise the message header
Commit
e93566a15c61c33faa changed the message header code needed to
make Skylake use SIMD4x2 so that it uses a register with width 4
instead of 8 as the source register in the send message. However it
also changed the width for the dest in the MOV instruction which is
used to initialise the header register with the values from g0. The
width of the destination is used to determine the exec size in
brw_set_dest so this would end up making the MOV have an exec size of
4. I think this would end up leaving the top half of the register
uninitialised. The top half of the header has meaningful values so
this probably isn't a good idea.
This patch just casts the dest register for the MOV instruction back
to a vec8 to fix it. It doesn't cause any changes to a Piglit run.
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Ian Romanick [Mon, 23 Mar 2015 19:03:56 +0000 (12:03 -0700)]
i965/fs: Always invert predicate of SEL with swapped arguments
Commit
b616164 added an optimization of b2f generation of a comparison.
It also included an extra optimization of one of the comparison values
is a constant of zero. The trick was that some value was known to be
zero, so that value could be used in the SEL instruction instead of
potentially loading 0.0 into a register.
This change switched the order of the arguments to the SEL, and, for
some unknown reason, I thought that the predicate should therefore
only be inverted for the == case. Clearly, it should always be
inverted.
Fixes piglit fs-notEqual-of-expression.shader_test and
fs-equal-of-expression.shader_test.
v2: Don't do the "register already has zero" optimization for the '== 0'
case. In that case, the register does not have zero when we want to
produce a zero result.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89722
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Tested-by: Lu Hua <huax.lu@intel.com>
Tom Stellard [Mon, 13 Apr 2015 13:25:41 +0000 (13:25 +0000)]
radeon/llvm: Improve codegen for KILL_IF
Rather than emitting one kill instruction per component of KILL_IF's src
reg, we now or the components of the src register together and use the
result as a condition for just one kill instruction.
shader-db stats (bonaire):
979 shaders
Totals:
SGPRS: 34872 -> 34848 (-0.07 %)
VGPRS: 20696 -> 20676 (-0.10 %)
Code Size: 749032 -> 748452 (-0.08 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 12288 -> 12288 (0.00 %) bytes per wave
Totals from affected shaders:
SGPRS: 1184 -> 1160 (-2.03 %)
VGPRS: 600 -> 580 (-3.33 %)
Code Size: 13200 -> 12620 (-4.39 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Increases:
SGPRS: 2 (0.00 %)
VGPRS: 0 (0.00 %)
Code Size: 0 (0.00 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)
Decreases:
SGPRS: 5 (0.01 %)
VGPRS: 5 (0.01 %)
Code Size: 25 (0.03 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)
*** BY PERCENTAGE ***
Max Increase:
SGPRS: 32 -> 40 (25.00 %)
VGPRS: 0 -> 0 (0.00 %)
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Max Decrease:
SGPRS: 32 -> 24 (-25.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 116 -> 96 (-17.24 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
*** BY UNIT ***
Max Increase:
SGPRS: 64 -> 72 (12.50 %)
VGPRS: 0 -> 0 (0.00 %)
Code Size: 0 -> 0 (0.00 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Max Decrease:
SGPRS: 32 -> 24 (-25.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 424 -> 356 (-16.04 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tom Stellard [Fri, 10 Apr 2015 17:07:16 +0000 (17:07 +0000)]
radeon/llvm: Run LLVM's instruction combining pass
This should improve code quality in general and will help with some
future changes to how we emit kill instructions.
shader-db shows a few regressions, but these don't seem to be the result
of deficiencies in instcombine. They're mostly caused by the scheduler
making different decisions than before.
shader-db stats (bonaire):
979 shaders
Totals:
SGPRS: 35056 -> 34872 (-0.52 %)
VGPRS: 20624 -> 20696 (0.35 %)
Code Size: 764372 -> 749032 (-2.01 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 12288 -> 12288 (0.00 %) bytes per wave
Totals from affected shaders:
SGPRS: 13264 -> 13072 (-1.45 %)
VGPRS: 8248 -> 8316 (0.82 %)
Code Size: 486320 -> 470992 (-3.15 %) bytes
LDS: 11 -> 11 (0.00 %) blocks
Scratch: 11264 -> 11264 (0.00 %) bytes per wave
Increases:
SGPRS: 6 (0.01 %)
VGPRS: 20 (0.02 %)
Code Size: 14 (0.01 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)
Decreases:
SGPRS: 32 (0.03 %)
VGPRS: 8 (0.01 %)
Code Size: 244 (0.25 %)
LDS: 0 (0.00 %)
Scratch: 0 (0.00 %)
*** BY PERCENTAGE ***
Max Increase:
SGPRS: 32 -> 48 (50.00 %)
VGPRS: 12 -> 20 (66.67 %)
Code Size: 216 -> 224 (3.70 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Max Decrease:
SGPRS: 40 -> 32 (-20.00 %)
VGPRS: 16 -> 12 (-25.00 %)
Code Size: 368 -> 280 (-23.91 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
*** BY UNIT ***
Max Increase:
SGPRS: 32 -> 48 (50.00 %)
VGPRS: 28 -> 36 (28.57 %)
Code Size: 39320 -> 40132 (2.07 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Max Decrease:
SGPRS: 72 -> 64 (-11.11 %)
VGPRS: 48 -> 40 (-16.67 %)
Code Size: 6272 -> 5852 (-6.70 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 0 -> 0 (0.00 %) bytes per wave
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tom Stellard [Mon, 13 Apr 2015 12:56:37 +0000 (12:56 +0000)]
radeonsi: Add header and footer to shader stat dump
This makes it easier to parse.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Sat, 11 Apr 2015 09:21:48 +0000 (02:21 -0700)]
i965: Fix software primitive restart with indirect draws.
new_prim was declared as a stack variable within a nested scope; we
tried to retain a pointer to that data beyond the scope, which is bogus.
GCC with -O1 eliminated most of the code that set new_prim's fields.
Move the declaration to fix the bug.
v2: Also fix new_ib (thanks to Matt Turner and Ben Widawsky).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81025
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Mon, 13 Apr 2015 01:39:07 +0000 (18:39 -0700)]
i965: Implement proper workaround for Gen4 GPU CONSTANT_BUFFER hangs.
I finally managed to dig up some information on our mysterious GPU hangs.
A wiki page from the Crestline validation team mentions that they found
a GPU hang in "Serious Sam 2" (on Windows) with remarkably similar
conditions to the ones we've seen in Google Chrome and glmark2.
Apparently, if WM_STATE has "PS Use Source Depth" enabled, CC_STATE has
most depth state disabled, and you issue a CONSTANT_BUFFER command and
immediately draw, the depth interpolator makes a small mistake that
leads to hangs.
Most of the traces I looked at contained a CONSTANT_BUFFER packet
immediately followed by 3DPRIMITIVE, or at least very few packets.
It appears they also have "PS Use Source Depth" enabled - either at the
hang, or a little before it. So I think this is our bug.
The workaround is to emit a non-pipelined state packet after issuing a
CONSTANT_BUFFER packet. This is really similar to the workaround I
developed in commit
c4fd0c9052dd391d6f2e9bb8e6da209dfc7ef35b.
v2: Fix word-wrapping issues.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Sun, 12 Apr 2015 10:52:39 +0000 (03:52 -0700)]
i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS.
In commit
4ebeb71573ad44f7657810dc5dd2c9030e3e63db, I deleted the
emit_shader_time_end() call in emit_urb_writes(). But I failed to add
it to run_vs(), as I intended. So no data was recorded at all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Anholt [Mon, 6 Apr 2015 22:12:58 +0000 (15:12 -0700)]
vc4: Add a blitter path using just the render thread.
This accelerates the path for generating the shadow tiled texture when
asked to sample from a raster texture (typical in glamor).
Eric Anholt [Thu, 9 Apr 2015 20:35:57 +0000 (13:35 -0700)]
vc4: Allow submitting jobs with no bin CL in validation.
For blitting, we want to fire off an RCL-only job. This takes a bit of
tweaking in our validation and the simulator support (and corresponding
new code in the kernel).
Eric Anholt [Thu, 9 Apr 2015 19:12:20 +0000 (12:12 -0700)]
vc4: Move the blit code to a separate file.
There will be other blit code showing up, and it seems like the place
you'd look.
Eric Anholt [Mon, 6 Apr 2015 19:58:51 +0000 (12:58 -0700)]
vc4: Separate out a bit of code for submitting jobs to the kernel.
I want to be able to have multiple jobs being set up at the same time (for
example, a render job to do a little fixup blit in the course of doing a
render to the main FBO).
Eric Anholt [Wed, 8 Apr 2015 19:49:24 +0000 (12:49 -0700)]
vc4: When asked to sample from a raster texture, make a shadow tiled copy.
So, it turns out my simulator doesn't *quite* match the hardware. And the
errata about raster textures tells you most of what's wrong, but there's
still stuff wrong after that. Instead, if we're asked to sample from
raster, we'll just blit it to a tiled temporary.
Raster textures should only be screen scanout, and word is that it's
faster to copy to tiled using the tiling engine first than to texture from
an entire raster texture, anyway.
Eric Anholt [Thu, 9 Apr 2015 20:43:55 +0000 (13:43 -0700)]
vc4: Fix off-by-one in branch target validation.
Eric Anholt [Mon, 13 Apr 2015 21:12:59 +0000 (14:12 -0700)]
vc4: Use NIR-level lowering for idiv.
This fixes the idiv tests in piglit.
Eric Anholt [Wed, 1 Apr 2015 22:35:13 +0000 (15:35 -0700)]
vc4: Add a bunch of type conversions.
These are required to get piglit's idiv tests working. The
unsigned<->float conversions are wrong, but are good enough to get
piglit's small ranges of values working.
Dave Airlie [Wed, 8 Apr 2015 00:00:27 +0000 (10:00 +1000)]
st/mesa: align cube map arrays layers
We create textures internally for texsubimage, and we use
the values from sub image to create a new texture, however
we don't align these to valid sizes, and cube map arrays
must have an array size aligned to 6.
This fixes texsubimage cube_map_array on CAYMAN at least,
(it was causing GPU hang and bad values), it probably
also fixes it on radeonsi and evergreen.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89957
Tested-by: Tom Stellard <thomas.stellard@amd.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 8 Apr 2015 00:59:20 +0000 (10:59 +1000)]
st/mesa: convert sub image for cube map arrays to 2d arrays for upload
Since we can subimage upload a number of cube map array layers,
that aren't a complete cube map array, we should specify things
as a 2D array and blit from that.
Suggested by Ilia Mirkin as an alternate fix for texsubimage
cube map array issues.
seems to work just as well.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Mathias Froehlich [Sun, 12 Apr 2015 16:23:58 +0000 (18:23 +0200)]
i965: Flush batchbuffer containing the query on glQueryCounter.
This change fixes a regression with timer queries introduced with
commit
3eb6258. There the pending batchbuffer is flushed
only if glEndQuery is executed. This present change adds such
a flush to glQueryCounter which also schedules a value query
just like glEndQuery does. The patch fixes GPU timer queries
going mad from within osgviewer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Mathias Froehlich <Mathias.Froehlich@web.de>
Cc: mesa-stable@lists.freedesktop.org
Eric Anholt [Wed, 8 Apr 2015 20:11:01 +0000 (13:11 -0700)]
vc4: Use the blit interface for updating shadow textures.
This lets us plug in a better blit implementation and have it impact the
shadow update, too.
Eric Anholt [Thu, 9 Apr 2015 20:13:23 +0000 (13:13 -0700)]
vc4: Remove dead fields from vc4_surface.
Eric Anholt [Mon, 6 Apr 2015 22:19:30 +0000 (15:19 -0700)]
vc4: Skip sending down the clear colors if not clearing.
Eric Anholt [Thu, 9 Apr 2015 20:41:29 +0000 (13:41 -0700)]
vc4: Sync with kernel changes to relax BCL versus RCL validation.
There was no reason to tie the two packets' values together.
Eric Anholt [Thu, 9 Apr 2015 20:05:00 +0000 (13:05 -0700)]
vc4: Fix another space allocation mistake.
We're over-allocating our BCL in vc4_draw.c, so this never mattered.
However, new RCL-only blit support might end up here without having set up
any BCL contents.
Eric Anholt [Mon, 6 Apr 2015 22:15:37 +0000 (15:15 -0700)]
vc4: Add missed accounting for the size of the semaphore.
This wouldn't have mattered except in the worst case scenario RCL setup.
Matt Turner [Sat, 11 Apr 2015 17:14:00 +0000 (10:14 -0700)]
swrast: Mark MAX_GLUINT literal with u suffix.
Coverity is confused by the "float < int / 2" expression and suggests
casting MAX_GLUINT to unsigned, which I believe it was supposed to have
been already.
Reviewed-by: Brian Paul <brianp@vmware.com>
Matt Turner [Sat, 11 Apr 2015 17:05:31 +0000 (10:05 -0700)]
i965: Don't bother freeing NULL.
Commit
e16c5c90 was replacing 'region' with 'mt', leaving this
nonsensical code.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Chad Versace [Fri, 10 Apr 2015 03:29:59 +0000 (20:29 -0700)]
i965: Lift some restrictions on dma_buf EGLImages
Allow glEGLImageTargetRenderbufferStorageOES and
glEGLImageTargetTexture2DOES for dma_buf EGLImages if the image is
a single RGBA8 unorm plane. This is safe, despite fast color clears,
because i965 disables allocation of auxiliary buffers for EGLImages.
Chrome OS needs this, because its compositor uses dma_buf EGLImages for
its scanout buffers.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`, with my Piglit patches that update the
EGL_EXT_image_dma_buf_import tests.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Chad Versace [Mon, 6 Apr 2015 15:07:27 +0000 (08:07 -0700)]
i965: Disable aux buffers for EGLImage-backed miptrees
EGL does not yet have extensions to manage the flushing and invalidating
of driver-internal aux buffers. So we must disable aux buffers of
dma_buf-backed EGLImages in order to safely render into them.
This patch is obviously needed for renderbufers. It's also needed for
textures because the user can attach the texture to a framebuffer and
because the driver sometimes renders to textures for internal reasons.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Chad Versace [Mon, 6 Apr 2015 15:11:43 +0000 (08:11 -0700)]
i965: Change intel_miptree_create_for_bo() signature
Add parameter 'bool disable_aux_buffers'.
This is a refactor patch. The patch changes no behavior because the new
parameter is false in every call.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Chad Versace [Mon, 6 Apr 2015 13:46:09 +0000 (06:46 -0700)]
i965: Add field intel_mipmap_tree::disable_aux_buffers
The new field disables allocation of auxiliary buffers, such as the HiZ
buffer and MCS buffer. This is useful for sharing the miptree bo with an
external client that doesn't understand auxiliary buffers.
We need this field to safely render to a buffer that was imported with
EGL_EXT_image_dma_buf_import, because EGL does not yet have extensions
to manage flushing and invalidating auxiliary buffers.
Nothing yet enables this field. That's left to follow-up patches.
Testing:
- Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
YouTube.
- No Piglit regressions on Broadwell with `piglit run -p gbm
tests/quick.py`.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Chad Versace [Mon, 6 Apr 2015 13:54:30 +0000 (06:54 -0700)]
i965: Refactor brw_is_hiz_depth_format()
Every caller of this function uses it to determine if the current
miptree needs a hiz buffer to be allocated. Strangely, the function
doesn't take a miptree argument. So, this function effectively decides
if and when a miptree's hiz buffer gets allocated without inspecting the
miptree itself. Luckily, the driver behaves correctly despite the
brw_is_hiz_depth_format's quirk.
I will soon make some changes to the miptree that will require
inspecting the miptree to determine if it needs a hiz buffer. So this
patch renames
brw_is_hiz_depth_format -> intel_miptree_wants_hiz_buffer
and gives it a miptree parameter.
This patch shouldn't change any behavior.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Chad Versace [Mon, 6 Apr 2015 14:13:53 +0000 (07:13 -0700)]
i965: Declare intel_miptree_create_layout() as static
It's not used outside intel_mipmap_tree.c.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Chad Versace [Mon, 6 Apr 2015 14:04:06 +0000 (07:04 -0700)]
i965: Declare intel_miptree_alloc_mcs() as static
It's not used outside of intel_mipmap_tree.c, nor should it ever be.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jose Fonseca [Mon, 13 Apr 2015 12:08:13 +0000 (13:08 +0100)]
docs: Improve LLVM_USE_CRT_xxx instructions.
Jose Fonseca [Thu, 2 Apr 2015 10:25:06 +0000 (11:25 +0100)]
glx: Include util/macros.h instead of redefining PRINTFLIKE.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Jose Fonseca [Thu, 2 Apr 2015 10:24:26 +0000 (11:24 +0100)]
util/ralloc: Fix `extern "C"` usage.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jose Fonseca [Thu, 2 Apr 2015 09:09:38 +0000 (10:09 +0100)]
mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.
I'm not sure what was the original intention, but currently
USE_EXTERNAL_DXTN_LIB always ends up defined, one way or another.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Emil Velikov [Sun, 12 Apr 2015 22:16:42 +0000 (23:16 +0100)]
docs: add news item and link release notes for mesa 10.5.3
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sun, 12 Apr 2015 22:10:42 +0000 (23:10 +0100)]
docs: Add 256 sums for the 10.5.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
65776421fe59a0ffd5388c0968c9b0b1c1b230ed)
Emil Velikov [Sun, 12 Apr 2015 21:29:06 +0000 (22:29 +0100)]
Add release notes for the 10.5.3 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
c4b8bff6e24c6661a8a05ec05f8ed5762e95021b)
Emil Velikov [Thu, 2 Apr 2015 08:37:12 +0000 (08:37 +0000)]
docs: remove the --with-max-{width,height} note
Missed out with commit
d99135b2e9b(configure: nuke
--with-max-{width,height})
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Emil Velikov [Wed, 1 Apr 2015 16:46:09 +0000 (17:46 +0100)]
configure.ac: remove deprecated --with-libclc-path
The option was deprecated with commit
959e83d6507(clover: Adapt libclc's
INCLUDEDIR and LIBEXECDIR to make use of the new introduced libclc.pc.)
back in 2012 with mesa 9.2.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Kenneth Graunke [Sat, 24 Jan 2015 10:05:56 +0000 (02:05 -0800)]
i965/nir: Make INTEL_DEBUG=ann work with NIR.
Now that we store a copy of the NIR shader, and don't immediately free
it, we can use it in annotations as well.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:15:09 +0000 (15:15 -0700)]
i965: Create NIR during LinkShader() and ProgramStringNotify().
Previously, we translated into NIR and did all the optimizations and
lowering as part of running fs_visitor. This meant that we did all of
that work twice for fragment shaders - once for SIMD8, and again for
SIMD16. We also had to redo it every time we hit a state based
recompile.
We now generate NIR once at link time. ARB programs don't have linking,
so we instead generate it at ProgramStringNotify time.
Mesa's fixed function vertex program handling doesn't bother to inform
the driver about new programs at all (which is rather mean), so we
generate NIR at the last minute, if it hasn't happened already.
shader-db runs ~9.4% faster on my i7-5600U, with a release build.
v2: Check NirOptions != NULL in ProgramStringNotify(). Don't bother
using _mesa_program_enum_to_shader_stage as we already know it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Wed, 8 Apr 2015 00:13:45 +0000 (17:13 -0700)]
nir: Store num_direct_uniforms in the nir_shader.
Storing this here is pretty sketchy - I don't know if any driver other
than i965 will want to use it. But this will make it a lot easier to
generate NIR code at link time. We'll probably rework it anyway.
(Ian suggested making nir_assign_var_locations_scalar_direct_first
simply modify the nir_shader's fields, rather than passing pointers
to them. If this stays long term, we should do that. But Jason and
I suspect we'll be reworking this area again in the near future.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:05:12 +0000 (15:05 -0700)]
i965: Move lower_output_reads to brw_link_shader().
This makes it so emit_nir_code() doesn't modify the GLSL IR.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Sat, 11 Apr 2015 17:11:13 +0000 (10:11 -0700)]
glsl: Mark path as unreachable.
Matt Turner [Sat, 11 Apr 2015 16:54:38 +0000 (09:54 -0700)]
i965: Remove useless null check.
If it were null, we'd have just derefernced it two lines above.
Matt Turner [Sat, 11 Apr 2015 16:49:36 +0000 (09:49 -0700)]
i965/fs/nir: Mark fallthrough.
Matt Turner [Sat, 11 Apr 2015 16:47:39 +0000 (09:47 -0700)]
i965: Remove useless reg_offset >= 0 tests.
Commit
eb9bd3a1 changed the type of this field to uint16_t.
Rob Clark [Sat, 11 Apr 2015 14:04:50 +0000 (10:04 -0400)]
freedreno/ir3/nir: couple little fixes
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 10 Apr 2015 19:57:29 +0000 (15:57 -0400)]
freedreno/ir3/nir: handle system values
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 10 Apr 2015 00:32:14 +0000 (20:32 -0400)]
freedreno/ir3/nir: handle txs and query_levels tex ops
These correspond to the tgsi TXQ opcode
(plus sneak in a fix for two-sided color)
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 9 Apr 2015 20:44:38 +0000 (16:44 -0400)]
freedreno/ir3/nir: split out tex helpers
We'll need these in one or two other spots.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Thu, 9 Apr 2015 16:55:49 +0000 (12:55 -0400)]
freedreno/ir3/nir: simplify emit_tex()
Just build up arrays for src0/src1, and use create_collect()..
Also add back missing .3d flag for 3d/cube textures.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 8 Apr 2015 18:10:00 +0000 (14:10 -0400)]
freedreno/ir3/cp: handle indirect properly
I noticed some cases where we where trying to copy-propagate indirect
src's into places they cannot go, like 2nd src for cat3 (mad, etc).
Expand out valid_flags() to be aware of relativ flag, and fix up a few
related spots.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 8 Apr 2015 15:04:37 +0000 (11:04 -0400)]
freedreno/ir3/sched: avoid getting stuck on addr conflicts
When we get in a scenario where we cannot schedule any more instructions
due to address register conflict, clone the instruction that writes the
address register, and switch the remaining unscheduled users for the
current address register over to the new clone.
This is simpler and more robust than the previous attempt (which tried
and sometimes failed to ensure all other dependencies of users of the
address register were scheduled first).. hint it would try to schedule
instructions that were not actually needed for any output value.
We probably need to do the same with predicate register, although so far
it isn't so heavily used so we aren't running into problems with it
(yet).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Wed, 8 Apr 2015 00:41:48 +0000 (20:41 -0400)]
freedreno/ir3/nir: add variable-indexing support
A bit fugly.. try and make this cleaner.. note if we hoist all the
get_addr() out of the loop we can drop the hashtable and just use
create_addr()..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 6 Apr 2015 15:42:57 +0000 (11:42 -0400)]
freedreno/ir3/asm: change assert to warning
It probably *should* be an assert, but for now TGSI f/e isn't very good
about dealing w/ CONST vs ABS/NEG. So for debug builds, print a warning
instead of crashing with an assert for now.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 6 Apr 2015 14:54:30 +0000 (10:54 -0400)]
freedreno/ir3/nir: set first_driver_param
Without this, a3xx breaks.. a4xx would too if it had already implemented
support for passing driver params.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Mon, 6 Apr 2015 14:48:11 +0000 (10:48 -0400)]
freedreno/ir3/cp: support to swap mad src's
For a normal MAD (ie. not MADSH), if first source is gpr and second
source is const, we can swap the first two sources to avoid needing a
mov instruction.
This gives back the biggest advantage TGSI f/e had over NIR f/e for
common shaders, since TGSI f/e had this logic in the f/e. Note that
doing this in copy-prop step has the advantage that it will also work
for cases like:
MOV TEMP[b], CONST[x]
MAD TEMP[d], TEMP[a], TEMP[b], TEMP[c]
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 10 Apr 2015 20:39:30 +0000 (16:39 -0400)]
nir: fix bit of cargo-culting in lower_idiv
I guess I was looking too much at how lower_system_values worked when
writing lower_idiv.
Since ttn wasn't emitting load_var for sysvals and the only drivers
using lower_idiv were using ttn, I think nothing was broken as a result.
But might as well fix this before it becomes a problem.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Rob Clark [Sat, 4 Apr 2015 12:13:44 +0000 (08:13 -0400)]
nir: split out lower_sub from lower_negate
Originally you had to have one or the other. But actually I don't want
either. (Or rather I want whatever is the minimum # of instructions.)
TODO: not sure where the best place to insert a check that driver hasn't
set *both* lower_negate and lower_sub?
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Rob Clark [Fri, 10 Apr 2015 19:01:16 +0000 (15:01 -0400)]
gallium/ttn: add support for system values
So far just the system values that freedreno supports, so we may add
more later.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Fri, 10 Apr 2015 18:19:22 +0000 (14:19 -0400)]
gallium/ttn: fix TXD
With TXD we also have the ddx/ddy sources (before the sampler).
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Thu, 9 Apr 2015 19:41:31 +0000 (15:41 -0400)]
gallium/ttn: add TXQ support (v2)
Split out from ttn_tex() since it is kind of a weird instruction that
maps to two NIR opcodes, and it was cleaner this way.
v2: query_levels doesn't take any args
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Thu, 9 Apr 2015 19:16:17 +0000 (15:16 -0400)]
gallium/ttn: split out helper to get texture info
We'll need this as well for TXQ. Split this out first to reduce noise
in the next patch.
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Tue, 7 Apr 2015 15:38:23 +0000 (11:38 -0400)]
gallium/ttn: add support for temp arrays
Since the rest of NIR really would rather have these as variables rather
than registers, create a nir_variable per array. But rather than
completely re-arrange ttn to be variable based rather than register
based, keep the registers. In the cases where there is a matching var
for the reg, ttn_emit_instruction will append the appropriate intrinsic
to get things back from the shadow reg into the variable.
NOTE: this doesn't quite handle TEMP[ADDR[]] when the DCL doesn't give
an array id. But those just kinda suck, and should really go away.
AFAICT we don't get those from glsl. Might be an issue for some other
state tracker.
v2: rework to use load_var/store_var with deref chains
v3: create new "burner" reg for temporarily holding the (potentially
writemask'd) dest after each instruction; add load_var to initialize
temporary dest in case not all components are overwritten
v4: review comments: asserts and use ttn_src_for_indirect() in
ttn_array_deref() so we can drop later patch converting to use vec1 for
addr reg (since ttn_src_for_indirect() handles the imov to vec1 from
tgsi addr component that we want)
v5: rebase: new requirements about parent mem ctx for derefs
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Rob Clark [Wed, 8 Apr 2015 17:17:30 +0000 (13:17 -0400)]
gallium/ttn: minor cleanup
Extract tgsi_dst->Index into a local.. split out from 'gallium/ttn: add
support for temp arrays' for noise reduction..
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Jason Ekstrand [Fri, 10 Apr 2015 23:24:11 +0000 (16:24 -0700)]
i965: Use NIR by default for fragment shaders
GLSL IR vs. NIR shader-db results on i965:
total instructions in shared programs:
2889747 ->
2890782 (0.04%)
instructions in affected programs:
2425446 ->
2426481 (0.04%)
helped: 3698
HURT: 5341
GLSL IR vs. NIR shader-db results on g4x:
total instructions in shared programs:
2547252 ->
2550440 (0.13%)
instructions in affected programs:
1984482 ->
1987670 (0.16%)
helped: 2844
HURT: 4776
GLSL IR vs. NIR shader-db results on Iron Lake:
total instructions in shared programs:
4053381 ->
4063828 (0.26%)
instructions in affected programs:
3026601 ->
3037048 (0.35%)
helped: 4110
HURT: 8331
GAINED: 1287
LOST: 9
GLSL IR vs. NIR shader-db results on Sandy Bridge:
total instructions in shared programs:
5307041 ->
5236666 (-1.33%)
instructions in affected programs:
3442908 ->
3372533 (-2.04%)
helped: 11829
HURT: 5604
GAINED: 33
LOST: 18
GLSL IR vs. NIR shader-db results on Ivy Bridge:
total instructions in shared programs:
4926333 ->
4857017 (-1.41%)
instructions in affected programs:
3144042 ->
3074726 (-2.20%)
helped: 11559
HURT: 4774
GAINED: 46
LOST: 25
GLSL IR vs. NIR shader-db results on Bay Trail:
total instructions in shared programs:
4926333 ->
4857017 (-1.41%)
instructions in affected programs:
3144042 ->
3074726 (-2.20%)
helped: 11559
HURT: 4774
GAINED: 46
LOST: 25
GLSL IR vs. NIR shader-db results on Haswell:
total instructions in shared programs:
4392487 ->
4293476 (-2.25%)
instructions in affected programs:
2800180 ->
2701169 (-3.54%)
helped: 13073
HURT: 3383
GAINED: 46
LOST: 23
GLSL IR vs. NIR shader-db results on Broadwell (FS only):
total instructions in shared programs:
4378113 ->
4283025 (-2.17%)
instructions in affected programs:
2743209 ->
2648121 (-3.47%)
helped: 12470
HURT: 3609
GAINED: 64
LOST: 27
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Fri, 10 Apr 2015 06:26:49 +0000 (23:26 -0700)]
i965: Don't set NirOptions for stages that will use the vec4 backend.
We've started using NirOptions != NULL to mean "we're using NIR for this
stage." However, when INTEL_USE_NIR=1, we set it for a bunch of stages
that still use the vec4 backend, and thus definitely aren't using NIR.
For example, if INTEL_USE_NIR=1 we disable the GLSL IR cubemap
normalization pass, even for vertex shaders and geometry shaders. This
is wrong, but breaks a very uncommon case.
When I started deleting GLSL IR for stages where we claimed to be using
NIR, this bug quickly became apparent.
For now, only set it for fragment shaders, and vertex shaders if
brw->scalar_vs is set.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Nick Sarnie [Fri, 10 Apr 2015 16:45:57 +0000 (12:45 -0400)]
gallivm: Fix build since llvm-3.7.0svn r234495
Revert
50e9fa2ed69cb5f76f66231976ea789c0091a64d as LLVM reverted their
change.
Signed-off-by: Nick Sarnie <commendsarnex@gmail.com>
Reviewed-by: Jan Vesely <jan.vesely@rutgers.edu>
Ville Syrjälä [Tue, 31 Mar 2015 12:01:24 +0000 (15:01 +0300)]
i965/disasm: Print the type after the swizzle also for 3src src operands
The disassembly currently has the swizzle after the type for 3src source
operands, and the other way around for 2src. Flip the type and swizzle
around for 3src so that the output matches 2src.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 23:28:10 +0000 (16:28 -0700)]
i965: Move brw_link_shader's GLSL IR transformations into a helper.
This function was getting a bit large and unwieldy.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 23:29:32 +0000 (16:29 -0700)]
i965: Change brw_shader to gl_shader in brw_link_shader().
Nothing actually wanted brw_shader fields - we just had to type
shader->base all over the place for no reason.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:50:54 +0000 (15:50 -0700)]
nir: Constify nir_lower_sampler's gl_shader_program pointer.
Now that we're not generating linker errors, we don't actually modify
this.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:46:56 +0000 (15:46 -0700)]
nir: Remove linker_error calls from nir_lower_samplers().
These should never happen. Plus, NIR passes really shouldn't be
reporting linker errors - this is past link time.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:14:16 +0000 (15:14 -0700)]
nir: Make nir_lower_samplers take a gl_shader_stage, not a gl_program *.
We don't actually need a gl_program struct. We only used it to
translate prog->Target (i.e. GL_VERTEX_PROGRAM) to the gl_shader_stage
(i.e. MESA_SHADER_VERTEX). We may as well just pass that.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:18:43 +0000 (15:18 -0700)]
nir: Move gl_shader_stage enum from mtypes.h to shader_enums.h.
I want to use this in some code that doesn't currently include mtypes.h.
It seems like a better place for it anyway.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:16:51 +0000 (15:16 -0700)]
nir: Fix #include guards in shader_enums.h.
This header was originally going to be called pipeline.h, but it got
renamed at the last minute. Make the include guards match.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 22:07:33 +0000 (15:07 -0700)]
nir: Constify prog_to_nir's gl_program pointer.
prog_to_nir should not modify the incoming Mesa IR program - just
translate it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Vinson Lee [Thu, 9 Apr 2015 05:51:57 +0000 (22:51 -0700)]
gallivm: Fix build since llvm-3.7.0svn r234460.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89963
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Roland Scheidegger [Sat, 4 Apr 2015 14:49:08 +0000 (16:49 +0200)]
draw: (trivial) don't print the shader twice with GALLIVM_DEBUG=tgsi (or ir)
Neither the shader nor the key change when doing elts or linear variant, so
this was just annoying (probably mildly useful at some point when we printed
the IR per function too).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Wed, 8 Apr 2015 22:49:11 +0000 (00:49 +0200)]
gallivm: don't use control flow when doing indirect constant buffer lookups
llvm goes crazy when doing that, using way more memory and time, though there's
probably more to it - this points to a very much similar issue as fixed in
8a9f5ecdb116d0449d63f7b94efbfa8b205d826f. In any case I've seen a quite
plain looking vertex shader with just ~50 simple tgsi instructions (but with a
dozen or so such indirect constant buffer lookups) go from a terribly high
~440ms compile time (consuming 25MB of memory in the process) down to a still
awful ~230ms and 13MB with this fix (with llvm 3.3), so there's still obvious
improvements possible (but I have no clue why it's so slow...).
The resulting shader is most likely also faster (certainly seemed so though
I don't have any hard numbers as it may have been influenced by compile times)
since generally fetching constants outside the buffer range is most likely an
app error (that is we expect all indices to be valid).
It is possible this fixes some mysterious vertex shader slowdowns we've seen
ever since we are conforming to newer apis at least partially (the main draw
loop also has similar looking conditionals which we probably could do without -
if not for the fetch at least for the additional elts condition.)
v2: use static vars for the fake bufs, minor code cleanups
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Wed, 1 Apr 2015 20:36:09 +0000 (14:36 -0600)]
glsl: check for forced_language_version in is_version()
This is a follow-on fix from the earlier "glsl: allow ForceGLSLVersion
to override #version directives" change. Since we're not changing
the language_version field, we have to check forced_language_version
here.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Neil Roberts [Fri, 6 Mar 2015 19:11:19 +0000 (19:11 +0000)]
i965/skl: Fix the order of the arguments for the LD sampler message
In Skylake the order of the arguments for sample messages with the LD
type are u, v, lod, r whereas previously they were u, lod, v, r.
This fixes 144 Piglit tests including ones that directly use
texelFetch and also some using the meta stencil blit path which
appears to use texelFetch in its shader.
v2: Fix sampling 1D textures
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Zhenyu Wang [Tue, 7 Apr 2015 05:48:38 +0000 (13:48 +0800)]
i965: Fix depth field setting in surface state for raw buffer on Gen7/8
On Gen7/8 for RAW surface format, the depth field (surf[3]) in surface
state means [30:21] bits of number of entries which is different from
other surface format which uses [26:21] bits field.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Dave Airlie [Wed, 8 Apr 2015 00:31:14 +0000 (10:31 +1000)]
u_tile: fix warnings about incompatible casts.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Glenn Kennard [Tue, 7 Apr 2015 01:00:20 +0000 (03:00 +0200)]
r600g/sb: Enable SB for geometry shaders
Add SV_GEOMETRY_EMIT special variable type to track the
implicit dependencies between CUT/EMIT_VERTEX/MEM_RING
instructions so GCM/scheduler doesn't reorder them.
Mark emit instructions as unkillable so DCE doesn't eat them.
Enable only for evergreen/cayman as there are a few
unexplained GS piglit regressions on R6xx/R7xx with SB
enabled otherwise.
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Glenn Kennard [Thu, 26 Mar 2015 01:56:50 +0000 (02:56 +0100)]
r600g/sb: Update last_cf for loops
CF_END could end up emitted in the middle of a shader on cayman
when there was a loop at the very end.
Fixes glsl-1.50-geometry-end-primitive and
ext_transform_feedback-geometry-shaders-basic piglit tests.
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 6 Apr 2015 23:52:41 +0000 (09:52 +1000)]
u_tile: fix stencil texturing tests under softpipe
arb_stencil_texturing-draw failed under softpipe because we got a float
back from the texturing function, and then tried to U2F it, stencil
texturing returns ints, so we should fix the tiling to retrieve
the stencil values as integers not floats.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Tue, 7 Apr 2015 19:33:17 +0000 (12:33 -0700)]
nir: Make nir_*_instr_create take a nir_shader instead of a void * context
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Sat, 28 Mar 2015 02:50:29 +0000 (19:50 -0700)]
nir: Implement a nir_sweep() pass.
This pass performs a mark and sweep pass over a nir_shader's associated
memory - anything still connected to the program will be kept, and any
dead memory we dropped on the floor will be freed.
The expectation is that this will be called when finished building and
optimizing the shader. However, it's also fine to call it earlier, and
many times, to free up memory earlier.
v2: (feedback from Jason Ekstrand)
- Skip sweeping impl->start_block, as it's already in the CF list.
- Don't sweep SSA defs (they're owned by their defining instruction)
- Don't steal phi sources (they're owned by nir_phi_instr).
- Don't steal tex->src (it's owned by the tex_inst itself)
- Don't sweep dereference chains (top-level dereferences are owned by
the instruction; sub-dereferences are owned by the parent deref).
- Don't sweep sources and destinations (SSA defs are handled as part of
the defining instruction, and registers are handled as part of
function implementations).
- Just steal instructions; don't walk them (no longer required).
v3: (feedback from Jason Ekstrand)
- Steal indirect sources from nir_src/nir_dest.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Fri, 3 Apr 2015 04:24:38 +0000 (21:24 -0700)]
nir: Allocate dereferences out of their parent instruction or deref.
Jason pointed out that variable dereferences in NIR are really part of
their parent instruction, and should have the same lifetime.
Unlike in GLSL IR, they're not used very often - just for intrinsic
variables, call parameters & return, and indirect samplers for
texturing. Also, nir_deref_var is the top-level concept, and
nir_deref_array/nir_deref_record are child nodes.
This patch attempts to allocate nir_deref_vars out of their parent
instruction, and any sub-dereferences out of their parent deref.
It enforces these restrictions in the validator as well.
This means that freeing an instruction should free its associated
dereference chain as well. The memory sweeper pass can also happily
ignore them.
v2: Rename make_deref to evaluate_deref and make it take a nir_instr *
instead of void *. This involves adding &instr->instr everywhere.
(Requested by Jason Ekstrand.)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Sat, 28 Mar 2015 17:02:17 +0000 (10:02 -0700)]
nir: Allocate nir_ssa_def::uses/if_uses out of the instruction.
We can't allocate them out of the nir_ssa_def itself, because it may not
be ralloc'd (for example, nir_dest embeds a nir_ssa_def).
However, allocating them out of the instruction should work.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Thu, 2 Apr 2015 23:15:11 +0000 (16:15 -0700)]
nir: Allocate nir_phi_src values out of the nir_phi_instr.
Phi sources are part of the phi instruction and should have the same
lifetime.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Tue, 7 Apr 2015 07:32:55 +0000 (00:32 -0700)]
nir: Allocate nir_call_instr::params out of the nir_call itself.
The lifetime of the params array needs to be match the nir_call_instr
itself. So, allocate it using the instruction itself as the context.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Sun, 29 Mar 2015 10:45:16 +0000 (03:45 -0700)]
i965: Add the ability to render to I8/L8 and I16/L16 UNORM formats.
This allows those formats to work with the meta PBO upload path.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Mon, 6 Apr 2015 23:09:35 +0000 (16:09 -0700)]
i965: Use SET_FIELD in 3DSTATE_STREAMOUT packets.
Suggested by Topi Pohjolainen.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>