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Dmytro Laktyushkin [Fri, 8 Nov 2019 21:20:36 +0000 (16:20 -0500)]
drm/amd/display: fix dml20 min_dst_y_next_start calculation
Bring this calculation in line with HW programming guide.
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Sun, 10 Nov 2019 20:22:15 +0000 (15:22 -0500)]
drm/amd/display: Disable chroma viewport w/a when rotated 180 degrees
[WHY]
Previous Renoir chroma viewport workaround fixed an MPO flicker by
increasing the chroma viewport size. However, when the MPO plane is
rotated 180 degrees, the viewport is read in reverse. Since the workaround
increases viewport size, when reading in reverse it causes a vertical
chroma offset.
[HOW]
Pass rotation value to viewport set functions
Temporarily disable the chroma viewport w/a when hubp is rotated 180 degrees
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
abdoulaye berthe [Wed, 23 Oct 2019 21:16:51 +0000 (17:16 -0400)]
drm/amd/display: add log for lttpr
Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Brandon Syu [Fri, 8 Nov 2019 03:26:06 +0000 (11:26 +0800)]
drm/amd/display: fixed that I2C over AUX didn't read data issue
[Why]
The variable mismatch assignment error.
[How]
To use uint32_t replace it.
Signed-off-by: Brandon Syu <Brandon.Syu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Hanghong) Ma [Thu, 7 Nov 2019 21:30:04 +0000 (16:30 -0500)]
drm/amd/display: Change the delay time before enabling FEC
[why]
DP spec requires 1000 symbols delay between the end of link training
and enabling FEC in the stream. Currently we are using 1 miliseconds
delay which is not accurate.
[how]
One lane RBR should have the maximum time for transmitting 1000 LL
codes which is 6.173 us. So using 7 microseconds delay instead of
1 miliseconds.
Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Aric Cyr [Mon, 11 Nov 2019 15:07:50 +0000 (10:07 -0500)]
drm/amd/display: 3.2.61
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Sun, 10 Nov 2019 17:08:02 +0000 (12:08 -0500)]
drm/amd/display: fix dprefclk and ss percentage reading on RN
[Why]
Before was using HW counter value to determine the dprefclk. Which
take into account ss, but has large variation, not good enough for
generating audio dto. Also, the bios parser code to get the ss
percentage was not working.
[How]
After this change, dprefclk is hard coded, same as on RV. We don't
expect this to change on Renoir. Modified bios parser code to get
the right ss percentage.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Gravenor [Fri, 8 Nov 2019 19:30:34 +0000 (14:30 -0500)]
drm/amd/display: have two different sr and pstate latency tables for renoir
[Why]
new sr and pstate latencies are optimized for the case when we are not
using lpddr4 memory
[How]
have two different wm tables, one for the lpddr case and one for
non lpddr case
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
David Galiffi [Thu, 7 Nov 2019 22:18:20 +0000 (17:18 -0500)]
drm/amd/display: Fixed kernel panic when booting with DP-to-HDMI dongle
[Why]
In dc_link_is_dp_sink_present, if dal_ddc_open fails, then
dal_gpio_destroy_ddc is called, destroying pin_data and pin_clock. They
are created only on dc_construct, and next aux access will cause a panic.
[How]
Instead of calling dal_gpio_destroy_ddc, call dal_ddc_close.
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Gravenor [Fri, 8 Nov 2019 00:20:00 +0000 (19:20 -0500)]
drm/amd/display: populate bios integrated info for renoir
[Why]
When video_memory_type bw_params->vram_type
is assigned, wedistinguish between Ddr4MemType and LpDdr4MemType.
Because of this we will never report that we are using
LpDdr4MemType and never re-purpose WM set D
[How]
populate bios integrated info for renoir by adding the
revision number for renoir and use that integrated info
table instead of of asic_id to get the vram type
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 7 Nov 2019 20:47:46 +0000 (15:47 -0500)]
drm/amd/display: Program CW5 for tracebuffer for dcn20
[Why]
On dcn21 this is programmed for tracebuffer support but isn't being
programmed on dcn20.
DMCUB execution hits an undefined address
65000000 on tracebuffer
access.
[How]
Program CW5.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 7 Nov 2019 20:29:20 +0000 (15:29 -0500)]
drm/amd/display: Return DMUB_STATUS_OK when autoload unsupported
[Why]
Not having support for autoload isn't an error. If the DMUB firmware
doesn't support it then don't return DMUB_STATUS_INVALID.
[How]
Return DMUB_STATUS_OK when ->is_auto_load_done is NULL.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Thu, 7 Nov 2019 20:26:14 +0000 (15:26 -0500)]
drm/amd/display: Only wait for DMUB phy init on dcn21
[Why]
The wait for PHY init won't finish if the firmware doesn't support it.
[How]
Only hook this functionality up on DCN21 and move it out of DCN20.
For ASIC without support then this should return OK so we don't hang
while waiting in DC.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yongqiang Sun [Thu, 7 Nov 2019 19:41:06 +0000 (14:41 -0500)]
drm/amd/display: Add DMCUB__PG_DONE trace code enum
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lucy Li [Fri, 25 Oct 2019 21:59:32 +0000 (17:59 -0400)]
drm/amd/display: Disable link before reenable
[Why]
Black screen seen after display is disabled then re-enabled.
Caused by difference in link settings when
switching between different resolutions.
[How]
In PnP case, or whenever the display is
still enabled but the driver is unloaded,
disable link before re-enabling with new link settings.
Signed-off-by: Lucy Li <lucy.li@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Paul Hsieh [Fri, 1 Nov 2019 06:41:37 +0000 (14:41 +0800)]
drm/amd/display: Reset PHY in link re-training
[Why]
Link training failed randomly when plugging USB-C display in/out.
[How]
If link training failed, reset PHY in link re-training.
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jaehyun Chung [Thu, 7 Nov 2019 16:16:49 +0000 (11:16 -0500)]
drm/amd/display: Wrong ifdef guards were used around DML validation
[Why]
Wrong guards were causing the debug option not to run.
[How]
Changed the guard to the correct one, matching the rq, ttu, dlg regs struct
members that need to be guarded. Also log a message when validation starts.
Signed-off-by: Jaehyun Chung <jaehyun.chung@amd.com>
Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Joseph Gravenor [Mon, 4 Nov 2019 21:39:35 +0000 (16:39 -0500)]
drm/amd/display: fix DalDramClockChangeLatencyNs override
[why]
pstate_latency_us never gets updated from the hard coded value
in rn_clk_mgr.c
[how]
update the wm table's values before we do calculations with them
Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Thu, 7 Nov 2019 18:06:48 +0000 (13:06 -0500)]
drm/amd/display: Map DSC resources 1-to-1 if numbers of OPPs and DSCs are equal
[why]
On ASICs where number of DSCs is the same as OPPs there's no need
for DSC resource management. Mappping 1-to-1 fixes mode-set- or S3-
-related issues for such platforms.
[how]
Map DSC resources 1-to-1 to pipes only if number of OPPs is the same
as number of DSCs. This will still keep other ASICs working.
A follow-up patch to fix mode-set issues on those ASICs will be
required if testing shows issues with mode set.
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Michael Strauss [Mon, 4 Nov 2019 18:39:20 +0000 (13:39 -0500)]
drm/amd/display: Fix Dali clk mgr construct
[WHY]
Dali is currently being misinterpreted as Renoir,
as a result uses wrong clk mgr constructor
[HOW]
Add check to init Dali as Raven2 before it can be misidentified
Clean up & fix Raven2 & Dali ASIC checks
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Tue, 5 Nov 2019 18:17:30 +0000 (13:17 -0500)]
drm/amd/display: add separate of private hwss functions
[Why]
Some function pointers in the hwss function pointer table are
meant to be hw sequencer entry points to be called from dc.
However some of those function pointers are not meant to
be entry points, but instead used as a code reuse/inheritance
tool called directly by other hwss functions, not by dc.
Therefore, we want a more clear separation of which functions
we determine to be interface functions vs the functions we
use within hwss.
[How]
DC interface functions will be stored in:
struct hw_sequencer_funcs
Functions used within HWSS will be stored in:
struct hwseq_private_funcs
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Anthony Koo [Tue, 5 Nov 2019 18:04:34 +0000 (13:04 -0500)]
drm/amd/display: rename core_dc to dc
[Why]
First, to make code more consistent
Second, to get rid of those scenario where we create a second
local pointer to dc when it's already passed in.
[How]
Rename core_dc to dc
Remove duplicate local pointers to dc
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Eric Yang [Tue, 5 Nov 2019 16:59:38 +0000 (11:59 -0500)]
drm/amd/display: update sr and pstate latencies for Renoir
[Why]
DF team has produced more optimized latency numbers.
[How]
Add sr latencies to the wm table, use different latencies
for different wm sets.
Also fix bb override from registery key for these latencies.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 27 Nov 2019 08:51:22 +0000 (16:51 +0800)]
drm/amdgpu: reduce redundant uvd context lost warning message
Move the print out of uvd instance loop in amdgpu_uvd_suspend
v2: drop unnecessary brackets
v3: grab ras_intr state once for multiple times use
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 25 Oct 2019 09:19:38 +0000 (17:19 +0800)]
drm/amdgpu: clear err_event_athub flag after reset exit
Otherwise next err_event_athub error cannot call gpu reset. And following
resume sequence will not be affected by this flag.
v2: create function to clear amdgpu_ras_in_intr for modularity of ras driver
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Wed, 27 Nov 2019 05:17:17 +0000 (13:17 +0800)]
drm/amdgpu: support full gpu reset workflow when ras err_event_athub occurs
This athub fatal error can be recovered by baco without system-level reboot,
so add a mode to use baco for the recovery. Not affect the default psp reset
situations for now.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 26 Nov 2019 14:12:31 +0000 (22:12 +0800)]
drm/amdgpu: add concurrent baco reset support for XGMI
Currently each XGMI node reset wq does not run in parrallel if bound to same
cpu. Make change to bound the xgmi_reset_work item to different cpus.
XGMI requires all nodes enter into baco within very close proximity before
any node exit baco. So schedule the xgmi_reset_work wq twice for enter/exit
baco respectively.
To use baco for XGMI, PMFW supported for baco on XGMI needs to be involved.
The case that PSP reset and baco reset coexist within an XGMI hive never exist
and is not in the consideration.
v2: define use_baco flag to simplify the code for xgmi baco sequence
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Tue, 26 Nov 2019 09:24:56 +0000 (17:24 +0800)]
drm/amdgpu: enable/disable doorbell interrupt in baco entry/exit helper
This operation is needed when baco entry/exit for ras recovery
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 22 Nov 2019 10:39:11 +0000 (18:39 +0800)]
drm/amdgpu: clear uncorrectable parity error status bit
This should be cleared during every nbif uncorrectable error cleanup work.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Fri, 22 Nov 2019 09:56:47 +0000 (17:56 +0800)]
drm/amdgpu: clear ras controller status registers when interrupt occurs
To fix issue that ras controller interrupt cannot be triggered anymore after
one time nbif uncorrectable error. And error count is stored in nbif ras object
for query.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 25 Nov 2019 04:26:09 +0000 (12:26 +0800)]
drm/amdgpu: export amdgpu_ras_find_obj to use externally
Change it to external interface.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Le Ma [Mon, 21 Oct 2019 18:41:26 +0000 (02:41 +0800)]
drm/amdgpu: remove ras global recovery handling from ras_controller_int handler
v2: add notification when ras controller interrupt generates
Signed-off-by: Le Ma <Le.Ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Pierre-Eric Pelloux-Prayer [Thu, 28 Nov 2019 11:08:58 +0000 (12:08 +0100)]
drm/amdgpu: add cache flush workaround to gfx8 emit_fence
The same workaround is used for gfx7.
Both PAL and Mesa use it for gfx8 too, so port this commit to
gfx_v8_0_ring_emit_fence_gfx.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 5 Dec 2019 03:07:49 +0000 (22:07 -0500)]
drm/amdgpu: add header line for power profile on Arcturus
So the output is consistent with other asics.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Fri, 8 Nov 2019 05:30:49 +0000 (00:30 -0500)]
drm/amdkfd: Eliminate unnecessary kernel queue function pointers
Up to this point, those functions are all the same for all ASICs, so
no need to call them by functions pointers. Removing the function
pointers will greatly increase the code readablity. If there is ever
need for those function pointers, we can add it back then.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 3 Dec 2019 20:40:10 +0000 (15:40 -0500)]
drm/amdgpu/gfx: Improvement on EDC GPR workarounds
SPI limits total CS waves in flight per SE to no more than 32 * num_cu and
we need to stuff 40 waves on a CU to completely clean the SGPR. This is
accomplished in the WR by cleaning the SE in two steps, half of the CU per
step.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Guchun Chen [Wed, 4 Dec 2019 07:51:16 +0000 (15:51 +0800)]
drm/amdgpu: add check before enabling/disabling broadcast mode
When security violation from new vbios happens, data fabric is
risky to stop working. So prevent the direct access to DF
mmFabricConfigAccessControl from the new vbios and onwards.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 26 Nov 2019 14:41:46 +0000 (09:41 -0500)]
drm/radeon: fix r1xx/r2xx register checker for POT textures
Shift and mask were reversed. Noticed by chance.
Tested-by: Meelis Roos <mroos@linux.ee>
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Zhan Liu [Tue, 3 Dec 2019 17:46:01 +0000 (12:46 -0500)]
drm/amd/display: Loading NV10/14 Bounding Box Data Directly From Code
[Why]
NV10/14 has released. Its time to get NV10/14 bounding box
directly from code.
[How]
Retrieve NV10/14 bounding box data directly from code.
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Tue, 3 Dec 2019 04:12:10 +0000 (23:12 -0500)]
drm/amdkfd: Contain MMHUB number in mmhub_v9_4_setup_vm_pt_regs()
Adjust the exposed function prototype so that the caller does not need
to know the MMHUB number.
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Mon, 2 Dec 2019 07:04:35 +0000 (15:04 +0800)]
drm/amdgpu/powerplay: unify smu send message function
Drop smu_send_smc_msg function from ASIC specify structure.
Reuse smu_send_smc_msg_with_param function for smu_send_smc_msg.
Set paramer to 0 for smu_send_msg function, otherwise it will send
with previous paramer value (Not a certain value).
Materialize msg type for smu send message function definition.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 2 Dec 2019 05:44:38 +0000 (13:44 +0800)]
drm/amdgpu: load np fw prior before loading the TAs
Platform TAs will independently toggle DF Cstate.
for instance, get/set topology from xgmi ta. do error
injection from ras ta. In such case, PMFW needs to be
loaded before TAs so that all the subsequent Cstate
calls recieved by PSP FW can be routed to PMFW.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 2 Dec 2019 05:37:42 +0000 (13:37 +0800)]
drm/amdgpu: unload asd in psp hw de-init phase
issue unload_ta_cmd to tOS to unload asd driver
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Mon, 2 Dec 2019 05:16:09 +0000 (13:16 +0800)]
drm/amdgpu: drop asd shared memory
asd shared memory is not needed since drivers doesn't
invoke any further cmd to asd directly after the asd
loading. trust application is the one who needs
to talk to asd after the initialization
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Mon, 2 Dec 2019 10:41:36 +0000 (18:41 +0800)]
amd/amdgpu/sriov swSMU disable for sriov
For boards greater than ARCTURUS, and under sriov platform,
swSMU is not supported because smu ip block is commented at
guest driver.
Generally for sriov, initialization of smu is moved to host driver.
Thus, smu sw_init and hw_init will not be executed at guest driver.
Without sw structure being initialized in guest driver, swSMU cannot
declare to be supported.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Mon, 2 Dec 2019 15:47:38 +0000 (15:47 +0000)]
drm/amd/display: remove redundant assignment to variable v_total
The variable v_total is being initialized with a value that is never
read and it is being updated later with a new value. The initialization
is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Thu, 28 Nov 2019 02:31:40 +0000 (10:31 +0800)]
drm/amd/display: Remove unneeded semicolon in display_rq_dlg_calc_21.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:1525:144-145: Unneeded semicolon
drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c:1526:142-143: Unneeded semicolon
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Thu, 28 Nov 2019 02:31:39 +0000 (10:31 +0800)]
drm/amd/display: Remove unneeded semicolon in hdcp.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/modules/hdcp/hdcp.c:506:2-3: Unneeded semicolon
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Thu, 28 Nov 2019 02:31:38 +0000 (10:31 +0800)]
drm/amd/display: Remove unneeded semicolon in bios_parser2.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c:995:2-3: Unneeded semicolon
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Thu, 28 Nov 2019 02:31:37 +0000 (10:31 +0800)]
drm/amd/display: Remove unneeded semicolon in bios_parser.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c:2192:2-3: Unneeded semicolon
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Wed, 27 Nov 2019 09:33:42 +0000 (17:33 +0800)]
drm/amd/powerplay: Remove unneeded variable 'ret' in amdgpu_smu.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c:1192:5-8: Unneeded variable: "ret". Return "0" on line 1195
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c:1945:5-8: Unneeded variable: "ret". Return "0" on line 1961
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Wed, 27 Nov 2019 09:33:41 +0000 (17:33 +0800)]
drm/amd/powerplay: Remove unneeded variable 'result' in vega12_hwmgr.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c:502:5-11: Unneeded variable: "result". Return "0" on line 515
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Wed, 27 Nov 2019 09:33:40 +0000 (17:33 +0800)]
drm/amd/powerplay: Remove unneeded variable 'ret' in smu7_hwmgr.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:5188:5-8: Unneeded variable: "ret". Return "0" on line 5196
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Wed, 27 Nov 2019 09:33:39 +0000 (17:33 +0800)]
drm/amd/powerplay: Remove unneeded variable 'result' in vega10_hwmgr.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c:4363:5-11: Unneeded variable: "result". Return "0" on line 4370
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Wed, 27 Nov 2019 09:33:38 +0000 (17:33 +0800)]
drm/amd/powerplay: Remove unneeded variable 'result' in smu10_hwmgr.c
Fixes coccicheck warning:
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c:1154:5-11: Unneeded variable: "result". Return "0" on line 1159
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Wed, 20 Nov 2019 17:22:42 +0000 (17:22 +0000)]
drm/amd/display: fix double assignment to msg_id field
The msg_id field is being assigned twice. Fix this by replacing the second
assignment with an assignment to msg_size.
Addresses-Coverity: ("Unused value")
Fixes:
11a00965d261 ("drm/amd/display: Add PSP block to verify HDCP2.2 steps")
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 15 Nov 2019 15:02:44 +0000 (10:02 -0500)]
drm/amd/display: re-enable wait in pipelock, but add timeout
Removing this causes hangs in some games, so re-add it, but add
a timeout so we don't hang while switching flip types.
Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205169
Bug: https://bugs.freedesktop.org/show_bug.cgi?id=112266
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhan liu [Mon, 2 Dec 2019 20:12:27 +0000 (15:12 -0500)]
drm/amd/display: Get NV14 specific ip params as needed
[Why]
NV14 is using its own ip params that's different from other
DCN2.0 ASICs.
[How]
Add ASIC revision check to make sure NV14 gets correct
ip params.
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhan liu [Mon, 2 Dec 2019 19:54:16 +0000 (14:54 -0500)]
drm/amd/display: Adding NV14 IP Parameters
[Why]
NV14 IP Parameters are missing.
[How]
Add IP Parameters in.
Signed-off-by: Zhan liu <zhan.liu@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily Deng [Mon, 2 Dec 2019 17:53:10 +0000 (01:53 +0800)]
drm/amdgpu/sriov: No need the event 3 and 4 now
As will call unload kms when initialize fail, and the unload kms will
send event 3 and 4, so don't need event 3 and 4 in device init.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Mon, 2 Dec 2019 09:57:25 +0000 (17:57 +0800)]
drm/amdgpu: Added ASIC specific checks in gfxhub V1.1 get XGMI info
Added max hive/node info checks per supported ASIC
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Fri, 8 Nov 2019 21:57:21 +0000 (16:57 -0500)]
drm/amd/display: Load TA firmware for navi10/12/14
load the ta firmware for navi10/12/14.
This is already being done for raven/picasso and
is needed for supporting hdcp on navi
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yintian Tao [Fri, 29 Nov 2019 08:05:55 +0000 (16:05 +0800)]
drm/amdgpu: not remove sysfs if not create sysfs
When load amdgpu failed before create pm_sysfs and ucode_sysfs,
the pm_sysfs and ucode_sysfs should not be removed.
Otherwise, there will be warning call trace just like below.
[ 24.836386] [drm] VCE initialized successfully.
[ 24.841352] amdgpu 0000:00:07.0: amdgpu_device_ip_init failed
[ 25.370383] amdgpu 0000:00:07.0: Fatal error during GPU init
[ 25.889575] [drm] amdgpu: finishing device.
[ 26.069128] amdgpu 0000:00:07.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_2.1.0 test failed (-110)
[ 26.070110] [drm:gfx_v9_0_hw_fini [amdgpu]] *ERROR* KCQ disable failed
[ 26.200309] [TTM] Finalizing pool allocator
[ 26.200314] [TTM] Finalizing DMA pool allocator
[ 26.200349] [TTM] Zone kernel: Used memory at exit: 0 KiB
[ 26.200351] [TTM] Zone dma32: Used memory at exit: 0 KiB
[ 26.200353] [drm] amdgpu: ttm finalized
[ 26.205329] ------------[ cut here ]------------
[ 26.205330] sysfs group 'fw_version' not found for kobject '0000:00:07.0'
[ 26.205347] WARNING: CPU: 0 PID: 1228 at fs/sysfs/group.c:256 sysfs_remove_group+0x80/0x90
[ 26.205348] Modules linked in: amdgpu(OE+) gpu_sched(OE) ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache binfmt_misc snd_hda_codec_generic ledtrig_audio crct10dif_pclmul snd_hda_intel crc32_pclmul snd_hda_codec ghash_clmulni_intel snd_hda_core snd_hwdep snd_pcm snd_timer input_leds snd joydev soundcore serio_raw pcspkr evbug aesni_intel aes_x86_64 crypto_simd cryptd mac_hid glue_helper sunrpc ip_tables x_tables autofs4 8139too psmouse 8139cp mii i2c_piix4 pata_acpi floppy
[ 26.205369] CPU: 0 PID: 1228 Comm: modprobe Tainted: G OE 5.2.0-rc1 #1
[ 26.205370] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014
[ 26.205372] RIP: 0010:sysfs_remove_group+0x80/0x90
[ 26.205374] Code: e8 35 b9 ff ff 5b 41 5c 41 5d 5d c3 48 89 df e8 f6 b5 ff ff eb c6 49 8b 55 00 49 8b 34 24 48 c7 c7 48 7a 70 98 e8 60 63 d3 ff <0f> 0b eb d7 66 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55
[ 26.205375] RSP: 0018:
ffffbee242b0b908 EFLAGS:
00010282
[ 26.205376] RAX:
0000000000000000 RBX:
0000000000000000 RCX:
0000000000000006
[ 26.205377] RDX:
0000000000000007 RSI:
0000000000000092 RDI:
ffff97ad6f817380
[ 26.205377] RBP:
ffffbee242b0b920 R08:
ffffffff98f520c4 R09:
00000000000002b3
[ 26.205378] R10:
ffffbee242b0b8f8 R11:
00000000000002b3 R12:
ffffffffc0e58240
[ 26.205379] R13:
ffff97ad6d1fe0b0 R14:
ffff97ad4db954c8 R15:
ffff97ad4db7fff0
[ 26.205380] FS:
00007ff3d8a1c4c0(0000) GS:
ffff97ad6f800000(0000) knlGS:
0000000000000000
[ 26.205381] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 26.205381] CR2:
00007f9b2ef1df04 CR3:
000000042aab8001 CR4:
00000000003606f0
[ 26.205384] DR0:
0000000000000000 DR1:
0000000000000000 DR2:
0000000000000000
[ 26.205385] DR3:
0000000000000000 DR6:
00000000fffe0ff0 DR7:
0000000000000400
[ 26.205385] Call Trace:
[ 26.205461] amdgpu_ucode_sysfs_fini+0x18/0x20 [amdgpu]
[ 26.205518] amdgpu_device_fini+0x3b4/0x560 [amdgpu]
[ 26.205573] amdgpu_driver_unload_kms+0x4f/0xa0 [amdgpu]
[ 26.205623] amdgpu_driver_load_kms+0xcd/0x250 [amdgpu]
[ 26.205637] drm_dev_register+0x12b/0x1c0 [drm]
[ 26.205695] amdgpu_pci_probe+0x12a/0x1e0 [amdgpu]
[ 26.205699] local_pci_probe+0x47/0xa0
[ 26.205701] pci_device_probe+0x106/0x1b0
[ 26.205704] really_probe+0x21a/0x3f0
[ 26.205706] driver_probe_device+0x11c/0x140
[ 26.205707] device_driver_attach+0x58/0x60
[ 26.205709] __driver_attach+0xc3/0x140
Signed-off-by: Yintian Tao <yttao@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nirmoy Das <nirmoy.das@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 26 Nov 2019 11:33:38 +0000 (19:33 +0800)]
drm/amdgpu: fix GFX10 missing CSIB set(v3)
still need to init csb even for SRIOV
v2:
drop init_pg() for gfx10 at all since
PG and GFX off feature will be fully controled
by RLC and SMU fw for gfx10
v3:
drop the flush_gpu_tlb lines since we consider
it is only usefull in emulation
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Fri, 29 Nov 2019 08:20:51 +0000 (16:20 +0800)]
drm/amdgpu: should stop GFX ring in hw_fini
To align with the scheme from gfx9
disabling GFX ring after VM shutdown could avoid
garbage data be fetched to GFX RB which may lead
to unnecessary screw up on GFX
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 26 Nov 2019 11:38:22 +0000 (19:38 +0800)]
drm/amdgpu: do autoload right after MEC loaded for SRIOV VF
since we don't have RLCG ucode loading and no SRlist as well
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 26 Nov 2019 11:36:29 +0000 (19:36 +0800)]
drm/amdgpu: skip rlc ucode loading for SRIOV gfx10
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 26 Nov 2019 11:42:25 +0000 (19:42 +0800)]
drm/amdgpu: fix calltrace during kmd unload(v3)
issue:
kernel would report a warning from a double unpin
during the driver unloading on the CSB bo
why:
we unpin it during hw_fini, and there will be another
unpin in sw_fini on CSB bo.
fix:
actually we don't need to pin/unpin it during
hw_init/fini since it is created with kernel pinned,
we only need to fullfill the CSB again during hw_init
to prevent CSB/VRAM lost after S3
v2:
get_csb in init_rlc so hw_init() will make CSIB content
back even after reset or s3
v3:
use bo_create_kernel instead of bo_create_reserved for CSB
otherwise the bo_free_kernel() on CSB is not aligned and
would lead to its internal reserve pending there forever
take care of gfx7/8 as well
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Harry Wentland [Thu, 28 Nov 2019 16:30:10 +0000 (11:30 -0500)]
drm/amd/display: Drop AMD_EDID_UTILITY defines
We don't use this upstream in the Linux kernel.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhan Liu [Thu, 28 Nov 2019 19:12:11 +0000 (14:12 -0500)]
drm/amd/display: Include num_vmid and num_dsc within NV14's resource caps
[Why]
"num_vmid" and "num_dsc" are missing within NV14's resource caps structure.
[How]
Add the missing parts.
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Monk Liu [Tue, 26 Nov 2019 11:40:08 +0000 (19:40 +0800)]
drm/amdgpu: use CPU to flush vmhub if sched stopped
otherwse the flush_gpu_tlb will hang if we unload the
KMD becuase the schedulers already stopped
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 26 Nov 2019 19:27:46 +0000 (14:27 -0500)]
drm/amdgpu/gfx: Increase dispatch packet number
For Arcturus, increase dispatch packet number to stress scheduler.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Tue, 26 Nov 2019 19:23:10 +0000 (14:23 -0500)]
drm/amdgpu/gfx: Clear more EDC cnt
Clear SDMA and HDP EDC counter in GPR workarounds.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 6 Nov 2019 13:08:06 +0000 (21:08 +0800)]
drm/amdgpu/gfx10: remove outdated comments
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Xiaojie Yuan [Wed, 6 Nov 2019 13:10:20 +0000 (21:10 +0800)]
drm/amdgpu/gfx10: unlock srbm_mutex after queue programming finish
srbm_mutex is to guarantee atomicity for r/w of gfx indexed registers
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jules Irenge [Tue, 26 Nov 2019 00:35:14 +0000 (00:35 +0000)]
drm: radeon: replace 0 with NULL
Replace 0 with NULL to fix sparse tool warning
warning: Using plain integer as NULL pointer
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dan Carpenter [Tue, 26 Nov 2019 12:10:29 +0000 (15:10 +0300)]
drm/amdgpu: Fix a bug in jpeg_v1_0_start()
Originally the last WREG32_SOC15() was a part of the if statement block
but the curly braces are on the wrong line.
Fixes:
bb0db70f3f75 ("drm/amdgpu: separate JPEG1.0 code out from VCN1.0")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 25 Nov 2019 16:11:18 +0000 (11:11 -0500)]
drm/amdgpu: flag vram lost on baco reset for VI/CIK
VI/CIK BACO was inflight when this fix landed for SOC15/NV.
Add the fix to VI/CIK as well.
Acked-by: Evan Quan <evan.quan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 20 Nov 2019 22:31:11 +0000 (17:31 -0500)]
drm/amdgpu: move pci handling out of pm ops
The documentation says the that PCI core handles this
for you unless you choose to implement it. Just rely
on the PCI core to handle the pci specific bits.
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Zhan liu [Mon, 25 Nov 2019 22:25:18 +0000 (17:25 -0500)]
drm/amd/display: Modify comments to match the code
[Why]
This line of code was modified. However, comments
remained unchanged. As a result, comments and code are
mismatching.
[How]
Modifying comments to reflect code. At the same time,
explaining why the value was changed from 200ms to
3000ms.
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 20 Nov 2019 11:21:35 +0000 (19:21 +0800)]
drm/amdgpu: apply gpr/gds workaround before enabling GFX EDC mode
gfx memory should be initialized before enabling
DED and FUE field in mmGB_EDC_MODE
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Zhang [Tue, 26 Nov 2019 06:47:29 +0000 (14:47 +0800)]
drm/amd/amdgpu/sriov skip jpeg ip block for ARCTURUS VF
Currently ARCTURUS VF doesn't support jpeg ip block.
Skip jpeg ip block in case guest driver load fail.
Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
Reviewed-by: Zhexi Zhang <zhexi.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Mon, 15 Jul 2019 20:18:03 +0000 (16:18 -0400)]
drm/amdgpu: Optimize KFD page table reservation
Be less pessimistic about estimated page table use for KFD. Most
allocations use 2MB pages and therefore need less VRAM for page
tables. This allows more VRAM to be used for applications especially
on large systems with many GPUs and hundreds of GB of system memory.
Example: 8 GPUs with 32GB VRAM each + 256GB system memory = 512GB
Old page table reservation per GPU: 1GB
New page table reservation per GPU: 32MB
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: xinhui pan <xinhui.pan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Felix Kuehling [Mon, 25 Nov 2019 21:25:35 +0000 (16:25 -0500)]
drm/amdgpu: Raise KFD unpinned system memory limit
Allow KFD applications to use more unpinned system memory through
HMM.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Mon, 25 Nov 2019 15:34:13 +0000 (10:34 -0500)]
drm/amd/display: Null check aconnector in event_property_validate
[Why]
previously event_property_validate was only called after we enabled the display.
But after "Refactor HDCP to handle multiple displays per link" this function
can be called at any time. In certain cases we don't have a aconnector
[How]
Null check aconnector and exit early. This is ok because we only need to check the
ENABLED->DESIRED transition if a connector exists.
Fixes:
b1abe5586ffc ("drm/amd/display: Refactor HDCP to handle multiple displays per link")
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Mon, 25 Nov 2019 14:58:43 +0000 (22:58 +0800)]
drm/amd/powerplay: remove set but not used variable 'stretch_amount2'
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:
In function vegam_populate_clock_stretcher_data_table:
drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/vegam_smumgr.c:1489:29:
warning: variable stretch_amount2 set but not used [-Wunused-but-set-variable]
It is never used, so can be removed.
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YueHaibing [Mon, 25 Nov 2019 14:54:45 +0000 (22:54 +0800)]
drm/amd/display: remove set but not used variable 'msg_out'
drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c: In function mod_hdcp_hdcp2_enable_encryption:
drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:633:77: warning: variable msg_out set but not used [-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c: In function mod_hdcp_hdcp2_enable_dp_stream_encryption:
drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:710:77: warning: variable msg_out set but not used [-Wunused-but-set-variable]
It is never used, so remove it.
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timothy Pearson [Sun, 24 Nov 2019 19:15:16 +0000 (13:15 -0600)]
amdgpu: Enable KFD on POWER systems
KFD has been verified to function on POWER systems (Talos II / Vega 64).
It should be available as a kernel configuration option on these systems.
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Fri, 22 Nov 2019 23:15:04 +0000 (23:15 +0000)]
drm/radeon: remove redundant assignment to variable ret
The variable ret is being initialized with a value that is never
read and it is being updated later with a new value. The
initialization is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nathan Chancellor [Sat, 23 Nov 2019 19:23:36 +0000 (12:23 -0700)]
drm/amdgpu: Ensure ret is always initialized when using SOC15_WAIT_ON_RREG
Commit
b0f3cd3191cd ("drm/amdgpu: remove unnecessary JPEG2.0 code from
VCN2.0") introduced a new clang warning in the vcn_v2_0_stop function:
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: warning: variable 'r'
is used uninitialized whenever 'while' loop exits because its condition
is false [-Wsometimes-uninitialized]
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
expanded from macro 'SOC15_WAIT_ON_RREG'
while ((tmp_ & (mask)) != (expected_value)) { \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1083:6: note: uninitialized use
occurs here
if (r)
^
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1082:2: note: remove the
condition if it is always true
SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, r);
^
../drivers/gpu/drm/amd/amdgpu/../amdgpu/soc15_common.h:55:10: note:
expanded from macro 'SOC15_WAIT_ON_RREG'
while ((tmp_ & (mask)) != (expected_value)) { \
^
../drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c:1072:7: note: initialize the
variable 'r' to silence this warning
int r;
^
= 0
1 warning generated.
To prevent warnings like this from happening in the future, make the
SOC15_WAIT_ON_RREG macro initialize its ret variable before the while
loop that can time out. This macro's return value is always checked so
it should set ret in both the success and fail path.
Link: https://github.com/ClangBuiltLinux/linux/issues/776
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nathan Chancellor [Sat, 23 Nov 2019 19:36:39 +0000 (12:36 -0700)]
drm/amd/display: Use NULL for pointer assignment in copy_stream_update_to_stream
Clang warns:
../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1965:26: warning:
expression which evaluates to zero treated as a null pointer constant of
type 'struct dc_dsc_config *' [-Wnon-literal-null-conversion]
update->dsc_config = false;
^~~~~
../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1971:25: warning:
expression which evaluates to zero treated as a null pointer constant of
type 'struct dc_dsc_config *' [-Wnon-literal-null-conversion]
update->dsc_config = false;
^~~~~
2 warnings generated.
Fixes:
f6fe4053b91f ("drm/amd/display: Use a temporary copy of the current state when updating DSC config")
Link: https://github.com/ClangBuiltLinux/linux/issues/777
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Colin Ian King [Fri, 22 Nov 2019 23:04:07 +0000 (23:04 +0000)]
drm/amd/powerplay: remove redundant assignment to variables HiSidd and LoSidd
The variables HiSidd and LoSidd are being initialized with values that
are never read and are being updated a little later with a new value.
The initialization is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 22 Nov 2019 19:16:55 +0000 (14:16 -0500)]
MAINTAINERS: Drop Rex Zhu for amdgpu powerplay
No longer works on the driver.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Krzysztof Kozlowski [Thu, 21 Nov 2019 13:29:30 +0000 (21:29 +0800)]
drm/amd: Fix Kconfig indentation
Adjust indentation from spaces to tab (+optional two spaces) as in
coding style with command like:
$ sed -e 's/^ /\t/' -i */Kconfig
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
John Clements [Mon, 25 Nov 2019 10:24:17 +0000 (18:24 +0800)]
drm/amdgpu: Resolved offchip EEPROM I/O issue
Updated target I2C address
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Oak Zeng [Fri, 22 Nov 2019 20:15:43 +0000 (14:15 -0600)]
drm/amdgpu: Apply noretry setting for mmhub9.4
Config the translation retry behavior according to noretry
kernel parameter
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Suggested-by: Jay Cornwall <Jay.Cornwall@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 19 Nov 2019 20:54:17 +0000 (15:54 -0500)]
drm/amd/display: add default clocks if not able to fetch them
dm_pp_get_clock_levels_by_type needs to add the default clocks
to the powerplay case as well. This was accidently dropped.
Fixes:
b3ea88fef321de ("drm/amd/powerplay: add get_clock_by_type interface for display")
Bug: https://gitlab.freedesktop.org/drm/amd/issues/906
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Fri, 22 Nov 2019 03:42:52 +0000 (11:42 +0800)]
drm/amdgpu: Use ARRAY_SIZE for sos_old_versions
Fixes coccicheck warning:
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c:182:40-41: WARNING: Use ARRAY_SIZE
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
zhengbin [Fri, 22 Nov 2019 03:42:51 +0000 (11:42 +0800)]
drm/amd/powerplay: Use ARRAY_SIZE for smu7_profiling
Fixes coccicheck warning:
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c:4946:28-29: WARNING: Use ARRAY_SIZE
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: zhengbin <zhengbin13@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yong Zhao [Sat, 9 Nov 2019 06:16:05 +0000 (01:16 -0500)]
drm/amdkfd: Remove duplicate functions update_mqd_hiq()
The functions are the same as update_mqd().
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
Reviewed-by: Zhan Liu <zhan.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>