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Tom Stellard [Fri, 20 Jul 2018 17:54:56 +0000 (19:54 +0200)]
radeonsi: Add debug option to enable LLVM GlobalISel (v2)
R600_DEBUG=gisel will tell LLVM to use GlobalISel rather than
SelectionDAG for instruction selection.
v2: mareko: move the helper to src/amd/common
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <tstellar@redhat.com>
Jason Ekstrand [Mon, 23 Jul 2018 16:41:26 +0000 (09:41 -0700)]
intel/compiler: Account for built-in uniforms in analyze_ubo_ranges
The original pass only looked for load_uniform intrinsics but there are
a number of other places that could end up loading a push constant. One
obvious omission was images which always implicitly use a push constant.
Legacy VS clip planes also get pushed into the shader. This fixes some
new Vulkan CTS tests that test random combinations of bindings and, in
particular, test lots of UBOs and images together.
Cc: mesa-stable@lists.freedesktop.org
Cc: Kenneth Graunke <kenneth@whitecape.org>
Daniel Schürmann [Tue, 15 May 2018 15:10:12 +0000 (17:10 +0200)]
radv: enable VK_KHR_16bit_storage extension / 16bit storage features
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Daniel Schürmann [Mon, 16 Jul 2018 18:45:24 +0000 (20:45 +0200)]
ac: add support for 16bit load_push_constant
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Daniel Schürmann [Tue, 15 May 2018 15:09:03 +0000 (17:09 +0200)]
radv: add support for 16bit input/output
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Daniel Schürmann [Tue, 6 Feb 2018 17:53:33 +0000 (18:53 +0100)]
nir: add 16bit type information to glsl types
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Daniel Schürmann [Tue, 15 May 2018 14:01:25 +0000 (16:01 +0200)]
ac: add support for 16bit buffer loads
v2: Fixed dvec3 loads (bas)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Daniel Schürmann [Wed, 7 Feb 2018 18:40:43 +0000 (19:40 +0100)]
ac: add support for 16bit UBO loads
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Daniel Schürmann [Tue, 15 May 2018 09:27:25 +0000 (11:27 +0200)]
ac: add support for 16bit ssbo stores
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Daniel Schürmann [Sat, 3 Feb 2018 13:37:26 +0000 (14:37 +0100)]
ac: add 16bit conversion operations
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Thu, 19 Jul 2018 04:39:15 +0000 (05:39 +0100)]
r600: enable tess_input_info for TES
There might be a nicer way to do this, but this is at least correct.
This fixes:
KHR-GL44.tessellation_shader.single.max_patch_vertices
KHR-GL44.tessellation_shader.tessellation_control_to_tessellation_evaluation.gl_PatchVerticesIn
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Cc: mesa-stable@lists.freedesktop.org
Dave Airlie [Mon, 23 Jul 2018 20:10:06 +0000 (06:10 +1000)]
docs/features: fix virgl gles3.1 entries
Roland Scheidegger [Sat, 21 Jul 2018 23:05:39 +0000 (01:05 +0200)]
draw: force draw pipeline if there's more than 65535 vertices
The pt emit path can only handle 65535 - the number of vertices is
truncated to a ushort, resulting in a too small buffer allocation, which
will crash.
Forcing the pipeline path looks suboptimal, then again this bug is
probably there ever since GS is supported, so it seems it's not
happening often. (Note that the vertex_id in the vertex header is 16
bit too, however this is only used by the draw pipeline, and it denotes
the emit vertex nr, and that uses vbuf code, which will only emit smaller
chunks, so should be fine I think.)
Other solutions would be to simply allow 32bit counts for vertex
allocation, however 65535 is already larger than this was intended for
(the idea being it should be more cache friendly). Or could try to teach
the pt emit path to split the emit in smaller chunks (only the non-index
path can be affected, since gs output is always linear), but it's a bit
tricky (we don't know the primitive boundaries up-front).
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=107295
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Dave Airlie [Mon, 23 Jul 2018 20:05:50 +0000 (06:05 +1000)]
docs/features: note ARB_copy_image is working on virgl
Dave Airlie [Mon, 23 Jul 2018 20:03:03 +0000 (06:03 +1000)]
Revert "virgl: remove unused stride-arguments"
This reverts commit
dc938b8398c0dafb60507e41685f7518b681c24d.
This adds warnings in vtest, and possibly breaks it.
Dave Airlie [Wed, 18 Jul 2018 02:36:04 +0000 (12:36 +1000)]
docs/features: note ssbo and atomic counters done for virgl
Dave Airlie [Tue, 17 Jul 2018 07:24:29 +0000 (17:24 +1000)]
virgl: add initial shader_storage_buffer_object support. (v2)
This adds the guest side support for ARB_shader_storage_buffer_object.
Co-authors: Gurchetan Singh <gurchetansingh@chromium.org>
v2: move to using separate maximums
(fixup macros)
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Jason Ekstrand [Mon, 23 Jul 2018 06:57:07 +0000 (23:57 -0700)]
nir: Add a couple trivial abs optimizations
Spotted in a shader in Batman: Arkham City.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Caio Marcelo de Oliveira Filho [Fri, 20 Jul 2018 20:21:33 +0000 (13:21 -0700)]
glsl: remove delegating constructors to allow build with C++98
Delegating constructors is a C++11 feature, so this was breaking when
compiling with C++98. Change the copy_propagation_state() calls that
used the convenience constructor to use a static member function
instead.
Since copy_propagation_state is expected to be heap allocated, this
change is a good fit.
Tested-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107305
Eric Anholt [Fri, 20 Jul 2018 21:27:09 +0000 (14:27 -0700)]
v3d: Implement a small immediates optimization, based on VC4's.
We can do one per instruction, and we have to be careful not to overwrite
raddr_b, but this greatly reduces the pressure on uniform loads
(particularly around ldvpm/stvpm instructions).
total instructions in shared programs: 90768 -> 88220 (-2.81%)
instructions in affected programs: 82711 -> 80163 (-3.08%)
Eric Anholt [Fri, 20 Jul 2018 21:06:57 +0000 (14:06 -0700)]
v3d: Return an invalid src number if asked for a missing implicit uniform.
Sometimes when iterating over sources, we might want to check if it's the
implicit one. We wouldn't want to match on a non-implicit src using this
function.
Eric Anholt [Fri, 20 Jul 2018 20:31:49 +0000 (13:31 -0700)]
v3d: Skip emitting texture config parameter 2 if it's just the defaults.
shader-db:
total instructions in shared programs: 91275 -> 90768 (-0.56%)
instructions in affected programs: 20702 -> 20195 (-2.45%)
Eric Anholt [Fri, 20 Jul 2018 20:24:53 +0000 (13:24 -0700)]
v3d: Update an XXX comment for a path we handled in HW on V3D 4.x.
Eric Anholt [Fri, 20 Jul 2018 20:06:50 +0000 (13:06 -0700)]
v3d: Switch to using the new SFU instructions on V3D 4.x.
These instructions let us write directly to the phys regfile, instead of
just R4. That lets us avoid moving out of R4 to avoid conflicting with
other SFU results, and to avoid conflicting with thread switches.
There is still an extra instruction of latency, which is not represented
in the scheduler at the moment. If you use the result before it's ready,
the QPU will just stall, unlike the magic R4 mode where you'd read the
previous value. That means that the following shader-db results aren't
quite representative (since we now cause some stalls instead of emitting
nops), but they're impressive enough that I'm happy with the change.
total instructions in shared programs: 95669 -> 91275 (-4.59%)
instructions in affected programs: 82590 -> 78196 (-5.32%)
Eric Anholt [Fri, 20 Jul 2018 19:19:36 +0000 (12:19 -0700)]
v3d: Add QPU pack/unpack for the new SFU instructions.
These instructions allow writing the result to any register, instead of a
special writeback to r4.
Eric Anholt [Fri, 20 Jul 2018 19:43:37 +0000 (12:43 -0700)]
v3d: Fix the name of the "flpop" operation.
Noticed while trying to sort a new op into the appropriate place to match
the documentation.
Eric Anholt [Fri, 20 Jul 2018 19:29:39 +0000 (12:29 -0700)]
v3d: Print the instruction we're testing in the QPU disasm/pack round-trip.
If we fail initial disassembly, it's good to know what instruction it was
that failed.
Eric Anholt [Fri, 20 Jul 2018 19:10:08 +0000 (12:10 -0700)]
v3d: Drop unused vir_SAT() operation.
We lower saturates in NIR.
Eric Anholt [Fri, 20 Jul 2018 19:05:57 +0000 (12:05 -0700)]
v3d: Rotate through registers to improve post-RA scheduling options.
Similarly to VC4's implementation, by not picking r0 immediately upon
freeing it, we give the scheduler more of a chance to fit later writes in
earlier. I'm not clear on whether there's any real cost to picking phys
over accumulators, so keep that behavior for now.
shader-db:
total instructions in shared programs: 96831 -> 95669 (-1.20%)
instructions in affected programs: 77254 -> 76092 (-1.50%)
Eric Anholt [Fri, 20 Jul 2018 18:53:25 +0000 (11:53 -0700)]
v3d: Allow reading from physical regs written in the previous instruction.
This restriction existed in V3D 2.x, but lifting it was a major change in
3.x.
shader-db results:
total instructions in shared programs: 98117 -> 96831 (-1.31%)
instructions in affected programs: 48520 -> 47234 (-2.65%)
Eric Engestrom [Tue, 17 Jul 2018 15:58:22 +0000 (16:58 +0100)]
anv: remove unnecessary runtime copy of static string
It's actually also a bit safer, since now the compiler will warn if
the string is larger than the `.name` array.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Alex Smith [Fri, 20 Jul 2018 10:39:32 +0000 (11:39 +0100)]
anv: Pay attention to VK_ACCESS_MEMORY_(READ|WRITE)_BIT
According to the spec, these should apply to all read/write access
types (so would be equivalent to specifying all other access types
individually). Currently, they were doing nothing.
v2: Handle VK_ACCESS_MEMORY_WRITE_BIT in dstAccessMask.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Erik Faye-Lund [Wed, 18 Jul 2018 10:57:13 +0000 (11:57 +0100)]
virgl: remove unused stride-arguments
The IOCTLs doesn't pass this along, so computing them in the first
place is kinda pointless.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Samuel Pitoiset [Fri, 20 Jul 2018 16:47:03 +0000 (18:47 +0200)]
radv: print a big warning when RADV_TRACE_FILE is set
Users shouldn't use this debugging option except when we
ask them to do!
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Fri, 20 Jul 2018 16:48:07 +0000 (18:48 +0200)]
radv: fix a memleak for merged shaders on GFX9
modules[i] can be NULL for merged shaders but we have to
free the NIR code. radv_can_dump_shader_stats() already handles
if modules[i] is NULL, no need to check it twice.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Jason Ekstrand [Fri, 20 Jul 2018 22:10:57 +0000 (15:10 -0700)]
intel/blorp: Fix blits to R8G8B8_UNORM_SRGB sRGB harder
The first fix attempt contained a nasty typo which somehow didn't get
caught in review. It also didn't work as intended because the sRGB
conversion was happening but then throwing away all but the red channel
because it dind't know it was RGB. Really, it's my fault for trying to
fix a bug without first writing tests. I've now written tests and they
pass with this change. :)
Fixes:
11712b9ca17 "intel/blorp: Fix blits to R8G8B8_UNORM_SRGB"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 11 Jul 2018 23:31:02 +0000 (16:31 -0700)]
anv: Stop setting 3DSTATE_PS_EXTRA::PixelShaderHasUAV
We've had several broadwell hangs that have come down to this bit just
not working correctly. Most recently, we've had a pile of hangs
reported with apps running under DXVK:
https://github.com/doitsujin/dxvk/issues/469
Instead, use the bit that doesn't try to imply weird D3D coherency
things and just force-enables the PS like we want.
cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 20 Jul 2018 21:24:17 +0000 (14:24 -0700)]
anv: Properly handle GetImageSubresourceLayout on complex images
We support mipmapped and arrayed linear images so we need to support
vkGetImageSubresourceLayout on them. Fortunately, it's just a trivial
call into ISL.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Mon, 16 Jul 2018 04:01:40 +0000 (14:01 +1000)]
radeonsi/nir: make use of nir_lower_load_const_to_scalar()
This allows NIR to CSE more operations. LLVM does this also so the
impact is limited, however doing this in NIR allows other opts to
make progress. For example some loops in Civilization Beyond Earth
shaders are unrolled.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Ilia Mirkin [Fri, 20 Jul 2018 21:50:02 +0000 (15:50 -0600)]
anv/gen9: expose VK_EXT_post_depth_coverage
Note that the use of ICMS_INNER_CONSERVATIVE disagrees with the GL driver.
Perhaps it's more performant than ICMS_NORMAL and is otherwise permitted?
Not sure, so I left it as-is.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Ilia Mirkin [Fri, 20 Jul 2018 21:50:01 +0000 (15:50 -0600)]
spirv: add support for SPV_KHR_post_depth_coverage
Allow the capability to be exposed, and convert the new execution mode
into fs state.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Mauro Rossi [Sat, 21 Jul 2018 08:40:32 +0000 (10:40 +0200)]
android: util/disk_cache: fix building errors in gallium drivers
This patch applies the necessary changes in Android.common.mk
as per automake rules, to avoid following building error:
external/mesa/src/gallium/drivers/nouveau/nouveau_screen.c:159:8:
error: implicit declaration of function 'disk_cache_get_function_timestamp'
is invalid in C99 [-Werror,-Wimplicit-function-declaration]
if (disk_cache_get_function_timestamp(nouveau_disk_cache_create,
^
1 error generated.
(v2) -DENABLE_SHADER_CACHE Android cflag is kept, to leave the AS-IS capability enabled
Fixes:
cc10b34 ("util/disk_cache: Fix disk_cache_get_function_timestamp with disabled cache.")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Chih-Wei Huang [Thu, 24 May 2018 07:03:31 +0000 (15:03 +0800)]
Android: fix a missing nir_intrinsics.h error
The commit
76dfed8ae2d5 changed nir_intrinsics.h to be a generated
header, but the corresponding dependency was not updated for Android.
It causes the error:
[ 0% 19/4336] target C: libmesa_pipe_radeonsi <= external/mesa/src/gallium/drivers/radeonsi/si_debug.c
...
In file included from external/mesa/src/gallium/drivers/radeonsi/si_debug.c:25:
In file included from external/mesa/src/gallium/drivers/radeonsi/si_pipe.h:28:
In file included from external/mesa/src/gallium/drivers/radeonsi/si_shader.h:140:
In file included from external/mesa/src/amd/common/ac_llvm_build.h:30:
external/mesa/src/compiler/nir/nir.h:966:10: fatal error: 'nir_intrinsics.h' file not found
^~~~~~~~~~~~~~~~~~
1 error generated.
Fixes:
76dfed8ae2d5 ("nir: mako all the intrinsics")
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Mauro Rossi <issor.oruam@gmail.com>
Bas Nieuwenhuizen [Fri, 20 Jul 2018 17:54:56 +0000 (19:54 +0200)]
nir: Fix end of function without return warning/error.
There always is a continue block, so let us just do unreachable.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Fixes:
8cacf38f527 "nir: Do not use continue block after removing it."
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107312
Danylo Piliaiev [Tue, 10 Jul 2018 08:51:45 +0000 (11:51 +0300)]
st: Sweep NIR after linking phase to free held memory
After optimization passes and many trasfromations most of memory
NIR holds is a garbage which was being freed only after shader deletion.
Freeing it at the end of linking will save memory which would be useful
in case there are a lot of complex shaders being compiled.
The common case for this issue is 32bit game running under Wine.
The cost of the optimization is around ~3-5% of compilation speed
with complex shaders.
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Anholt [Mon, 16 Jul 2018 22:22:57 +0000 (15:22 -0700)]
st/dri: Don't require a dri_format for image creation.
Nothing in EGL_KHR_gl_image.txt seems to let us deny creation based on
formats, and doing so causes many failures in
dEQP-EGL.functional.image.api.*
The NONE value we were protecting from only gets looked at in the
__DRI_IMAGE_ATTRIB_FORMAT and __DRI_IMAGE_ATTRIB_FOURCC queries, which are
used from wayland and gbm (which throw an error cleanly on unknown format)
and DMABUF export.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Eric Anholt [Mon, 16 Jul 2018 23:18:03 +0000 (16:18 -0700)]
egl: Refuse EGL_MESA_image_dma_buf_export if we don't have a DRM fourcc.
The EGL CTS expects that you can make images from all sorts of things,
including things like z16 and s8, which we don't have DRM fourccs for.
Just return an error when trying to export one of those.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Eric Anholt [Mon, 9 Jul 2018 19:41:46 +0000 (12:41 -0700)]
v3d: Fix incorrect handling of two fences created back-to-back.
Recreating our context's syncobj with ALREADY_SIGNALED meant that if you
created two fences in a row, then waiting on the second would succeed
immediately. Instead, export a sync file in the gallium fence (since we
don't have a syncobj clone ioctl), and just create a new syncobj to wait
on whenever we need to.
Noticed while debugging
dEQP-GLES3.functional.fence_sync.client_wait_sync_finish
Eric Anholt [Mon, 9 Jul 2018 20:18:34 +0000 (13:18 -0700)]
v3d: Fix the timeout value passed to drmSyncobjWait().
The API wants an absolute time, so we need to go add gallium's argument to
CLOCK_MONOTONIC.
Eric Anholt [Wed, 18 Jul 2018 19:06:45 +0000 (12:06 -0700)]
v3d: Fix drmSyncobjWait() return value checking even more.
It tends to return >0 in the success case (I think the value is something
like "how much of the timeout remained"). Fixes
dEQP-GLES3.functional.fence_sync.client_wait_sync_finish
Eric Anholt [Tue, 17 Jul 2018 21:33:19 +0000 (14:33 -0700)]
v3d: Use the list_first_entry/list_last_entry macros.
Eric Anholt [Tue, 17 Jul 2018 21:29:41 +0000 (14:29 -0700)]
v3d: Move BO cache counting to dump time instead of cache management.
This is one less way to get the dump stats wrong.
Eric Anholt [Tue, 17 Jul 2018 20:21:58 +0000 (13:21 -0700)]
v3d: Reduce the stale BO reclamation spam with dump_stats set.
This was obviously meant to be when we were actually freeing a BO, not
just when there was at least one BO in the list.
Eric Anholt [Mon, 16 Jul 2018 23:44:58 +0000 (16:44 -0700)]
v3d: Respect a sampler view's first_layer field.
Fixes texturing from EGL images created from cubemap faces, as in
dEQP-EGL.functional.image.create.gles2_cubemap_negative_x_rgba_texture
Sonny Jiang [Wed, 18 Jul 2018 21:48:50 +0000 (17:48 -0400)]
radeonsi: emit_spi_map packets optimization
v2: marek: remove an empty line before break;
rename reg_val_seq -> spi_ps_input_cntl
"type * x" -> "type *x"
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Gert Wollny [Tue, 3 Jul 2018 11:32:21 +0000 (13:32 +0200)]
virgl: Expose GL_ARB_copy_image if host supports it
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Gert Wollny [Thu, 12 Jul 2018 10:55:36 +0000 (12:55 +0200)]
virgl: Allow RGB32* textures only as buffer objects
When requesting a texture of the internal format GL_RGB32F Gallium will
try to allocate a renderable texture and returns RGBA32F or RGBX32F, but
when one requests GL_RGB32I or GL_RGB32UI the according 3-component
texture will be returned. This leads to problems later, when one wants
to use glCopyImageSubData to copy data between these textures that should
be compatible, but given the way virgl and Gallium handle this the latter
fails with an assertion, because the per-texel bit size is different.
By allowing the GL_RGB32* only for texture buffers these problems are avoided
without losing the ARB_tbo_rgb32 extension (thanks Ilia Mirkin).
v2: Correct spelling (Gurchetan Singh)
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Lionel Landwerlin [Fri, 20 Jul 2018 10:20:41 +0000 (11:20 +0100)]
intel: tools: dump: protect against multiple calls on destructor
When running gdb, make sure to pass the LD_PRELOAD variable only to
the executed program, not the debugger. Otherwise the debugger will
run the preloaded constructor/destructor too and bad things will
happen.
Suggested-by: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Lionel Landwerlin [Fri, 20 Jul 2018 10:18:18 +0000 (11:18 +0100)]
intel: tools: dump: make dump tool reliable under gdb
The problem with passing the configuration of the dump lib through a
file descriptor is that it can be read only once. But under gdb you
might want to rerun your program multiple times.
This change hands the configuration through a temporary file that is
deleted once the command line passes to intel_dump_gpu has exited.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Samuel Pitoiset [Fri, 20 Jul 2018 13:07:34 +0000 (15:07 +0200)]
radv: don't flush DB before subpass FS resolves
That shouldn't be needed because the DB state is invalid.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Gert Wollny [Tue, 17 Jul 2018 17:04:09 +0000 (19:04 +0200)]
r600: Correct evaluation of cube array index and face
The array index needs to be corrected and it must be insured that it is
rounded and its value is non-negative before it is combined with the
face id.
v5: Use RNDNE instead of ADD 0.5 and FLOOR (Ilia Mirkin)
v6: Fix type (Roland Scheidegger)
Fixes 182 from android/cts/master/gles31-master.txt:
dEQP-GLES31.functional.texture.filtering.cube_array.formats.*
dEQP-GLES31.functional.texture.filtering.cube_array.sizes.*
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.nearest_mipmap_*
dEQP-GLES31.functional.texture.filtering.cube_array.combinations.linear_mipmap_*
dEQP-GLES31.functional.texture.filtering.cube_array.no_edges_visible.*
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Gert Wollny [Tue, 17 Jul 2018 17:04:08 +0000 (19:04 +0200)]
r600: correct texture offset for array index lookup
Correct the array index for TEXTURE_*1D_ARRAY, and TEXTURE_*2D_ARRAY
The standard says the array index is evaluated according to
floor(z + 0.5)
but RNDNE is sufficient also for the test cases were z is close to 1.5
and it is likely to hit 1.5, the corner case were RNDNE gives a result
different from above formula.
v5: - Use RNDNE instead of ADD 0.5 and FLOOR (Ilia Mirkin)
- update commit message
Fixes 325 tests from android/cts/master/gles3-master.txt:
dEQP-GLES3.functional.shaders.texture_functions.texture.*sampler2darray*
dEQP-GLES3.functional.shaders.texture_functions.textureoffset.*sampler2darray*
dEQP-GLES3.functional.shaders.texture_functions.texturelod.sampler2darray*
dEQP-GLES3.functional.shaders.texture_functions.texturelodoffset.*sampler2darray*
dEQP-GLES3.functional.shaders.texture_functions.texturegrad.*sampler2darray*
dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.*sampler2darray*
dEQP-GLES3.functional.texture.filtering.2d_array.formats.*
dEQP-GLES3.functional.texture.filtering.2d_array.sizes.*
dEQP-GLES3.functional.texture.filtering.2d_array.combinations.*
dEQP-GLES3.functional.texture.shadow.2d_array.*
dEQP-GLES3.functional.texture.vertex.2d_array.*
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Gert Wollny [Tue, 17 Jul 2018 17:04:07 +0000 (19:04 +0200)]
r600: Delay emission of texture gradients and lookup offsets
Gradients used in texture lookups and the offsets must reside in the
same fetch clause (the first is imposed by the hardware and the second
is expected by sb). In order to ensure that no ALU clause is inserted
between emission and use of these, delay the emission of these
instructions until the texture instruction using them is also emitted.
This is needed in preparation for the correction of the texture array
indices.
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Bas Nieuwenhuizen [Wed, 18 Jul 2018 11:58:49 +0000 (13:58 +0200)]
util/disk_cache: Fix disk_cache_get_function_timestamp with disabled cache.
radv always needs it, so just check the header instead. Also
do not declare the function if the variable is not set, so we
get a nice compile error instead of failing to open a device
at runtime.
Fixes:
b87ef9e606a "util: fix MSVC build issue in disk_cache.h"
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Bas Nieuwenhuizen [Sat, 14 Jul 2018 23:19:17 +0000 (01:19 +0200)]
nir: Do not use continue block after removing it.
Reinserting code directly before a jump means the block gets split
and merged, removing the original block and replacing it in the
process.
Hence keeping a pointer to the continue block over a reinsert
causes issues.
This code changes nir_opt_if to simply look for the new continue
block.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107275
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Samuel Pitoiset [Wed, 18 Jul 2018 14:19:07 +0000 (16:19 +0200)]
radv: simplify a condition in radv_src_access_flush()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 18 Jul 2018 14:19:06 +0000 (16:19 +0200)]
radv: save current state just before resolving with FS
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 18 Jul 2018 14:19:05 +0000 (16:19 +0200)]
radv: don't check if a subpass has resolve attachments twice
We already check that in radv_cmd_buffer_resolve_subpass().
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 18 Jul 2018 14:19:04 +0000 (16:19 +0200)]
radv: make use of radv_subpass_barrier() when resolving subpasses
The goal is to use radv_barrier()/radv_subpass_barrier() as
much as possible for further optimizations.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Rhys Perry [Tue, 12 Jun 2018 11:14:14 +0000 (12:14 +0100)]
nv50/ir: move LateAlgebraicOpt back to right after ConstantFolding
total instructions in shared programs :
5480808 ->
5472107 (-0.16%)
total gprs used in shared programs : 647530 -> 647532 (0.00%)
total shared used in shared programs : 389120 -> 389120 (0.00%)
total local used in shared programs : 21064 -> 21064 (0.00%)
total bytes used in shared programs :
58551648 ->
58459352 (-0.16%)
local shared gpr inst bytes
helped 0 0 73 2609 2609
hurt 0 0 71 34 34
Rhys Perry [Tue, 12 Jun 2018 10:43:49 +0000 (11:43 +0100)]
nv50/ir: handle SHLADD in IndirectPropagation
An alternative solution to the problem fixed in
0bd83d0 ("nv50/ir: move LateAlgebraicOpt to the very end").
total instructions in shared programs :
5481195 ->
5480808 (-0.01%)
total gprs used in shared programs : 647535 -> 647530 (-0.00%)
total shared used in shared programs : 389120 -> 389120 (0.00%)
total local used in shared programs : 21064 -> 21064 (0.00%)
total bytes used in shared programs :
58555784 ->
58551648 (-0.01%)
local shared gpr inst bytes
helped 0 0 2 34 34
hurt 0 0 0 0 0
Rhys Perry [Thu, 19 Jul 2018 15:58:46 +0000 (16:58 +0100)]
gm107/ir: use CS2R for SV_CLOCK
This instruction seems to be faster than S2R and requires no barrier,
though the range of special registers it can read from is limited.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Lionel Landwerlin [Wed, 18 Jul 2018 16:38:52 +0000 (17:38 +0100)]
intel: tools: dump: remove mentions of intel_aubdump
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
Lionel Landwerlin [Wed, 18 Jul 2018 16:39:19 +0000 (17:39 +0100)]
intel: tools: aubwrite: fix invalid frees on finish
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Samuel Pitoiset [Thu, 19 Jul 2018 18:27:11 +0000 (20:27 +0200)]
ac/nir: add a workaround for bitfield_extract when count is 0
LLVM 7 returns incorrect results when count is 0, something
has been broken since LLVM 6. Of course, the best solution is
to fix LLVM but this workaround works as expected for now.
Original workaround by Philippe Rebohle.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107276
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nanley Chery [Mon, 16 Jul 2018 22:42:39 +0000 (15:42 -0700)]
intel/isl/gen4: Make depth/stencil buffers Y-Tiled
Rendering to a linear depth buffer on gen4 is causing a GPU hang in the
CI system. Until a better explanation is found, assume that errata is
applicable to all gen4 platforms.
Fixes
fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").
Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Nanley Chery [Mon, 16 Jul 2018 20:03:09 +0000 (13:03 -0700)]
i965/misc: Use depth/stencil surf's tiling on gen4-5
Make the 3D engine aware of the depth/stencil surface's tiling before
doing any render operations.
Fixes
fbe01625f6bf2cef6742e1ff0d3d44a2afec003e
("i965/miptree: Share tiling_flags in miptree_create").
Reported-by: Mark Janes <mark.a.janes@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107248
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Caio Marcelo de Oliveira Filho [Tue, 26 Jun 2018 23:26:46 +0000 (16:26 -0700)]
glsl: don't let an 'if' then-branch kill copy propagation (elements) for else-branch
When handling 'if' in copy propagation elements, if a certain variable
was killed when processing the first branch of the 'if', then the
second would get any propagation from previous nodes.
x = y;
if (...) {
z = x; // This would turn into z = y.
x = 22; // x gets killed.
} else {
w = x; // This would NOT turn into w = y.
}
With the change, we let copy propagation happen independently in the
two branches and only then apply the killed values for the subsequent
code.
One example in shader-db part of shaders/unity/8.shader_test:
(assign (xyz) (var_ref col_1) (var_ref tmpvar_8) )
(if (expression bool < (swiz y (var_ref xlv_TEXCOORD0) )(constant float (0.000000)) ) (
(assign (xyz) (var_ref col_1) (expression vec3 + (var_ref tmpvar_8) ... ) ... )
)
(
(assign (xyz) (var_ref col_1) (expression vec3 lrp (var_ref col_1) ... ) ... )
))
The variable col_1 was replaced by tmpvar_8 in the then-part but not
in the else-part.
NIR deals well with copy propagation, so it already covered for the
missing ones that this patch fixes.
Reviewed-by: Eric Anholt <eric@anholt.net>
Caio Marcelo de Oliveira Filho [Mon, 25 Jun 2018 17:44:56 +0000 (10:44 -0700)]
glsl: change opt_copy_propagation_elements data structures
Instead of keeping multiple acp_entries in lists, have a single
acp_entry per variable. With this, the implementation of clone is more
convenient and now fully implemented. In the previous code, clone was
only partial.
Before this patch, each acp_entry struct represented a write to a
variable including LHS, RHS and a mask of what channels were written
to. There were two main hash tables, the first (lhs_ht) stored a list
of acp_entries per LHS variable, with the values available to copy for
that variable; the second (rhs_ht) was a "reverse index" for the first
hash table, so stored acp_entries per RHS variable.
After the patch, there's a single acp_entry struct per LHS variable,
it contains an array with references to the RHS variables per
channel. There now is a single hash table, from LHS variable to the
corresponding entry. The "reverse index" is stored in the ACP entry,
in the form of a set of variables that copy from the LHS. To make the
clone operation cheaper, the ACP entries are created on demand.
This should not change the result of copy propagation, a later patch
will take advantage of the clone operation.
v2: Add note clarifying how the hashtable is destroyed.
v3: (all from Eric Anholt)
Add remove_unused_var_from_dsts() function for reuse.
Remove from dsts as we go instead of clearing at the end.
Add clarifying comment to erase().
Reviewed-by: Eric Anholt <eric@anholt.net>
Caio Marcelo de Oliveira Filho [Sat, 23 Jun 2018 00:35:23 +0000 (17:35 -0700)]
glsl: separate copy propagation state
Separate higher level logic of visiting instructions and chosing when
to store and use new copy data from the datastructure holding the copy
propagation information. This will also make easier later patches that
change the structure.
v2: Remove empty destructor and clarify how hash tables are destroyed.
Reviewed-by: Eric Anholt <eric@anholt.net>
Lionel Landwerlin [Wed, 18 Jul 2018 17:19:31 +0000 (18:19 +0100)]
intel: tools: dump: trace memory writes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Lionel Landwerlin [Wed, 18 Jul 2018 14:12:57 +0000 (15:12 +0100)]
intel: tools: dump: remove command execution feature
In commit
86cb05a6d35a52 ("intel: aubinator: remove standard input
processing option") we removed the ability to process aub as an input
stream because we're now rely on mmapping the aub file to back the
buffers aubinator is parsing.
intel_aubdump was the provider of the standard input data and since
we've copied/reworked intel_aubdump into intel_dump_gpu within Mesa,
we don't need that code anymore.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Danylo Piliaiev [Wed, 18 Jul 2018 08:47:19 +0000 (11:47 +0300)]
radv: Fix incorrect assumption about ternary operator precedence
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Thu, 19 Jul 2018 05:16:56 +0000 (01:16 -0400)]
mesa: fix make check for AMD_performance_monitor
Marek Olšák [Tue, 17 Jul 2018 03:29:48 +0000 (23:29 -0400)]
mesa: remove dead code from api_loopback
This should only contain functions not set in vtxfmt.c.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Tue, 17 Jul 2018 03:16:31 +0000 (23:16 -0400)]
mesa: expose ARB_indirect_parameters in the compatibility profile
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (v1)
v2: fix dispatch_sanity
Marek Olšák [Tue, 17 Jul 2018 03:14:14 +0000 (23:14 -0400)]
vbo: fix ARB_multi_draw_indirect for the compatibility profile
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Tue, 17 Jul 2018 03:10:17 +0000 (23:10 -0400)]
mesa: expose ARB_shader_viewport_layer_array in the compatibility profile
no changes needed for GL compat
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Tue, 17 Jul 2018 03:09:53 +0000 (23:09 -0400)]
mesa: expose ARB_ES3_1_compatibility in the compatibility profile
no changes needed for GL compat
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Mon, 25 Jun 2018 22:57:08 +0000 (18:57 -0400)]
winsys/amdgpu: remove RADEON_SURF_FMASK leftover
RADEON_SURF_FMASK is never set.
Marek Olšák [Thu, 5 Jul 2018 06:27:45 +0000 (02:27 -0400)]
ac: run LLVM optimization passes only on the final function after inlining
Bas Nieuwenhuizen [Sat, 14 Jul 2018 12:28:23 +0000 (14:28 +0200)]
radv: Enable binning and dfsm by default on Raven.
Seems like it increases performance by 2-3% for some demos and games.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Sat, 14 Jul 2018 12:28:22 +0000 (14:28 +0200)]
radv: Always set disable zpass increment bit when possible.
When no occlusion queries are active even if out of order is enabled.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Sat, 14 Jul 2018 12:28:21 +0000 (14:28 +0200)]
radv: Select correct entries for binning.
Overshot it by one every time.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Sat, 14 Jul 2018 12:28:20 +0000 (14:28 +0200)]
radv: Fix number of samples used for binning.
Used the wrong register ...
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Bas Nieuwenhuizen [Sat, 14 Jul 2018 12:28:19 +0000 (14:28 +0200)]
radv: Disable disabled color buffers in rbplus opts.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Marek Olšák [Wed, 18 Jul 2018 21:47:54 +0000 (17:47 -0400)]
r600: silence the signed overflow warning like radeonsi
r600_gpu_load.c: In function ‘r600_gpu_load_thread’:
../../../../src/util/os_time.h:82:7: warning: assuming signed overflow does not occur when assuming that (X + c) >= X is always true [-Wstrict-overflow]
if (start <= end)
Andres Rodriguez [Wed, 18 Jul 2018 18:18:57 +0000 (14:18 -0400)]
radv: fix wmaybe-uninitialized in radv_meta_fast_clear.c
Assignment and usage of this variable both happen inside an
if(rad_image_has_dcc()) {} blocks. It seems gcc plays it safe and
assumes that both function calls could have different return values.
But in this case we should be safe.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Sonny Jiang [Tue, 17 Jul 2018 14:22:03 +0000 (10:22 -0400)]
radeonsi: emit_guardband packets optimization
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Sonny Jiang [Tue, 17 Jul 2018 14:22:02 +0000 (10:22 -0400)]
radeonsi: Save CLEAR_STATE initial values for optimization
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>