OSDN Git Service
Craig Topper [Wed, 29 Nov 2017 23:08:25 +0000 (23:08 +0000)]
[X86] Remove some questionable looking code that seems to be looking through a VZEXT to create a larger VSEXT.
If the input the vzext was signed this would do the wrong thing.
Not sure how to test this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319382
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Joerg Sonnenberger [Wed, 29 Nov 2017 23:05:56 +0000 (23:05 +0000)]
First step towards more human-friendly PPC assembler output:
- add -ppc-reg-with-percent-prefix option to use %r3 etc as register
names
- split off logic for Darwinish verbose conditional codes into a helper
function
- be explicit about Darwin vs AIX vs GNUish assembler flavors
Based on the patch from Alexandre Yukio Yamashita
Differential Revision: https://reviews.llvm.org/D39016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319381
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Sam Clegg [Wed, 29 Nov 2017 23:05:50 +0000 (23:05 +0000)]
[WebAssembly] Update test expectations for gcc torture tests
I believe these were recently fixed by:
https://reviews.llvm.org/rL319186
Differential Revision: https://reviews.llvm.org/D40619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319380
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Zachary Turner [Wed, 29 Nov 2017 22:41:56 +0000 (22:41 +0000)]
[CodeView] Factor some code out of TypeTableBuilder.
This class had some code that would automatically remap type
indices before hashing and serializing. The only caller of
this method was the TypeStreamMerger anyway, and the method
doesn't make general sense, and prevents making certain future
improvements to the class. So, factoring this up one level
into the TypeStreamMerger where it belongs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319377
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Craig Topper [Wed, 29 Nov 2017 22:15:43 +0000 (22:15 +0000)]
[SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint to insert an assertsext/assertzext based on the original type
If we put in an assertsext/zext here, we're able to generate better truncate code using pack on pre-avx512 targets.
Similar is already done during type legalization. This is the equivalent for op legalization
Differential Revision: https://reviews.llvm.org/D40591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319368
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Dan Gohman [Wed, 29 Nov 2017 20:20:11 +0000 (20:20 +0000)]
[WebAssembly] Fix fptoui lowering bounds
To fully avoid trapping on wasm, fptoui needs a second check to ensure that
the operand isn't below the supported range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319354
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Sam Clegg [Wed, 29 Nov 2017 20:10:14 +0000 (20:10 +0000)]
Add libstd++-4.8 exceptions to ubsan_blacklist.txt
Differential Revision: https://reviews.llvm.org/D40589
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319353
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Krzysztof Parzyszek [Wed, 29 Nov 2017 19:59:29 +0000 (19:59 +0000)]
[Hexagon] Remove HexagonISD::PACKHL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319352
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Krzysztof Parzyszek [Wed, 29 Nov 2017 19:58:10 +0000 (19:58 +0000)]
[Hexagon] Create helpers extractVector and insertVector in lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319351
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Simon Pilgrim [Wed, 29 Nov 2017 19:37:38 +0000 (19:37 +0000)]
[X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)
Accidental commit of incomplete patch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319346
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Zachary Turner [Wed, 29 Nov 2017 19:35:21 +0000 (19:35 +0000)]
Make TypeTableBuilder inherit from TypeCollection.
A couple of places in LLD were passing references to
TypeTableCollections around, which makes it hard to change the
implementation at runtime. However, these cases only needed to
iterate over the types in the collection, and TypeCollection
already provides a handy abstract interface for this purpose.
By implementing this interface, we can get rid of the need to
pass TypeTableBuilder references around, which should allow us
to swap the implementation at runtime in subsequent patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319345
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Zachary Turner [Wed, 29 Nov 2017 19:29:25 +0000 (19:29 +0000)]
Fix line endings in llvm-pdbutil.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319340
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Simon Pilgrim [Wed, 29 Nov 2017 19:19:59 +0000 (19:19 +0000)]
[X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319338
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Simon Pilgrim [Wed, 29 Nov 2017 18:52:20 +0000 (18:52 +0000)]
[X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319337
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Nirav Dave [Wed, 29 Nov 2017 18:06:13 +0000 (18:06 +0000)]
[ARM][DAG] Revert Disable post-legalization store merge for ARM
Partially reverting enabling of post-legalization store merge
(r319036) for just ARM backend as it is causing incorrect code
in some Thumb2 cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319331
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Greg Bedwell [Wed, 29 Nov 2017 18:05:32 +0000 (18:05 +0000)]
[cmake] Replace -Wall with /W4 in clang-cl options now that -Wall aliases -Weverything
Instead, reuse the code-path for cl.exe that adds /W4 , which for clang-cl
aliases clang's "-Wall -Wextra" which matches what clang-cl's /Wall
previously aliased.
This should restore the verbosity of a Windows selfhost build back to
its previous levels.
Differential Revision: https://reviews.llvm.org/D40603
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319330
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Greg Bedwell [Wed, 29 Nov 2017 18:05:26 +0000 (18:05 +0000)]
Make check-lit tests respect LLVM_LIT_TOOLS_DIR
Differential Revision: https://reviews.llvm.org/D40520
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319329
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Zaara Syeda [Wed, 29 Nov 2017 17:26:20 +0000 (17:26 +0000)]
[Power9] add more tests for D38287; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319328
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Sanjay Patel [Wed, 29 Nov 2017 17:21:39 +0000 (17:21 +0000)]
[InstCombine] add tests for select-of-constants; NFC
These are variants of a test that was originally added in:
https://reviews.llvm.org/rL75531
...but removed with:
https://reviews.llvm.org/rL159230
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319327
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Simon Pilgrim [Wed, 29 Nov 2017 17:21:15 +0000 (17:21 +0000)]
[X86][AVX512] Add itinerary argument to all AVX512_maskable_* wrappers. NFCI
All default to NoItinerary
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319326
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Adam Nemet [Wed, 29 Nov 2017 17:07:41 +0000 (17:07 +0000)]
Add opt-viewer testing
Detects whether we have the Python modules (pygments, yaml) required by
opt-viewer and hooks this up to REQUIRES.
This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer
testing).
It's also related to https://github.com/apple/swift/pull/12938 and the idea is
to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake.
Differential Revision: https://reviews.llvm.org/D40202
Fixes since the first commit:
1. Disable syntax highlighting as different versions of pygments generate
different HTML
2. Use llvm-cxxfilt from the build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319324
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Sander de Smalen [Wed, 29 Nov 2017 15:14:39 +0000 (15:14 +0000)]
Reverted r319315 because of unused functions (due to PPR not yet being
used by any instructions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319321
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Simon Pilgrim [Wed, 29 Nov 2017 14:58:34 +0000 (14:58 +0000)]
[X86][AVX512] Tag VPERMILV instruction scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319316
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Sander de Smalen [Wed, 29 Nov 2017 14:34:18 +0000 (14:34 +0000)]
[AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support
Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.
Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, llvm-commits, tschuett
Differential Revision: https://reviews.llvm.org/D40360
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319315
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Diana Picus [Wed, 29 Nov 2017 14:20:06 +0000 (14:20 +0000)]
[ARM GlobalISel] Fix selecting G_BRCOND
When lowering a G_BRCOND, we generate a TSTri of the condition against
1, which sets the flags, and then a Bcc which branches based on the
value of the flags.
Unfortunately, we were using the wrong condition code to check whether
we need to branch (EQ instead of NE), which caused all our branches to
do the opposite of what they were intended to do. This patch fixes the
issue by using the correct condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319313
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Simon Pilgrim [Wed, 29 Nov 2017 13:49:51 +0000 (13:49 +0000)]
[X86][AVX512] Setup unary (PABS/VPLZCNT/VPOPCNT/VPCONFLICT/VMOV*DUP) instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319312
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Dmitry Preobrazhensky [Wed, 29 Nov 2017 13:33:40 +0000 (13:33 +0000)]
[AMDGPU][MC][GFX9] Corrected mapping of GFX9 v_add/sub/subrev_u32
When translating pseudo to MC, v_add/sub/subrev_u32 shall be mapped via a separate table as GFX8 has opcodes with the same names.
These instructions shall also be labelled as renamed for pseudoToMCOpcode to handle them correctly.
Reviewers: arsenm
Differential Revision: https://reviews.llvm.org/D40550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319311
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Simon Pilgrim [Wed, 29 Nov 2017 12:12:27 +0000 (12:12 +0000)]
[X86][SSE] Merged sse2_unpack and sse2_unpack PUNPCK instruction templates. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319310
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Simon Pilgrim [Wed, 29 Nov 2017 11:35:45 +0000 (11:35 +0000)]
[X86][SSE] Merged sse2_pack and sse2_pack_y PACKSS/PACKUS instruction templates. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319308
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Max Kazantsev [Wed, 29 Nov 2017 10:54:16 +0000 (10:54 +0000)]
[SCEV][NFC] Break from loop after we found first non-Phi in getAddRecExprPHILiterally
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319306
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Oliver Stannard [Wed, 29 Nov 2017 10:12:15 +0000 (10:12 +0000)]
[ARM] Add support for armv7e-m to the .arch directive
This will allow compilation of assembly files targeting armv7e-m without having
to specify the Tag_CPU_arch attribute as a workaround.
Differential revision: https://reviews.llvm.org/D40370
Patch by Ian Tessier!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319303
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Serguei Katkov [Wed, 29 Nov 2017 09:48:50 +0000 (09:48 +0000)]
[CGP] Enable complex addr mode
Enable complex addr modes after two critical fixes: rL319109 and rL319292
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319302
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Jonas Paulsson [Wed, 29 Nov 2017 09:16:37 +0000 (09:16 +0000)]
Comment fix in SelectionDAG.h
/// Replace any uses of From with To, leaving
- /// uses of other values produced by From.Val alone.
+ /// uses of other values produced by From.getNode() alone.
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To);
(this is what it says in the .cpp file above this method)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319301
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Craig Topper [Wed, 29 Nov 2017 08:19:36 +0000 (08:19 +0000)]
[X86] Remove setOperationAction Promote for ISD::SINT_TO_FP MVT::v8i16/v16i8/v16i16.
A DAG combine ensures these ops are always promoted to vXi32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319298
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Max Kazantsev [Wed, 29 Nov 2017 06:10:36 +0000 (06:10 +0000)]
[SCEV][NFC] Remove condition that can never happen due to check few lines above
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319293
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Serguei Katkov [Wed, 29 Nov 2017 05:51:26 +0000 (05:51 +0000)]
[CGP] Fix common type handling in optimizeMemoryInst
If common type is different we should bail out due to we will not be
able to create a select or Phi of these values.
Basically it is done in ExtAddrMode::compare however it does not work
if we handle the null first and then two values of different types.
so add a check in initializeMap as well. The check in ExtAddrMode::compare
is used as earlier bail out.
Reviewers: reames, john.brawn
Reviewed By: john.brawn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40479
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319292
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Sean Fertile [Wed, 29 Nov 2017 04:09:29 +0000 (04:09 +0000)]
[PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.
Separate the handling of AND/AND8 out from PHI/OR/ISEL checking. The reasoning
is the others need all their operands to be sign/zero extended for their output
to also be sign/zero extended. This is true for AND and sign-extension, but for
zero-extension we only need at least one of the input operands to be zero
extended for the result to also be zero extended.
Differential Revision: https://reviews.llvm.org/D39078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319289
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Matt Arsenault [Wed, 29 Nov 2017 02:25:14 +0000 (02:25 +0000)]
AMDGPU: Use stricter regexes for add instructions
Match the entire _co as one optional piece rather than
a set of characters to match multiple times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319275
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Bruno Cardoso Lopes [Wed, 29 Nov 2017 01:53:49 +0000 (01:53 +0000)]
[Modules] Add textual headers for recently added .def files
Keep module.modulemap up to date and get rid of -Wincomplete-umbrella warnings
rdar://problem/
35711925
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319273
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Matt Arsenault [Wed, 29 Nov 2017 01:25:12 +0000 (01:25 +0000)]
DAG: Add nuw when splitting loads and stores
The object can't straddle the address space
wrap around, so I think it's OK to assume any
offsets added to the base object pointer can't
overflow. Similar logic already appears to be
applied in SelectionDAGBuilder when lowering
aggregate returns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319272
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Adrian Prantl [Wed, 29 Nov 2017 01:12:22 +0000 (01:12 +0000)]
llvm-dwarfdump: honor the --show-children option when dumping a specific DIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319271
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Matt Arsenault [Wed, 29 Nov 2017 00:55:57 +0000 (00:55 +0000)]
AMDGPU: Select DS insts without m0 initialization
GFX9 stopped using m0 for most DS instructions. Select
a different instruction without the use. I think this will
be less error prone than trying to manually maintain m0
uses as needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319270
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Don Hinton [Wed, 29 Nov 2017 00:47:16 +0000 (00:47 +0000)]
Rollback r319176.
The ';' separators in LLVM_TARGETS_TO_BUILD disappear when list
variables are evaluated in custom commands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319268
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Craig Topper [Wed, 29 Nov 2017 00:32:09 +0000 (00:32 +0000)]
[X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319266
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Zachary Turner [Wed, 29 Nov 2017 00:13:44 +0000 (00:13 +0000)]
Fix a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319263
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Adam Nemet [Wed, 29 Nov 2017 00:10:48 +0000 (00:10 +0000)]
Revert "Add opt-viewer testing"
This reverts commit r319188.
Breaks when c++filt is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319262
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Craig Topper [Wed, 29 Nov 2017 00:02:22 +0000 (00:02 +0000)]
[X86] Add test cases for fptosi v16f32->v16i8/v16i16 to show scalarization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319261
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Zachary Turner [Tue, 28 Nov 2017 23:57:13 +0000 (23:57 +0000)]
[NFC] Minor cleanups in CodeView TypeTableBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319260
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Craig Topper [Tue, 28 Nov 2017 23:56:02 +0000 (23:56 +0000)]
[X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of legal. Fix infinite loop in op legalization when promotion requires 2 steps.
Previously we had an isel pattern to add the truncate. Instead use Promote to add the truncate to the DAG before isel.
The Promote legalization code had to be updated to prevent an infinite loop if promotion took multiple steps because it wasn't remembering the previously tried value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319259
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Craig Topper [Tue, 28 Nov 2017 23:55:59 +0000 (23:55 +0000)]
[X86] Regenerate avx512-schedule test.
For some reason some sqrt instructions were missing the scheduling comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319258
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Matt Arsenault [Tue, 28 Nov 2017 23:40:12 +0000 (23:40 +0000)]
AMDGPU: Enable IPRA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319256
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Simon Pilgrim [Tue, 28 Nov 2017 23:25:42 +0000 (23:25 +0000)]
[X86] Tag CLFLUSHOPT with same scheduling behaviour as CLFLUSH
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319253
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Daniel Sanders [Tue, 28 Nov 2017 23:18:54 +0000 (23:18 +0000)]
[globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal()
Summary:
From the bug report:
> The problem is that it fails when trying to compare -65536 (or
4294901760) to 0xFFFF,0000. This is because the
> constant in the instruction is sign extended to 64 bits (0xFFFF,FFFF,FFFF,0000) and then compared to the non
> extended 64 bit version expected by TableGen.
>
> In contrast, the DAGISelEmitter generates special code for AND immediates (OPC_CheckAndImm), which does not
> sign extend.
This patch doesn't introduce the special case for AND (and OR) immediates since the majority of it is related to handling known bits that have no effect on the result and GlobalISel doesn't detect known-bits at this time. Instead this patch just ensures that the immediate is extended consistently on both sides of the check.
Thanks to Diana Picus for the detailed bug report.
Reviewers: rovka
Reviewed By: rovka
Subscribers: kristof.beyls, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319252
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Simon Pilgrim [Tue, 28 Nov 2017 23:12:12 +0000 (23:12 +0000)]
[X86] Add CLFLUSHOPT schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319250
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Simon Pilgrim [Tue, 28 Nov 2017 23:09:18 +0000 (23:09 +0000)]
[X86][SSE] Add SSE_SHUFP OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.
Will be reused in the AVX512 equivalents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319249
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Simon Pilgrim [Tue, 28 Nov 2017 23:04:42 +0000 (23:04 +0000)]
[X86] Test clflushopt intrinsic on 32 and 64-bit targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319247
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Simon Pilgrim [Tue, 28 Nov 2017 22:55:08 +0000 (22:55 +0000)]
[X86][SSE] Add SSE_UNPCK/SSE_PUNPCK OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.
Will be reused in the AVX512 equivalents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319245
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Simon Pilgrim [Tue, 28 Nov 2017 22:47:45 +0000 (22:47 +0000)]
[X86][SSE] Use SSE_PACK OpndItins in PACKSS/PACKUS instruction definitions
Update multi-classes to take the scheduling OpndItins instead of hard coding it.
SSE_PACK will be reused in the AVX512 equivalents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319243
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Adam Nemet [Tue, 28 Nov 2017 22:39:38 +0000 (22:39 +0000)]
Remove this test
After r319235, we no longer generate this remark.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319242
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Simon Pilgrim [Tue, 28 Nov 2017 22:32:43 +0000 (22:32 +0000)]
Fix VS2017 narrowing conversion warning. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319240
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Craig Topper [Tue, 28 Nov 2017 22:28:23 +0000 (22:28 +0000)]
[X86] Remove unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319239
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Adam Nemet [Tue, 28 Nov 2017 22:11:00 +0000 (22:11 +0000)]
Demote this opt remark to DEBUG.
From a random opt-stat output:
Top 10 remarks:
tailcallelim/tailcall 53%
inline/AlwaysInline 13%
gvn/LoadClobbered 13%
inline/Inlined 8%
inline/TooCostly 2%
inline/NoDefinition 2%
licm/LoadWithLoopInvariantAddressInvalidated 2%
licm/Hoisted 1%
asm-printer/InstructionCount 1%
prologepilog/StackSize 1%
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319235
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Craig Topper [Tue, 28 Nov 2017 22:08:51 +0000 (22:08 +0000)]
[X86] Remove code from combineUIntToFP that tried to favor UINT_TO_FP if legal when zero extending from vXi8/vX816.
The UINT_TO_FP is immediately converted to SINT_TO_FP when the node is re-evaluated because we'll detect that the sign bit is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319234
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Craig Topper [Tue, 28 Nov 2017 22:08:48 +0000 (22:08 +0000)]
[X86] Remove custom lowering for uint_to_fp from vXi8/vXi16.
We have a DAG combine that uses a zero extend that should prevent this from ever occurring now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319233
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Daniel Sanders [Tue, 28 Nov 2017 22:07:05 +0000 (22:07 +0000)]
[globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG.
GIM_CheckNonAtomic has been replaced by GIM_CheckAtomicOrdering to allow it to support a wider
range of orderings. This has then been used to import patterns using nodes such
as atomic_cmp_swap, atomic_swap, and atomic_load_*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319232
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Adrian Prantl [Tue, 28 Nov 2017 21:30:38 +0000 (21:30 +0000)]
SROA: Don't create variable fragments that are outside of the variable.
An alloca may be larger than a variable that is described to be stored
there. Don't create a dbg.value for fragments that are outside of the
variable.
This fixes PR35447.
https://bugs.llvm.org/show_bug.cgi?id=35447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319230
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Don Hinton [Tue, 28 Nov 2017 21:23:30 +0000 (21:23 +0000)]
[cmake] Pass LLVM_USE_LINKER flag when building host tools, e.g.,
LLVM_OPTIMIZED_TABLEGEN=ON, and not crosscompiling.
Differential Revision: https://reviews.llvm.org/D39734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319228
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Alexey Bataev [Tue, 28 Nov 2017 20:48:24 +0000 (20:48 +0000)]
[SLP] Additional test for PR35354, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319224
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Mandeep Singh Grang [Tue, 28 Nov 2017 20:48:10 +0000 (20:48 +0000)]
[Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ordering
Summary:
This fixes failures in the following tests uncovered by D39245:
LLVM :: CodeGen/Hexagon/args.ll
LLVM :: CodeGen/Hexagon/constp-extract.ll
LLVM :: CodeGen/Hexagon/expand-condsets-basic.ll
LLVM :: CodeGen/Hexagon/gp-rel.ll
LLVM :: CodeGen/Hexagon/packetize_cond_inst.ll
LLVM :: CodeGen/Hexagon/simple_addend.ll
LLVM :: CodeGen/Hexagon/swp-stages4.ll
LLVM :: CodeGen/Hexagon/swp-vmult.ll
LLVM :: CodeGen/Hexagon/swp-vsum.ll
LLVM :: MC/Hexagon/align.s
LLVM :: MC/Hexagon/asmMap.s
LLVM :: MC/Hexagon/dis-duplex-p0.s
LLVM :: MC/Hexagon/double-vector-producer.s
LLVM :: MC/Hexagon/inst_select.ll
LLVM :: MC/Hexagon/instructions/j.s
Reviewers: colinl, kparzysz, adasgupt, slarin
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40227
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319223
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Daniel Sanders [Tue, 28 Nov 2017 20:27:59 +0000 (20:27 +0000)]
[aarch64][globalisel] Add missing tests from r319216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319220
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Sean Fertile [Tue, 28 Nov 2017 20:25:58 +0000 (20:25 +0000)]
[PowerPC] Allow tail calls of fastcc functions from C CallingConv functions.
Allow fastcc callees to be tail-called from ccc callers.
Differential Revision: https://reviews.llvm.org/D40355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319218
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Daniel Sanders [Tue, 28 Nov 2017 20:21:15 +0000 (20:21 +0000)]
[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
The IRTranslator cannot generate these instructions at the moment so there's no
issue with not having implemented ISel for them yet. D40092 will add
G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* to the IRTranslator and a
further patch will add support for lowering G_ATOMIC_CMPXCHG_WITH_SUCCESS into
G_ATOMIC_CMPXCHG with an external success check via the `Lower` action.
The separation of G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMIC_CMPXCHG is
to import SelectionDAG rules while still supporting targets that prefer to
custom lower the original LLVM-IR-like operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319216
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Mandeep Singh Grang [Tue, 28 Nov 2017 19:55:54 +0000 (19:55 +0000)]
[SelectionDAG] Make sorting predicate stronger to remove non-deterministic ordering
Summary:
Recommitting this with the correct sorting predicate. The Low field of Clusters is a ConstantInt and
cannot be directly compared. So we needed to invoke slt (signed less than) to compare correctly.
This fixes failures in the following tests uncovered by D39245:
LLVM :: CodeGen/ARM/ifcvt3.ll
LLVM :: CodeGen/ARM/switch-minsize.ll
LLVM :: CodeGen/X86/switch.ll
LLVM :: CodeGen/X86/switch-bt.ll
LLVM :: CodeGen/X86/switch-density.ll
Reviewers: hans, fhahn
Reviewed By: hans
Subscribers: aemerson, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D40541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319210
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Simon Pilgrim [Tue, 28 Nov 2017 19:39:47 +0000 (19:39 +0000)]
[X86][SSE] Add SSE_HADDSUB/SSE_PABS/SSE_PALIGN OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.
Will be reused in the AVX512 equivalents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319209
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Craig Topper [Tue, 28 Nov 2017 19:25:45 +0000 (19:25 +0000)]
[X86] In lowerVectorShuffleAsElementInsertion, if were able to find a scalar i8 or i16 and need to zero extend it, make sure we use a vXi32 type of the full vector width.
Previously, this was hardcoded to v4i32, but if the input type is 256 bits we need to use v8i32.
Fixes PR35443
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319208
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Francis Visoiu Mistrih [Tue, 28 Nov 2017 19:23:39 +0000 (19:23 +0000)]
[CodeGen] Fix doxygen \file comment style
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319207
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Francis Visoiu Mistrih [Tue, 28 Nov 2017 19:15:46 +0000 (19:15 +0000)]
[CodeGen] Fix doxygen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319206
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Sanjay Patel [Tue, 28 Nov 2017 19:13:23 +0000 (19:13 +0000)]
[InstCombine] auto-generate complete test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319205
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Krzysztof Parzyszek [Tue, 28 Nov 2017 19:13:17 +0000 (19:13 +0000)]
[Hexagon] Make sure to zero-extend bytes before building a vector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319204
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Sanjay Patel [Tue, 28 Nov 2017 19:07:28 +0000 (19:07 +0000)]
[InstCombine] auto-generate complete test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319203
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Daniel Sanders [Tue, 28 Nov 2017 18:57:02 +0000 (18:57 +0000)]
[mir] Print/Parse both MOLoad and MOStore when they occur together.
Summary:
They're not always mutually exclusive. read-modify-write atomics are both
at the same time. One example of this is the SWP instructions on AArch64.
Another example is GlobalISel's G_ATOMICRMW_* generic instructions which
will be added in a later patch.
Reviewers: arphaman, aemerson
Reviewed By: aemerson
Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D40157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319202
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Rafael Espindola [Tue, 28 Nov 2017 18:50:08 +0000 (18:50 +0000)]
Fix non assert build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319200
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Hans Wennborg [Tue, 28 Nov 2017 18:44:26 +0000 (18:44 +0000)]
EntryExitInstrumenter: set DebugLocs on the inserted call instructions (PR35412)
Apparently the verifier requires that inlineable calls in a function
with debug info have debug locations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319199
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Zachary Turner [Tue, 28 Nov 2017 18:33:17 +0000 (18:33 +0000)]
[CodeView] Refactor / Rewrite TypeSerializer and TypeTableBuilder.
The motivation behind this patch is that future directions require us to
be able to compute the hash value of records independently of actually
using them for de-duplication.
The current structure of TypeSerializer / TypeTableBuilder being a
single entry point that takes an unserialized type record, and then
hashes and de-duplicates it is not flexible enough to allow this.
At the same time, the existing TypeSerializer is already extremely
complex for this very reason -- it tries to be too many things. In
addition to serializing, hashing, and de-duplicating, ti also supports
splitting up field list records and adding continuations. All of this
functionality crammed into this one class makes it very complicated to
work with and hard to maintain.
To solve all of these problems, I've re-written everything from scratch
and split the functionality into separate pieces that can easily be
reused. The end result is that one class TypeSerializer is turned into 3
new classes SimpleTypeSerializer, ContinuationRecordBuilder, and
TypeTableBuilder, each of which in isolation is simple and
straightforward.
A quick summary of these new classes and their responsibilities are:
- SimpleTypeSerializer : Turns a non-FieldList leaf type into a series of
bytes. Does not do any hashing. Every time you call it, it will
re-serialize and return bytes again. The same instance can be re-used
over and over to avoid re-allocations, and in exchange for this
optimization the bytes returned by the serializer only live until the
caller attempts to serialize a new record.
- ContinuationRecordBuilder : Turns a FieldList-like record into a series
of fragments. Does not do any hashing. Like SimpleTypeSerializer,
returns references to privately owned bytes, so the storage is
invalidated as soon as the caller tries to re-use the instance. Works
equally well for LF_FIELDLIST as it does for LF_METHODLIST, solving a
long-standing theoretical limitation of the previous implementation.
- TypeTableBuilder : Accepts sequences of bytes that the user has already
serialized, and inserts them by de-duplicating with a hash table. For
the sake of convenience and efficiency, this class internally stores a
SimpleTypeSerializer so that it can accept unserialized records. The
same is not true of ContinuationRecordBuilder. The user is required to
create their own instance of ContinuationRecordBuilder.
Differential Revision: https://reviews.llvm.org/D40518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319198
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Simon Pilgrim [Tue, 28 Nov 2017 18:10:29 +0000 (18:10 +0000)]
[X86][X87] Tag FP_TO_INT_IN_MEM pseudos with hasNoSchedulingInfo
We don't need scheduling info for pseudos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319197
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Francis Visoiu Mistrih [Tue, 28 Nov 2017 17:58:43 +0000 (17:58 +0000)]
[CodeGen] Separate MachineOperand implementation from MachineInstr
Move the implementation to its own file.
Differential Revision: https://reviews.llvm.org/D40419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319194
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Francis Visoiu Mistrih [Tue, 28 Nov 2017 17:58:38 +0000 (17:58 +0000)]
[CodeGen] Cleanup MachineOperand
* clang-format
* move doxygen from the implementation to headers
* remove duplicate doxygen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319193
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Konstantin Zhuravlyov [Tue, 28 Nov 2017 17:51:08 +0000 (17:51 +0000)]
AMDGPU: Add num spilled s/vgprs to metadata
This was requested by tools.
Differential Revision: https://reviews.llvm.org/D40321
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319192
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Adam Nemet [Tue, 28 Nov 2017 17:26:28 +0000 (17:26 +0000)]
Add opt-viewer testing
Detects whether we have the Python modules (pygments, yaml) required by
opt-viewer and hooks this up to REQUIRES.
This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer
testing).
It's also related to https://github.com/apple/swift/pull/12938 and the idea is
to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake.
Differential Revision: https://reviews.llvm.org/D40202
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319188
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Francis Visoiu Mistrih [Tue, 28 Nov 2017 17:15:09 +0000 (17:15 +0000)]
[CodeGen] Print register names in lowercase in both MIR and debug output
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.
* Only debug printing is affected. It now follows MIR.
Differential Revision: https://reviews.llvm.org/D40417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319187
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Dan Gohman [Tue, 28 Nov 2017 17:15:03 +0000 (17:15 +0000)]
[WebAssembly] Support bitcasted function addresses with varargs.
Generalize FixFunctionBitcasts to handle varargs functions. This in
particular fixes the case where clang bitcasts away a varargs when
calling a K&R-style function.
This avoids interacting with tricky ABI details because it operates
at the LLVM IR level before varargs ABI details are exposed.
This fixes PR35385.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319186
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Matt Arsenault [Tue, 28 Nov 2017 17:11:30 +0000 (17:11 +0000)]
DAG: Legalize truncstores to illegal int types
Truncate to a legal int type, and produce a new
truncstore from a narrower type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319185
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Simon Pilgrim [Tue, 28 Nov 2017 16:57:20 +0000 (16:57 +0000)]
[X86][X87] Tag FTST x87 instruction scheduler class
Looking through Agner, FTST is very similar to generic float compare behaviour, so I've added them to the existing IIC_FCOMI (WriteFAdd) tags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319184
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Sanjay Patel [Tue, 28 Nov 2017 16:40:30 +0000 (16:40 +0000)]
[InstCombine] add tests from D39421 to show current transforms; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319182
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Francis Visoiu Mistrih [Tue, 28 Nov 2017 16:11:56 +0000 (16:11 +0000)]
[Support] Add unit test for printLowerCase
Add test case for the function added in r319171.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319177
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Don Hinton [Tue, 28 Nov 2017 16:08:57 +0000 (16:08 +0000)]
[cmake] Remove redundant call to cmake when building host tools.
Summary:
Remove the redundant, config-time call to cmake when
building host tools for cross compiles or optimized tablegen..
The config-time call to cmake is redundant because it will always get
called again when the CONFIGURE_LLVM_${target_name} target fires at
build-time. This speeds up initial configuration, but has no affect
on build behavior.
Reviewers: beanz
Reviewed By: beanz
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D40229
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319176
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Simon Pilgrim [Tue, 28 Nov 2017 15:03:42 +0000 (15:03 +0000)]
[X86][X87] Tag FABS/FCHS/FSQRT/FSIN/FCOS x87 instruction scheduler classes
Atom's FABS/FCHS/FSQRT latencies taken from Agner.
Note: I just added FSIN and FCOS to the existing IIC_FSINCOS itinerary, which is actually a more costly instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319175
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Jonas Paulsson [Tue, 28 Nov 2017 14:44:32 +0000 (14:44 +0000)]
Use getStoreSize() in various places instead of 'BitSize >> 3'.
This is needed for cases when the memory access is not as big as the width of
the data type. For instance, storing i1 (1 bit) would be done in a byte (8
bits).
Using 'BitSize >> 3' (or '/ 8') would e.g. give the memory access of an i1 a
size of 0, which for instance makes alias analysis return NoAlias even when
it shouldn't.
There are no tests as this was done as a follow-up to the bugfix for the case
where this was discovered (r318824). This handles more similar cases.
Review: Björn Petterson
https://reviews.llvm.org/D40339
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319173
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Simon Pilgrim [Tue, 28 Nov 2017 14:35:52 +0000 (14:35 +0000)]
[X86][X86] Add some x87 schedule tests
Still missing some instructions: mainly loads/stores/system ops, all flagged as TODO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319172
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Francis Visoiu Mistrih [Tue, 28 Nov 2017 14:22:27 +0000 (14:22 +0000)]
[Support] Merge toLower / toUpper implementations
Merge the ones from StringRef and StringExtras.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319171
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