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Craig Topper [Sun, 30 Oct 2016 00:02:55 +0000 (00:02 +0000)]
[X86] Don't use loadv2i64 on SSE version of PMULHRSW. Use memopv2i64 instead.
This bug was introduced in r285501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285510
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NAKAMURA Takumi [Sat, 29 Oct 2016 23:14:18 +0000 (23:14 +0000)]
NativeFormatting.cpp: Fix build for mingw. Where would writePadding() be?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285509
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Teresa Johnson [Sat, 29 Oct 2016 21:52:23 +0000 (21:52 +0000)]
[ThinLTO] Rename doPromoteLocalToGlobal to shouldPromoteLocalToGlobal (NFC)
Rename as suggested in code review for D26063.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285508
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Teresa Johnson [Sat, 29 Oct 2016 21:31:48 +0000 (21:31 +0000)]
[ThinLTO] Use NoPromote flag in summary during promotion
Summary:
Replace the check of whether a GV has a section with the flag check
in the summary. This is in preparation for using the NoPromote flag
to convey other situations when we can't promote (e.g. locals used in
inline asm).
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26063
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285507
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Peter Collingbourne [Sat, 29 Oct 2016 20:57:12 +0000 (20:57 +0000)]
IR: Remove a no longer needed assert.
This assert was checking for a miscompile in a version of GCC that
we no longer support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285506
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Craig Topper [Sat, 29 Oct 2016 18:41:45 +0000 (18:41 +0000)]
[X86] Use intrinsics table for VPMULHRSW intrincis so that the legacy intrinsics can select EVEX encoded instructions when available.
This requires a minor rename of the instructions due to the use of different tablegen classes and how the names are concatenated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285501
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Sanjay Patel [Sat, 29 Oct 2016 16:21:19 +0000 (16:21 +0000)]
[ValueTracking] recognize more variants of smin/smax
Try harder to detect obfuscated min/max patterns: the initial pattern was added with D9352 / rL236202.
There was a bug fix for PR27137 at rL264996, but I think we can do better by folding the corresponding
smax pattern and commuted variants.
The codegen tests demonstrate the effect of ValueTracking on the backend via SelectionDAGBuilder. We
can't expose these differences minimally in IR because we don't have smin/smax intrinsics for IR.
Differential Revision: https://reviews.llvm.org/D26091
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285499
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Sanjay Patel [Sat, 29 Oct 2016 16:02:57 +0000 (16:02 +0000)]
[x86] add tests for smin/smax matchSelPattern (D26091)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285498
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Sanjay Patel [Sat, 29 Oct 2016 15:22:04 +0000 (15:22 +0000)]
[InstCombine] re-use bitcasted compare operands in selects (PR28001)
These mixed bitcast patterns show up with SSE/AVX intrinsics because we bitcast function parameters to <2 x i64>.
The bitcasts obfuscate the expected min/max forms as shown in PR28001:
https://llvm.org/bugs/show_bug.cgi?id=28001#c6
Differential Revision: https://reviews.llvm.org/D25943
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285495
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Simon Pilgrim [Sat, 29 Oct 2016 11:29:39 +0000 (11:29 +0000)]
[DAGCombiner] (REAPPLIED) Add vector demanded elements support to computeKnownBits
Currently computeKnownBits returns the common known zero/one bits for all elements of vector data, when we may only be interested in one/some of the elements.
This patch adds a DemandedElts argument that allows us to specify the elements we actually care about. The original computeKnownBits implementation calls with a DemandedElts demanding all elements to match current behaviour. Scalar types set this to 1.
The approach was found to be easier than trying to add a per-element known bits solution, for a similar usefulness given the combines where computeKnownBits is typically used.
I've only added support for a few opcodes so far (the ones that have proven straightforward to test), all others will default to demanding all elements but can be updated in due course.
DemandedElts support could similarly be added to computeKnownBitsForTargetNode in a future commit.
This looked like this had caused compile time regressions on some buildbots (and was reverted in rL285381), but appears to have just been a harmless bystander!
Differential Revision: https://reviews.llvm.org/D25691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285494
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Elena Demikhovsky [Sat, 29 Oct 2016 08:44:46 +0000 (08:44 +0000)]
Fixed FMA + FNEG combine.
Masked form of FMA should be omitted in this optimization.
Differential Revision: https://reviews.llvm.org/D25984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285492
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Matt Arsenault [Sat, 29 Oct 2016 04:05:06 +0000 (04:05 +0000)]
AMDGPU: Use 1/2pi inline imm on VI
I'm guessing at how it is supposed to be printed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285490
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Matthias Braun [Sat, 29 Oct 2016 01:03:41 +0000 (01:03 +0000)]
AArch64DeadRegisterDefinitionsPass: Cleanup; NFC
- Fix doxygen file comment
- reduce indentation in loop
- Factor out some common subexpressions
- Move independent helper function out of class
- Fix Changed flag (this is not strictly NFC but a bugfix, but the flag
seems ignored anyway)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285488
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Rui Ueyama [Sat, 29 Oct 2016 00:56:44 +0000 (00:56 +0000)]
Define calculateDbgStreamSize for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285487
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Tim Shen [Sat, 29 Oct 2016 00:51:41 +0000 (00:51 +0000)]
[APFloat] Remove the redundent function body of uninitialized ctor, which should be done in r285468
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285486
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Zachary Turner [Sat, 29 Oct 2016 00:27:22 +0000 (00:27 +0000)]
Resubmit "Add support for advanced number formatting."
This resubmits r284436 and r284437, which were reverted in
r284462 as they were breaking the AArch64 buildbot.
The breakage on AArch64 turned out to be a miscompile which is
still not fixed, but is actively tracked at llvm.org/pr30748.
This resubmission re-writes the code in a way so as to make the
miscompile not happen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285483
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Rui Ueyama [Fri, 28 Oct 2016 23:57:37 +0000 (23:57 +0000)]
Do not print out Flags field twice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285481
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Davide Italiano [Fri, 28 Oct 2016 23:55:32 +0000 (23:55 +0000)]
[DAGCombiner] Fix a crash visiting `AND` nodes.
Instead of asserting that the shift count is != 0 we just bail out
as it's not profitable trying to optimize a node which will be
removed anyway.
Differential Revision: https://reviews.llvm.org/D26098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285480
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Tom Stellard [Fri, 28 Oct 2016 23:53:48 +0000 (23:53 +0000)]
AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructions
Summary:
Flat instruction can return out of order, so we need always need to wait
for all the outstanding flat operations.
Reviewers: tony-tye, arsenm
Subscribers: kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl
Differential Revision: https://reviews.llvm.org/D25998
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285479
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Matt Arsenault [Fri, 28 Oct 2016 23:00:38 +0000 (23:00 +0000)]
AMDGPU: Fix instruction flags for s_endpgm
Set isReturn, remove hasSideEffects. Also remove
hasCtrlDep, I'm not really sure what that does.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285476
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Adrian Prantl [Fri, 28 Oct 2016 22:57:02 +0000 (22:57 +0000)]
Refactor DW_LNE_* into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285475
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Adrian Prantl [Fri, 28 Oct 2016 22:56:59 +0000 (22:56 +0000)]
Refactor DW_LNS_* into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285474
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Adrian Prantl [Fri, 28 Oct 2016 22:56:56 +0000 (22:56 +0000)]
Refactor DW_APPLE_PROPERTY_* into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285473
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Adrian Prantl [Fri, 28 Oct 2016 22:56:53 +0000 (22:56 +0000)]
Refactor DW_CFA_* into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285472
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Adrian Prantl [Fri, 28 Oct 2016 22:56:50 +0000 (22:56 +0000)]
Remove whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285471
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Adrian Prantl [Fri, 28 Oct 2016 22:56:45 +0000 (22:56 +0000)]
Refactor all DW_FORM_* constants into Dwarf.def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285470
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Tim Shen [Fri, 28 Oct 2016 22:45:33 +0000 (22:45 +0000)]
[APFloat] Fix memory bugs revealed by MSan
Reviewers: eugenis, hfinkel, kbarton, iteratee, echristo
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D26102
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285468
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Justin Bogner [Fri, 28 Oct 2016 22:42:54 +0000 (22:42 +0000)]
SDAG: Make sure we use an allocatable reg class when we create this vreg
As per the discussion on r280783, if constrainRegClass fails we need
to call getAllocatableClass like we did before that commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285467
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Kostya Serebryany [Fri, 28 Oct 2016 22:03:54 +0000 (22:03 +0000)]
[libFuzzer] mention one more trophie
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285465
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Justin Lebar [Fri, 28 Oct 2016 21:56:07 +0000 (21:56 +0000)]
Add missing lit.local.cfg to llvm/test/Transforms/CodeGenPrepare/NVPTX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285464
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Matt Arsenault [Fri, 28 Oct 2016 21:55:15 +0000 (21:55 +0000)]
AMDGPU: Add definitions for scalar store instructions
Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.
This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285463
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Matt Arsenault [Fri, 28 Oct 2016 21:55:08 +0000 (21:55 +0000)]
AMDGPU: Rename glc operand type
While trying to add the glc bit to SMEM instructions on VI
with the new refactoring I ran into some kind of shadowing
problem for the glc operand when using the pseudoinstruction
as a multiclass parameter.
Everywhere that currently uses it defines the operand to have the same
name as its type, i.e. glc:$glc which works. For some reason now it
conflicts, and its up evaluating to the wrong thing. For the
real encoding classes,
let Inst{16} = !if(ps.has_glc, glc, ?); was not being evaluated
and still visible in the Inst initializer in the expanded td file.
In other cases I got a a different error about an illegal operand
where this was using { 0 } initializer from the bits<1> glc initializer
instead of evaluating it as false in the if.
For consistency all of the operand types should probably
be captialized to avoid conflicting with the variable names
unless somebody has a better idea of how to fix this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285462
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Justin Lebar [Fri, 28 Oct 2016 21:44:00 +0000 (21:44 +0000)]
[NVPTX] Compute 'rem' using the result of 'div', if possible.
Summary:
In isel, transform
Num % Den
into
Num - (Num / Den) * Den
if the result of Num / Den is already available.
Reviewers: tra
Subscribers: hfinkel, llvm-commits, jholewinski
Differential Revision: https://reviews.llvm.org/D26090
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285461
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Justin Lebar [Fri, 28 Oct 2016 21:43:54 +0000 (21:43 +0000)]
Don't leave unused divs/rems sitting around in BypassSlowDivision.
Summary:
This "pass" eagerly creates div and rem instructions even when only one
is needed -- it relies on a later pass (machine DCE?) to clean them up.
This is problematic not just from a cleanliness perspective (this pass
is running during CodeGenPrepare, so should leave the IR in a better
state), but it also creates a problem for instruction selection. If we
always have a div+rem, isel will always select a divrem instruction (if
possible), even when a single div or rem would do.
Specifically, in NVPTX, we want to compute rem from the output of div,
if available. But if a div is not available, we want to leave the rem
alone. This transformation is overeager if div is always available.
Because this code runs as part of CodeGenPrepare, it's nontrivial to
write a test for this change. But this will effectively be tested by
a later patch which adds the aforementioned change to NVPTX isel.
Reviewers: tra
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285460
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Justin Lebar [Fri, 28 Oct 2016 21:43:51 +0000 (21:43 +0000)]
Don't claim the udiv created in BypassSlowDivision is exact.
Summary:
In BypassSlowDivision's short-dividend path, we would create e.g.
udiv exact i32 %a, %b
"exact" here means that we are asserting that %a is a multiple of %b.
But we have no reason to believe this must be true -- this is just a
bug, as far as I can tell.
Reviewers: tra
Subscribers: jholewinski, llvm-commits
Differential Revision: https://reviews.llvm.org/D26097
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285459
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Justin Bogner [Fri, 28 Oct 2016 20:48:47 +0000 (20:48 +0000)]
cmake: Enable the lto cache when building with -flto=thin on darwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285450
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Matt Arsenault [Fri, 28 Oct 2016 20:33:01 +0000 (20:33 +0000)]
AMDGPU: Change check prefix in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285449
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Adrian Prantl [Fri, 28 Oct 2016 20:32:17 +0000 (20:32 +0000)]
Fix a copy&paste error in the macro definition for HANDLE_DW_MACRO and
HANDLE_DE_RLE. Caught by the LLDB build bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285448
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Matt Arsenault [Fri, 28 Oct 2016 20:31:47 +0000 (20:31 +0000)]
AMDGPU: Diagnose using too many SGPRs
This is possible when using inline asm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285447
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Adrian Prantl [Fri, 28 Oct 2016 20:18:26 +0000 (20:18 +0000)]
Remove redundant prefixes from constants and unbreak the LLDB bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285444
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Tim Shen [Fri, 28 Oct 2016 20:13:06 +0000 (20:13 +0000)]
[APFloat] Use std::move() in move assignment operator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285442
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Krzysztof Parzyszek [Fri, 28 Oct 2016 20:06:37 +0000 (20:06 +0000)]
Handle non-~0 lane masks on live-in registers in LivePhysRegs
When LivePhysRegs adds live-in registers, it recognizes ~0 as a special
lane mask indicating the entire register. If the lane mask is not ~0,
it will only add the subregisters that overlap the specified lane mask.
The problem is that if a live-in register does not have subregisters,
and the lane mask is not ~0, it will not be added to the live set.
(The given lane mask may simply be the lane mask of its register class.)
If a register does not have subregisters, add it to the live set if
the lane mask is non-zero.
Differential Revision: https://reviews.llvm.org/D26094
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285440
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Matt Arsenault [Fri, 28 Oct 2016 20:00:33 +0000 (20:00 +0000)]
SpeculativeExecution: Allow speculating more inst types
Partial step towards removing the whitelist and only
using TTI's cost.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285438
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Matt Arsenault [Fri, 28 Oct 2016 19:43:31 +0000 (19:43 +0000)]
AMDGPU: Fix using incorrect private resource with no allocation
It's possible to have a use of the private resource descriptor or
scratch wave offset registers even though there are no allocated
stack objects. This would result in continuing to use the maximum
number reserved registers. This could go over the number of SGPRs
available on VI, or violate the SGPR limit requested by
the function attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285435
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Nemanja Ivanovic [Fri, 28 Oct 2016 19:38:24 +0000 (19:38 +0000)]
Implement vector count leading/trailing bytes with zero lsb and vector parity
builtins - llvm portion
This patch corresponds to review https://reviews.llvm.org/D26003.
Committing on behalf of Zaara Syeda.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285434
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Teresa Johnson [Fri, 28 Oct 2016 19:36:00 +0000 (19:36 +0000)]
[ThinLTO] Use flags from summary when writing variable summary (NFC)
We already read the flags out of the summary when writing the summary
records for functions and aliases, do the same for variables.
This is an NFC change for now since the flags computed on the fly from
the GlobalValue currently will always match those in the summary
already, but once I send a follow-on patch to set the NoRename flag for
locals in the llvm.used set this becomes a necessary change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285433
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George Burgess IV [Fri, 28 Oct 2016 19:22:46 +0000 (19:22 +0000)]
[MemorySSA] Add const to getClobberingMemoryAccess.
Thanks to bryant for the patch!
Differential Revision: https://reviews.llvm.org/D26086
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285432
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Arnold Schwaighofer [Fri, 28 Oct 2016 19:18:09 +0000 (19:18 +0000)]
Make swift calling convention test specific to armv7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285431
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Sanjay Patel [Fri, 28 Oct 2016 19:08:20 +0000 (19:08 +0000)]
[x86] add tests for missed umin/umax
This is actually a deficiency in ValueTracking's matchSelectPattern(),
but a codegen test is the simplest way to expose the bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285429
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Lang Hames [Fri, 28 Oct 2016 18:24:15 +0000 (18:24 +0000)]
[Error] Unify +Asserts/-Asserts behavior for checked flags in Error/Expected<T>.
(1) Switches to raw pointer and bitmasking operations for Error payload.
(2) Always includes the 'unchecked' bitfield in Expected<T>, even in -Asserts.
(3) Always propagates checked bit status in move-ops for both classes, even in
-Asserts.
This should allow debug programs to link against release libraries without
encountering spurious 'unchecked error' terminations.
Error checks still aren't verified in release mode so this doesn't introduce
any new control flow, but it does require new bit-masking ops in release mode
to preserve the flag values during move ops. I expect the overhead to be
minimal, but if we discover any corner cases where it matters we could fix
this by making flag propagation conditional on a new build option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285426
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Adrian Prantl [Fri, 28 Oct 2016 18:21:39 +0000 (18:21 +0000)]
Move the DWARF attribute constants into Dwarf.def and delete 300 lines of silly code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285425
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Matthias Braun [Fri, 28 Oct 2016 18:05:09 +0000 (18:05 +0000)]
MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285423
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Matthias Braun [Fri, 28 Oct 2016 18:05:05 +0000 (18:05 +0000)]
TargetPassConfig: Move addPass of IPRA RegUsageInfoProp down.
TargetPassConfig::addMachinePasses() does some housekeeping first:
Handling the -print-machineinstrs flag and doing an initial printing
"After Instruction Selection". There is no reason for RegUsageInfoProp
to run before those two steps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285422
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Adrian Prantl [Fri, 28 Oct 2016 17:59:50 +0000 (17:59 +0000)]
Import/update constants from the DWARF 5 public review draft document.
https://reviews.llvm.org/D26051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285421
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Arnold Schwaighofer [Fri, 28 Oct 2016 17:21:05 +0000 (17:21 +0000)]
More swift calling convention tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285417
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Kostya Serebryany [Fri, 28 Oct 2016 16:55:29 +0000 (16:55 +0000)]
[libFuzzer] a bit more docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285415
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Sanjay Patel [Fri, 28 Oct 2016 16:54:03 +0000 (16:54 +0000)]
[InstCombine] move/add tests for smin/smax folds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285414
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Lang Hames [Fri, 28 Oct 2016 16:52:34 +0000 (16:52 +0000)]
[lli] Pass command line arguments in to the orc-lazy JIT.
This brings the LLI orc-lazy JIT's behavior more closely in-line with LLI's
mcjit bahavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285413
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Krzysztof Parzyszek [Fri, 28 Oct 2016 15:50:22 +0000 (15:50 +0000)]
[Hexagon] Maintain kill flags through splitting in expand-condsets
Do not use LiveIntervals to recalculate kills, because that cannot be
done accurately without implicit uses on predicated instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285409
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Tom Stellard [Fri, 28 Oct 2016 15:32:28 +0000 (15:32 +0000)]
[Loads] Fix crash in is isDereferenceableAndAlignedPointer()
Summary:
We were trying to add APInt values with different bit sizes after
visiting an addrspacecast instruction which changed the bit width
of the pointer.
Reviewers: majnemer, hfinkel
Subscribers: hfinkel, wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D24774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285407
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Teresa Johnson [Fri, 28 Oct 2016 15:30:27 +0000 (15:30 +0000)]
[cmake] Temporarily revert enforcement of minimum GCC version increase
Summary:
This is temporary, until bot that builds public facing LLVM
documentation is upgraded. It reverts only the cmake change in r284497,
but leaves the doc changes in place to preserve intent.
Reviewers: aaron.ballman
Subscribers: mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D26078
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285406
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Matthew Simpson [Fri, 28 Oct 2016 14:27:45 +0000 (14:27 +0000)]
[LV] Correct misleading comments in test (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285402
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Simon Pilgrim [Fri, 28 Oct 2016 14:07:44 +0000 (14:07 +0000)]
[SelectionDAG] computeKnownBits - early-out if any BUILD_VECTOR element has no known bits
No need to check the remaining elements - no common known bits are available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285399
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Simon Pilgrim [Fri, 28 Oct 2016 13:42:23 +0000 (13:42 +0000)]
[SelectionDAG] Tidyup UDIV computeKnownBits implementation
No need to clear KnownOne2/KnownZero2 bits as the next call to computeKnownBits will overwrite them anyway
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285398
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Simon Pilgrim [Fri, 28 Oct 2016 13:13:16 +0000 (13:13 +0000)]
[SelectionDAG] Increment computeKnownBits recursion depth for SMIN/SMAX/UMIN/UMAX like all other ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285397
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Igor Laevsky [Fri, 28 Oct 2016 12:57:20 +0000 (12:57 +0000)]
[LCSSA] Perform LCSSA verification only for the current loop nest.
Now LPPassManager will run LCSSA verification only for the top-level loop
which was processed on the current iteration.
Differential Revision: https://reviews.llvm.org/D25873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285394
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Juergen Ributzka [Fri, 28 Oct 2016 04:01:12 +0000 (04:01 +0000)]
Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits"
This seems to have increased LTO compile time bejond 2x of previous builds.
See http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto/10676/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285381
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Davide Italiano [Fri, 28 Oct 2016 02:47:09 +0000 (02:47 +0000)]
[Reassociate] Removing instructions mutates the IR.
Fixes PR 30784. Discussed with Justin, who pointed out that
in the new PassManager infrastructure we can have more fine-grained
control on which analyses we want to preserve, but this is the
best we can do with the current infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285380
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Teresa Johnson [Fri, 28 Oct 2016 02:39:38 +0000 (02:39 +0000)]
[ThinLTO] Create AliasSummary when building index
Summary:
Previously we were creating the alias summary on the fly while writing
the summary to bitcode. This moves the creation of these summaries to
the module summary index builder where we build the rest of the summary
index.
This is going to be necessary for setting the NoRename flag for values
possibly used in inline asm or module level asm.
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285379
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Teresa Johnson [Fri, 28 Oct 2016 02:24:59 +0000 (02:24 +0000)]
[ThinLTO] Rename HasSection to NoRename (NFC)
Summary:
This is in preparation for a change to utilize this flag for symbols
referenced/defined in either inline or module level assembly.
Reviewers: mehdi_amini
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D26048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285376
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Davide Italiano [Fri, 28 Oct 2016 01:41:56 +0000 (01:41 +0000)]
[IR] Clang-format my previous commit. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285375
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Davide Italiano [Fri, 28 Oct 2016 00:53:16 +0000 (00:53 +0000)]
[ConstantFold] Get the correct vector type when folding a getelementptr.
Differential Revision: https://reviews.llvm.org/D26014
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285371
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Tom Stellard [Thu, 27 Oct 2016 23:50:21 +0000 (23:50 +0000)]
AMDGPU/SI: Handle hazard with s_rfe_b64
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285368
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Tom Stellard [Thu, 27 Oct 2016 23:42:29 +0000 (23:42 +0000)]
AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}lane
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285367
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Davide Italiano [Thu, 27 Oct 2016 23:40:19 +0000 (23:40 +0000)]
Remove accidentally commited test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285366
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Davide Italiano [Thu, 27 Oct 2016 23:38:51 +0000 (23:38 +0000)]
[IR] Reintroduce getGEPReturnType(), it will be used in a later patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285365
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Tom Stellard [Thu, 27 Oct 2016 23:28:03 +0000 (23:28 +0000)]
AMDGPU/SI: Fix unused variable warning on non-debug builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285363
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Ekaterina Romanova [Thu, 27 Oct 2016 23:20:19 +0000 (23:20 +0000)]
Reverting back r285355: "Update .debug_line section version information to match DWARF version", while I'm investigating a test failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285362
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Vedant Kumar [Thu, 27 Oct 2016 23:17:51 +0000 (23:17 +0000)]
[Coverage] Darwin: Move __llvm_covmap from __DATA to __LLVM_COV
Programs with very large __llvm_covmap sections may fail to link on
Darwin because because of out-of-range 32-bit RIP relative references.
It isn't possible to work around this by using the large code model
because it isn't supported on Darwin. One solution is to move the
__llvm_covmap section past the end of the __DATA segment.
=== Testing ===
In addition to check-{llvm,clang,profile}, I performed a link test on a
simple object after injecting ~4GB of padding into __llvm_covmap:
@__llvm_coverage_padding = internal constant [
4000000000 x i8] zeroinitializer, section "__LLVM_COV,__llvm_covmap", align 8
(This test is too expensive to check-in.)
=== Backwards Compatibility ===
This patch should not pose any backwards-compatibility concerns. LLVM
is expected to scan all of the sections in a binary for __llvm_covmap,
so changing its segment shouldn't affect anything. I double-checked this
by loading coverage produced by an unpatched compiler with a patched
llvm-cov.
Suggested by Nick Kledzik.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285360
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Tom Stellard [Thu, 27 Oct 2016 23:05:31 +0000 (23:05 +0000)]
AMDGPU/SI: Handle hazard with > 8 byte VMEM stores
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285359
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Tim Shen [Thu, 27 Oct 2016 22:52:40 +0000 (22:52 +0000)]
Reapply r285351 "[APFloat] Add DoubleAPFloat mode to APFloat. NFC." with
a workaround for old clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285358
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Ekaterina Romanova [Thu, 27 Oct 2016 22:37:25 +0000 (22:37 +0000)]
Update .debug_line section version information to match DWARF version.
In the past the compiler always emitted .debug_line version 2, though some opcodes from DWARF 3 (e.g. DW_LNS_set_prologue_end, DW_LNS_set_epilogue_begin or DW_LNS_set_isa) and from DWARF 4 could be emitted by the compiler.
This patch changes version information of .debug_line to exactly match the DWARF version. For .debug_line version 4, a new field maximum_operations_per_instruction is emitted.
Differential Revision: https://reviews.llvm.org/D16697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285355
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Tim Shen [Thu, 27 Oct 2016 21:54:29 +0000 (21:54 +0000)]
Revert "[APFloat] Add DoubleAPFloat mode to APFloat. NFC."
This reverts r285351, since it breaks the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285354
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Kostya Serebryany [Thu, 27 Oct 2016 21:44:37 +0000 (21:44 +0000)]
[libFuzzer] enable use_cmp by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285353
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Tim Shen [Thu, 27 Oct 2016 21:39:51 +0000 (21:39 +0000)]
[APFloat] Add DoubleAPFloat mode to APFloat. NFC.
Summary:
This patch adds DoubleAPFloat mode to APFloat.
Now, an APFloat with semantics PPCDoubleDouble will have DoubleAPFloat layout
(APFloat.U.Double), which contains two underlying APFloats as
PPCDoubleDoubleImpl and IEEEdouble semantics. Currently the IEEEdouble APFloat
is not used, and the first APFloat behaves exactly the same before this change.
This patch consists of three kinds of logics:
1) Construction and destruction of APFloat. Now the ctors, dtor, assign
opertors and factory functions construct different underlying layout
based on the semantics passed in.
2) s/IEEE/getIEEE()/ for normal, lifetime-unrelated computation functions.
These functions only access Floats[0] in DoubleAPFloat, which is the
same as today's semantic.
3) A "Double dispatch" function, APFloat::convert. Converting between two
different layouts requires appropriate logic.
Neither of these change the external behavior.
Reviewers: hfinkel, kbarton, echristo, iteratee
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D25977
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285351
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Peter Collingbourne [Thu, 27 Oct 2016 21:39:28 +0000 (21:39 +0000)]
BitcodeReader: Require clients to read the block info block at most once.
This change makes it the client's responsibility to call ReadBlockInfoBlock()
at most once. This is in preparation for a future change that will allow
there to be multiple block info blocks.
See also: http://lists.llvm.org/pipermail/llvm-dev/2016-October/106512.html
Differential Revision: https://reviews.llvm.org/D26016
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285350
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Kyle Butt [Thu, 27 Oct 2016 21:37:20 +0000 (21:37 +0000)]
CodeGen: Handle missed case of block removal during BlockPlacement.
There is a use after free bug in the existing code. Loop layout selects
a preferred exit block, and then lays out the loop. If this block is
removed during layout, it needs to be invalidated to prevent a use after
free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285348
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Sanjay Patel [Thu, 27 Oct 2016 21:19:40 +0000 (21:19 +0000)]
[InstCombine] fix foldSPFofSPF() to handle vector splats
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285345
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Kostya Serebryany [Thu, 27 Oct 2016 21:03:48 +0000 (21:03 +0000)]
[libFuzzer] docs: update the examples
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285344
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Kevin Enderby [Thu, 27 Oct 2016 20:59:10 +0000 (20:59 +0000)]
Another additional error check for invalid Mach-O files for the
obsolete load commands.
Again the philosophy of the error checking in libObject for
Mach-O files, the idea behind the checking is that we never
will return a Mach-O file out of libObject that contains unknown
things the library code can’t operate on. So known obsolete
load commands will cause a hard error.
Also to make things clear I have added comments to the
values and structures in Support/Mach-O.h and
Support/MachO.def as to what is obsolete.
As noted in a TODO in the code, there may need to be a
non-default mode to allow some unknown values for well
structured Mach-O files with things like unknown load
load commands. So things like using an old lldb on a newer
Mach-O file could still provide some limited functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285342
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Sanjay Patel [Thu, 27 Oct 2016 20:51:03 +0000 (20:51 +0000)]
[InstCombine] add vector tests for foldSPFofSPF to show missing folds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285340
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Kostya Serebryany [Thu, 27 Oct 2016 20:45:35 +0000 (20:45 +0000)]
[libFuzzer] docs: separate section for fuzz target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285339
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Tom Stellard [Thu, 27 Oct 2016 20:39:09 +0000 (20:39 +0000)]
AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285338
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Kostya Serebryany [Thu, 27 Oct 2016 20:14:03 +0000 (20:14 +0000)]
[libFuzzer] remove large examples from the libFuzzer docs and link to the libFuzzer tutorial instead; also fix a build error in another file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285337
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Sanjay Patel [Thu, 27 Oct 2016 19:54:15 +0000 (19:54 +0000)]
[InstCombine] auto-generate checks for min/max tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285336
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Ehsan Amiri [Thu, 27 Oct 2016 19:10:09 +0000 (19:10 +0000)]
[PPC] Adding the removed testcase again
This testcase was originally part of r284995, but I put it in a wrong directory.
So I removed it. Before adding it back I did some small enhancements. Also I
changed the assertions a little bit, to take into account the impact of some
changes performed since code review is done.
This is similar to changes done for another testcase in the original commit.
See: https://reviews.llvm.org/D23614#577749
Basically for instead of vxor we now generate xxlxor in some cases, which is
better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285333
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Haicheng Wu [Thu, 27 Oct 2016 18:40:02 +0000 (18:40 +0000)]
[LoopUnroll] Check partial unrolling is enabled before initialization. NFC.
Differential Revision: https://reviews.llvm.org/D23891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285330
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Simon Pilgrim [Thu, 27 Oct 2016 18:32:06 +0000 (18:32 +0000)]
[X86][AVX512] Fix MUL v8i64 costs on non-AVX512DQ targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285329
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Sanjay Patel [Thu, 27 Oct 2016 17:30:50 +0000 (17:30 +0000)]
[InstCombine] handle simple vector integer constants in IsFreeToInvert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285318
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Simon Pilgrim [Thu, 27 Oct 2016 17:07:40 +0000 (17:07 +0000)]
[X86][AVX512DQ] Move v2i64 and v4i64 MUL lowering to tablegen
As suggested by @igorb on D26011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285313
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