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Pete Couperus [Wed, 15 May 2019 19:46:17 +0000 (19:46 +0000)]
Uncomment LLVM_FALLTHROUGH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360798
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Cameron McInally [Wed, 15 May 2019 19:37:03 +0000 (19:37 +0000)]
Add unary fneg to InstSimplify/fp-nan.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360797
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Taewook Oh [Wed, 15 May 2019 19:35:38 +0000 (19:35 +0000)]
[PredicateInfo] Do not process unreachable operands.
Summary: We should excluded unreachable operands from processing as their DFS visitation order is undefined. When `renameUses` function sorts `OpsToRename` (https://fburl.com/d2wubn60), the comparator assumes that the parent block of the operand has a corresponding dominator tree node. This is not the case for unreachable operands and crashes the compiler.
Reviewers: dberlin, mgrang, davide
Subscribers: efriedma, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360796
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Nicolai Haehnle [Wed, 15 May 2019 17:48:10 +0000 (17:48 +0000)]
[MachineOperand] Add a ChangeToGA method
Summary:
Analogous to the other ChangeToXXX methods. See the next patch for a
use case.
Change-Id: I6548d614706834fb9109ab3c8fe915e9c6ece2a7
Reviewers: arsenm, kzhuravl
Subscribers: wdng, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61651
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360789
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Nicolai Haehnle [Wed, 15 May 2019 17:29:58 +0000 (17:29 +0000)]
RegAlloc: try to fail more gracefully when out of registers
Summary:
The emitError path allows the program to continue, unlike report_fatal_error.
This is friendlier to use cases where LLVM is embedded in a larger program,
because the caller may be able to deal with the error somewhat gracefully.
Change the number of requested NOP bytes in the AArch64 and PowerPC
test cases to avoid triggering an unrelated assertion. The compilation
still fails, as verified by the test.
Change-Id: Iafb9ca341002a597b82e59ddc7a1f13c78758e3d
Reviewers: arsenm, MatzeB
Subscribers: qcolombet, nemanjai, wdng, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360786
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Thomas Preud'homme [Wed, 15 May 2019 15:20:45 +0000 (15:20 +0000)]
[FileCheck] Fix sphinx error: Make input be gas block
Summary:
Change example of input text from being llvm block to being gas block
since that text is made-up assembly.
Reviewers: jhenderson, jdenny, probinson, arichardson
Subscribers: llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61893
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360781
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Hiroshi Yamauchi [Wed, 15 May 2019 15:15:16 +0000 (15:15 +0000)]
[JumpThreading] A bug fix for stale loop info after unfold select
Summary:
The return value of a TryToUnfoldSelect call was not checked, which led to an
incorrectly preserved loop info and some crash.
The original crash was reported on https://reviews.llvm.org/D59514.
Reviewers: davidxl, amehsan
Reviewed By: davidxl
Subscribers: fhahn, brzycki, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360780
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Ryan Taylor [Wed, 15 May 2019 14:43:55 +0000 (14:43 +0000)]
[AMDGPU] Increases available SGPR for Calling Convention
Summary:
SGPR in CC can be either hw initialized or set by other chained shaders
and so this increases the SGPR count availalbe to CC to 105.
Change-Id: I3dfadc750fe4a3e2bd07117a2899fd13f3e2fef3
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61261
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360778
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Cameron McInally [Wed, 15 May 2019 14:31:33 +0000 (14:31 +0000)]
Teach InstSimplify -X + X --> 0.0 about unary FNeg
Differential Revision: https://reviews.llvm.org/D61916
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360777
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Clement Courbet [Wed, 15 May 2019 14:21:59 +0000 (14:21 +0000)]
Revert r360771 "[MergeICmps] Simplify the code."
Breaks a bunch of builbdots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360776
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Clement Courbet [Wed, 15 May 2019 14:00:45 +0000 (14:00 +0000)]
[MergeICmps] Fix r360771.
Twine references a StringRef by reference, not value...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360775
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Stephen Tozer [Wed, 15 May 2019 13:41:44 +0000 (13:41 +0000)]
Revert "[Salvage] Change salvage debug info implementation to use DW_OP_LLVM_convert where needed"
This reverts r360772 due to build issues.
Reverted commit:
17dd4d7403770bd683675e45f5517e0cdb8f9b2b.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360773
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Stephen Tozer [Wed, 15 May 2019 13:15:48 +0000 (13:15 +0000)]
[Salvage] Change salvage debug info implementation to use DW_OP_LLVM_convert where needed
Fixes issue: https://bugs.llvm.org/show_bug.cgi?id=40645
Previously, LLVM had no functional way of performing casts inside of a
DIExpression(), which made salvaging cast instructions other than Noop
casts impossible. With the recent addition of DW_OP_LLVM_convert this
salvaging is now possible, and so can be used to fix the attached bug as
well as any cases where SExt instruction results are lost in the
debugging metadata. This patch introduces this fix by expanding the
salvage debug info method to cover these cases using the new operator.
Differential revision: https://reviews.llvm.org/D61184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360772
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Clement Courbet [Wed, 15 May 2019 13:04:24 +0000 (13:04 +0000)]
[MergeICmps] Simplify the code.
Instead of patching the original blocks, we now generate new blocks and
delete the old blocks. This results in simpler code with a less twisted
control flow (see the change in `entry-block-shuffled.ll`).
This will make https://reviews.llvm.org/D60318 simpler by making it more
obvious where control flow created and deleted.
Reviewers: gchatelet
Subscribers: hiraditya, llvm-commits, spatel
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360771
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Simon Pilgrim [Wed, 15 May 2019 13:03:10 +0000 (13:03 +0000)]
Revert rL360675 : [APFloat] APFloat::Storage::Storage - fix use after move
This was mentioned both in https://www.viva64.com/en/b/0629/ and by scan-build checks
........
There's concerns this may just introduce a use-after-free instead.....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360770
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David Green [Wed, 15 May 2019 12:58:02 +0000 (12:58 +0000)]
[ARM] Don't use the Machine Scheduler for cortex-m at minsize
The new cortex-m schedule in rL360768 helps performance, but can increase the
amount of high-registers used. This, on average, ends up increasing the
codesize by a fair amount (because less instructions are converted from T2 to
T1). On cortex-m at -Oz, where we are quite size-paranoid, it is better to use
the existing DAG scheduler with the RegPressure scheduling preference (at least
until the issues around T2 vs T1 instructions can be improved).
I have also made sure that the Sched::RegPressure dag scheduler is always
chosen for MinSize.
The test shows one case where we increase the number of registers used.
Differential Revision: https://reviews.llvm.org/D61882
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360769
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David Green [Wed, 15 May 2019 12:41:58 +0000 (12:41 +0000)]
[ARM] Cortex-M4 schedule
This patch adds a simple Cortex-M4 schedule, renaming the existing M3
schedule to M4 and filling in the latencies as-per the Cortex-M4 TRM:
https://developer.arm.com/docs/ddi0439/latest
Most of these are 1, with the important exception being loads taking 2
cycles. A few others are also higher, but I don't believe they make a
large difference. I've repurposed the M3 schedule as the latencies are
mostly the same between the two cores, with the M4 having more FP and
DSP instructions. We also turn on MISched and UseAA for the cores that
now use this.
It also adds some schedule Write's to various instruction to make things
simpler.
Differential Revision: https://reviews.llvm.org/D54142
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360768
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Nico Weber [Wed, 15 May 2019 12:08:45 +0000 (12:08 +0000)]
gn build: Merge r360671
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360766
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Simon Atanasyan [Wed, 15 May 2019 12:05:27 +0000 (12:05 +0000)]
[mips] LLVM and GAS now use same instructions for CFA Definition. NFCI
LLVM previously used `DW_CFA_def_cfa` instruction in .eh_frame to set
the register and offset for current CFA rule. We change it to
`DW_CFA_def_cfa_register` which is the same one used by GAS that only
changes the register but keeping the old offset.
Patch by Mirko Brkusanin.
Differential Revision: https://reviews.llvm.org/D61899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360765
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Nico Weber [Wed, 15 May 2019 12:03:10 +0000 (12:03 +0000)]
gn build: Run `git ls-files '*.gn' '*.gni' | xargs llvm/utils/gn/gn.py format`
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360764
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Tim Northover [Wed, 15 May 2019 12:01:04 +0000 (12:01 +0000)]
arm64_32: add some unittests that were in the wrong commit.
Accidentally dropped them when committing the arm64_32 binutils support.
There's no change to real code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360763
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Roman Lebedev [Wed, 15 May 2019 10:24:38 +0000 (10:24 +0000)]
[NFC][InstCombine] Regenerate trunc.ll test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360759
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Florian Hahn [Wed, 15 May 2019 10:05:49 +0000 (10:05 +0000)]
[LV] Move getScalarizationOverhead and vector call cost computations to CM. (NFC)
This reduces the number of parameters we need to pass in and they seem a
natural fit in LoopVectorizationCostModel. Also simplifies things for
D59995.
As a follow up refactoring, we could only expose a expose a
shouldUseVectorIntrinsic() helper in LoopVectorizationCostModel, instead
of calling getVectorCallCost/getVectorIntrinsicCost in
InnerLoopVectorizer/VPRecipeBuilder.
Reviewers: Ayal, hsaito, dcaballe, rengolin
Reviewed By: rengolin
Differential Revision: https://reviews.llvm.org/D61638
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360758
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Clement Courbet [Wed, 15 May 2019 08:21:18 +0000 (08:21 +0000)]
[[DAGCombiner][NFC] Add a comment.
As suggested in D61846.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360755
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Craig Topper [Wed, 15 May 2019 04:15:46 +0000 (04:15 +0000)]
[X86] Use OR32mi8Locked instead of LOCK_OR32mi8 in emitLockedStackOp.
They encode the same way, but OR32mi8Locked sets hasUnmodeledSideEffects set
which should be stronger than the mayLoad/mayStore on LOCK_OR32mi8. I think
this makes sense since we are using it as a fence.
This also seems to hide the operation from the speculative load hardening pass
so I've reverted r360511.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360747
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Fangrui Song [Wed, 15 May 2019 03:08:21 +0000 (03:08 +0000)]
Fix 2-field llvm.global_ctors `REQUIRES: asserts` tests after rL360742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360743
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Fangrui Song [Wed, 15 May 2019 02:35:32 +0000 (02:35 +0000)]
[IR] Disallow llvm.global_ctors and llvm.global_dtors of the 2-field form in textual format
The 3-field form was introduced by D3499 in 2014 and the legacy 2-field
form was planned to be removed in LLVM 4.0
For the textual format, this patch migrates the existing 2-field form to
use the 3-field form and deletes the compatibility code.
test/Verifier/global-ctors-2.ll checks we have a friendly error message.
For bitcode, lib/IR/AutoUpgrade UpgradeGlobalVariables will upgrade the
2-field form (add i8* null as the third field).
Reviewed By: rnk, dexonsmith
Differential Revision: https://reviews.llvm.org/D61547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360742
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Philip Reames [Wed, 15 May 2019 01:39:07 +0000 (01:39 +0000)]
[NFC] Reuse a helper function to eliminate duplicate code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360740
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Richard Trieu [Wed, 15 May 2019 01:28:30 +0000 (01:28 +0000)]
[XCore] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360738
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Richard Trieu [Wed, 15 May 2019 01:17:58 +0000 (01:17 +0000)]
[X86] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360736
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Richard Trieu [Wed, 15 May 2019 01:03:00 +0000 (01:03 +0000)]
[WebAssembly] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360735
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Richard Trieu [Wed, 15 May 2019 00:46:18 +0000 (00:46 +0000)]
[SystemZ] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360734
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Richard Trieu [Wed, 15 May 2019 00:35:37 +0000 (00:35 +0000)]
[Sparc] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360733
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Richard Trieu [Wed, 15 May 2019 00:24:15 +0000 (00:24 +0000)]
[RISCV] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360732
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Richard Trieu [Wed, 15 May 2019 00:09:58 +0000 (00:09 +0000)]
[PowerPC] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360731
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Richard Trieu [Tue, 14 May 2019 23:56:18 +0000 (23:56 +0000)]
[NVPTX] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360729
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Richard Trieu [Tue, 14 May 2019 23:45:18 +0000 (23:45 +0000)]
[MSP430] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360728
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Richard Trieu [Tue, 14 May 2019 23:34:37 +0000 (23:34 +0000)]
[Mips] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360727
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Richard Trieu [Tue, 14 May 2019 23:17:18 +0000 (23:17 +0000)]
[Lanai] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360726
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Richard Trieu [Tue, 14 May 2019 23:04:55 +0000 (23:04 +0000)]
[Hexagon] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360724
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Richard Trieu [Tue, 14 May 2019 22:54:06 +0000 (22:54 +0000)]
[BPF] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360722
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Richard Trieu [Tue, 14 May 2019 22:41:58 +0000 (22:41 +0000)]
[AVR] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360721
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Philip Reames [Tue, 14 May 2019 22:32:42 +0000 (22:32 +0000)]
Use an offset from TOS for idempotent rmw locked op lowering
This was the portion split off D58632 so that it could follow the redzone API cleanup. Note that I changed the offset preferred from -8 to -64. The difference should be very minor, but I thought it might help address one concern which had been previously raised.
Differential Revision: https://reviews.llvm.org/D61862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360719
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Richard Trieu [Tue, 14 May 2019 22:29:50 +0000 (22:29 +0000)]
[ARM] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360718
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Richard Trieu [Tue, 14 May 2019 22:06:04 +0000 (22:06 +0000)]
[ARC] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360716
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Richard Trieu [Tue, 14 May 2019 21:54:37 +0000 (21:54 +0000)]
[AMDGPU] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360713
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Richard Trieu [Tue, 14 May 2019 21:33:53 +0000 (21:33 +0000)]
[AArch64] Create a TargetInfo header. NFC
Move the declarations of getThe<Name>Target() functions into a new header in
TargetInfo and make users of these functions include this new header.
This fixes a layering problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360709
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Leonard Chan [Tue, 14 May 2019 21:17:21 +0000 (21:17 +0000)]
[NewPM] Port HWASan and Kernel HWASan
Port hardware assisted address sanitizer to new PM following the same guidelines as msan and tsan.
Changes:
- Separate HWAddressSanitizer into a pass class and a sanitizer class.
- Create new PM wrapper pass for the sanitizer class.
- Use the getOrINsert pattern for some module level initialization declarations.
- Also enable kernel-kwasan in new PM
- Update llvm tests and add clang test.
Differential Revision: https://reviews.llvm.org/D61709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360707
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Roman Lebedev [Tue, 14 May 2019 20:17:04 +0000 (20:17 +0000)]
[NFC][CodeGen][X86][AArch64] Add and-const-mask + const-shift pattern tests
Unlike instcombine, we currently don't turn and+shift into shift+and.
We probably should, likely unconditionally.
While i'm adding only all-ones (potentially shifted) mask,
this obviously isn't limited to any particular mask pattern:
https://rise4fun.com/Alive/kmX
Related to https://bugs.llvm.org/show_bug.cgi?id=41874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360706
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Florian Hahn [Tue, 14 May 2019 19:41:36 +0000 (19:41 +0000)]
[LICM] Allow AliasSetMap to contain top-level loops.
When an outer loop gets deleted by a different pass, before LICM visits
it, we cannot clean up its sub-loops in AliasSetMap, because at the
point we receive the deleteAnalysisLoop callback for the outer loop, the loop
object is already invalid and we cannot access its sub-loops any longer.
Reviewers: asbirlea, sanjoy, chandlerc
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D61904
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360704
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Dmitry Preobrazhensky [Tue, 14 May 2019 19:16:24 +0000 (19:16 +0000)]
[AMDGPU][GFX8][GFX9] Corrected predicate of v_*_co_u32 aliases
Reviewers: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D61905
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360702
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Nikita Popov [Tue, 14 May 2019 18:53:47 +0000 (18:53 +0000)]
[LVI][CVP] Add support for abs/nabs select pattern flavor
Based on ConstantRange support added in D61084, we can now handle
abs and nabs select pattern flavors in LVI.
Differential Revision: https://reviews.llvm.org/D61794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360700
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Alina Sbirlea [Tue, 14 May 2019 18:07:18 +0000 (18:07 +0000)]
[MemorySSA] LoopSimplify preserves MemorySSA only when flag is flipped.
LoopSimplify can preserve MemorySSA after r360270.
But the MemorySSA analysis is retrieved and preserved only when the
EnableMSSALoopDependency is set to true. Use the same conditional to
mark the pass as preserved, otherwise subsequent passes will get an
invalid analysis.
Resolves PR41853.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360697
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Philip Reames [Tue, 14 May 2019 17:50:06 +0000 (17:50 +0000)]
Fix a release mode warning introduced in r360694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360696
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Philip Reames [Tue, 14 May 2019 17:20:10 +0000 (17:20 +0000)]
[IndVars] Extend reasoning about loop invariant exits to non-header blocks
Noticed while glancing through the code for other reasons. The extension is trivial enough, decided to just do it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360694
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Cameron McInally [Tue, 14 May 2019 16:51:18 +0000 (16:51 +0000)]
Support FNeg in SpeculativeExecution pass
Differential Revision: https://reviews.llvm.org/D61910
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360692
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Philip Reames [Tue, 14 May 2019 16:37:29 +0000 (16:37 +0000)]
[Test] Autogen a test for ease of later changing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360690
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Stanislav Mekhanoshin [Tue, 14 May 2019 16:18:00 +0000 (16:18 +0000)]
[AMDGPU] Fixed handling of imemdiate i1 literals
This bug was exposed by the rL360395.
Differential Revision: https://reviews.llvm.org/D61812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360689
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Tim Renouf [Tue, 14 May 2019 16:17:14 +0000 (16:17 +0000)]
[AMDGPU] Fixed +DumpCode
The +DumpCode attribute is a horrible hack in AMDGPU to embed the
disassembly of the generated code into the elf file. It is used by LLPC
to implement an extension that allows the application to read back the
disassembly of the code. Longer term, we should re-implement that by
using the LLVM disassembler from the Vulkan driver.
Recent LLVM changes broke +DumpCode. With -filetype=asm it crashed, and
with -filetype=obj I think it did not include any instructions, only the
labels. Fixed with this commit: now it has no effect with -filetype=asm,
and works as intended with -filetype=obj.
Differential Revision: https://reviews.llvm.org/D60682
Change-Id: I6436d86fe2ea220d74a643a85e64753747c9366b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360688
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Javed Absar [Tue, 14 May 2019 16:14:24 +0000 (16:14 +0000)]
[ARM][CMSE] Add cmse intrinsics for TT instructions
Defines intrinsics cmse_TT, cmse_TTT, cmse_TTA, cmse_TTAT.
No tests here as the tests are in patches that uses these.
Reviewed By: Todd Snider, Dave Green
Differential Revision: https://reviews.llvm.org/D59888
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360687
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Stanislav Mekhanoshin [Tue, 14 May 2019 16:04:03 +0000 (16:04 +0000)]
[AMDGPU] gfx1010 Strengthen some SMEM WAR hazard unit tests. NFC.
Tighten conditions on SMEM WAR hazard unit tests to ensure rejection
of workaround insertion where a s_waitcnt is present in dependency
chain. The current workaround code already conforms to these revise
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360686
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Simon Pilgrim [Tue, 14 May 2019 15:21:28 +0000 (15:21 +0000)]
[X86] Disable shouldFoldConstantShiftPairToMask for scalar shifts on AMD targets (PR40758)
D61068 handled vector shifts, this patch does the same for scalars where there are similar number of pipes for shifts as bit ops - this is true almost entirely for AMD targets where the scalar ALUs are well balanced.
This combine avoids AND immediate mask which usually means we reduce encoding size.
Some tests show use of (slow, scaled) LEA instead of SHL in some cases, but thats due to particular shift immediates - shift+mask generate these just as easily.
Differential Revision: https://reviews.llvm.org/D61830
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360684
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Cullen Rhodes [Tue, 14 May 2019 15:10:16 +0000 (15:10 +0000)]
[AArch64][SVE2] Asm: add SQRDMLAH/SQRDMLSH instructions
Summary:
This patch adds support for the indexed and unpredicated vectors forms of the
SQRDMLAH and SQRDMLSH instructions.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D61515
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360683
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Cullen Rhodes [Tue, 14 May 2019 15:01:00 +0000 (15:01 +0000)]
[AArch64][SVE2] Asm: add integer multiply-add/subtract (indexed) instructions
Summary:
This patch adds support for the following instructions:
MLA mul-add, writing addend (Zda = Zda + Zn * Zm[idx])
MLS mul-sub, writing addend (Zda = Zda + -Zn * Zm[idx])
Predicated forms of these instructions were added in SVE.
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: rovka
Differential Revision: https://reviews.llvm.org/D61514
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360682
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Paul Robinson [Tue, 14 May 2019 14:51:54 +0000 (14:51 +0000)]
Replace lit feature keyword 'not_COFF' with 'uses_COFF'.
Differential Revision: https://reviews.llvm.org/D61791
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360680
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Fangrui Song [Tue, 14 May 2019 14:37:26 +0000 (14:37 +0000)]
DWARF v5: emit DW_AT_addr_base if DW_AT_low_pc references .debug_addr
The condition !AddrPool.empty() is tested before attachRangesOrLowHighPC(), which may add an entry to AddrPool. We emit DW_AT_low_pc (DW_FORM_addrx) but may incorrectly omit DW_AT_addr_base for LineTablesOnly. This can be easily reproduced:
clang -gdwarf-5 -gmlt -c a.cc
Fix this by moving !AddrPool.empty() below.
This was discovered while investigating an lld crash (fixed by D61889) on such object files: ld.lld --gdb-index a.o
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D61891
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360678
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Lei Huang [Tue, 14 May 2019 14:27:06 +0000 (14:27 +0000)]
[PowerPC] Custom lower known CR bit spills
For known CRBit spills, CRSET/CRUNSET, it is more efficient to load and spill
the known value instead of extracting the bit.
eg. This sequence is currently used to spill a CRUNSET:
crclr 4*cr5+lt
mfocrf r3,4
rlwinm r3,r3,20,0,0
stw r3,132(r1)
This patch custom lower it to:
li r3,0
stw r3,132(r1)
Differential Revision: https://reviews.llvm.org/D61754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360677
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George Rimar [Tue, 14 May 2019 14:22:44 +0000 (14:22 +0000)]
[llvm-readobj] - Apply clang format. NFC.
I am a bit tired of the formatting issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360676
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Simon Pilgrim [Tue, 14 May 2019 14:13:30 +0000 (14:13 +0000)]
[APFloat] APFloat::Storage::Storage - fix use after move
This was mentioned both in https://www.viva64.com/en/b/0629/ and by scan-build checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360675
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Xing Xue [Tue, 14 May 2019 13:54:33 +0000 (13:54 +0000)]
[lit][tests]Add feature libcxx-used and use it in llvm-*-fuzzer tests
When a LLVM binary such as llvm-*-fuzzer is built with libc++, it has dependency on libc++. The path to find shared libraries specified in llvm-*-fuzzer is relative. As a result, these binaries cannot be copied to an arbitrary directory and launched from there. Changes in this patch add a LIT feature to indicate that libc++ is used to build and, based on the feature exclude test cases that test by copying llvm-*-fuzzer binaries to a directory.
Reviewers: hubert.reinterpretcast, dberris, amyk, jasonliu, EricWF
Reviewed By: hubert.reinterpretcast, amyk
Subscribers: javed.absar, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360672
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Kit Barton [Tue, 14 May 2019 13:26:36 +0000 (13:26 +0000)]
Save the induction binary operator in IVDescriptors for non FP induction variables.
Summary:
Currently InductionBinOps are only saved for FP induction variables, the PR extends it with non FP induction variable, so user of IVDescriptors can query the InductionBinOps for integer induction variables.
The changes in hasUnsafeAlgebra() and getUnsafeAlgebraInst() are required for the existing LIT test cases to pass. As described in the comment of the two functions, one of the requirement to return true is it is a FP induction variable. The checks was not needed because InductionBinOp was not set on non FP cases before.
https://reviews.llvm.org/D60565 depends on the patch.
Committed on behalf of @Whitney (Whitney Tsang).
Reviewers: jdoerfert, kbarton, fhahn, hfinkel, dmgreen, Meinersbur
Reviewed By: jdoerfert
Subscribers: mgorny, hiraditya, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360671
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Tim Northover [Tue, 14 May 2019 13:04:25 +0000 (13:04 +0000)]
TableGen: support #ifndef in addition to #ifdef.
TableGen has a limited preprocessor, which only really supports
easier.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360670
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Thomas Preud'homme [Tue, 14 May 2019 11:58:30 +0000 (11:58 +0000)]
Reinstate "FileCheck [5/12]: Introduce regular numeric variables"
This reinstates r360578 (git
e47362c1ec1ea31b626336cc05822035601c3e57),
reverted in r360653 (git
004393681c25e34e921adccc69ae6378090dee54),
with a fix for the list added in FileCheck.rst to build without error.
Copyright:
- Linaro (changes up to diff 183612 of revision D55940)
- GraphCore (changes in later versions of revision D55940 and
in new revision created off D55940)
Reviewers: jhenderson, chandlerc, jdenny, probinson, grimar,
arichardson, rnk
Subscribers: hiraditya, llvm-commits, probinson, dblaikie, grimar,
arichardson, tra, rnk, kristina, hfinkel, rogfer01, JonChesterfield
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D60385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360665
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Simon Pilgrim [Tue, 14 May 2019 11:30:39 +0000 (11:30 +0000)]
[X86] X86TargetLowering::LowerINTRINSIC_WO_CHAIN - ensure rounding control is initialized. NFCI.
Fixes scan-build warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360664
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Tim Northover [Tue, 14 May 2019 11:25:44 +0000 (11:25 +0000)]
AArch64: support binutils-like things on arm64_32.
This adds support for the arm64_32 watchOS ABI to LLVM's low level tools,
teaching them about the specific MachO choices and constants needed to
disassemble things.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360663
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Tim Northover [Tue, 14 May 2019 11:03:13 +0000 (11:03 +0000)]
GlobalOpt: do not promote globals used atomically to constants.
Some atomic loads are implemented as cmpxchg (particularly if large or
floating), and that usually requires write access to the memory involved
or it will segfault.
We can still propagate the constant value to users we understand though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360662
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James Henderson [Tue, 14 May 2019 10:59:04 +0000 (10:59 +0000)]
[llvm-objcopy] Cache gnu_debuglink's target CRC
.gnu_debuglink section contains information regarding file with
debugging symbols, identified by its CRC32. This target file is not
intended to ever change or it would invalidate the stored checksum, yet
the checksum is calculated over and over again for each of the objects
inside the archive, usually hundreds of times.
This patch precomputes the CRC32 of the target once and then reuses the
value where required, saving lots of redundant I/O.
The error message reported should stay the same, although now it might
be reported earlier.
Reviewed by: jhenderson, jakehehrlich, MaskRay
Differential Revision: https://reviews.llvm.org/D61343
Patch by Michal Janiszewski
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360661
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James Henderson [Tue, 14 May 2019 10:53:35 +0000 (10:53 +0000)]
[test]Make test work on Windows
Previously, the test didn't work because '\' characters appeared in the
sed string, causing bogus escape characters to form in the substituted
string literal. Switching to using '%/p' causes the path to be emitted
with '/' characters instead, so that there are are no escaping issues.
Reviewed by: kzhuravl, grimar
Differential Revision: https://reviews.llvm.org/D61856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360660
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Simon Pilgrim [Tue, 14 May 2019 10:29:18 +0000 (10:29 +0000)]
[MemorySanitizer] getMMXVectorTy - assert valid element size. NFCI.
Fixes scan-build warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360658
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Diana Picus [Tue, 14 May 2019 09:25:17 +0000 (09:25 +0000)]
[IRTranslator] Don't hardcode GEP index type
When breaking up loads and stores of aggregates, the IRTranslator uses
LLT::scalar(64) for the index type of the G_GEP instructions that
compute the addresses. This is unnecessarily large for 32-bit targets.
Use the int ptr type provided by the DataLayout instead.
Note that we're already doing the right thing when translating
getelementptr instructions from the IR. This is just an oversight when
generating new ones while translating loads/stores.
Both x86 and AArch64 already have tests confirming that the old
behaviour is preserved for 64-bit targets.
Differential Revision: https://reviews.llvm.org/D61852
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360656
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Thomas Preud'homme [Tue, 14 May 2019 08:43:11 +0000 (08:43 +0000)]
Revert "FileCheck [5/12]: Introduce regular numeric variables"
This reverts r360578 (git
e47362c1ec1ea31b626336cc05822035601c3e57) to
solve the sphinx build failure on
http://lab.llvm.org:8011/builders/llvm-sphinx-docs buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360653
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Alex Denisov [Tue, 14 May 2019 07:20:58 +0000 (07:20 +0000)]
Add guidelines/recommendations for organizers of LLVM Socials
Differential Revision: https://reviews.llvm.org/D61550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360651
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Philip Reames [Tue, 14 May 2019 04:43:37 +0000 (04:43 +0000)]
[X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets
This is a follow on to D58632, with the same logic. Given a memory operation which needs ordering, but doesn't need to modify any particular address, prefer to use a locked stack op over an mfence.
Differential Revision: https://reviews.llvm.org/D61863
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360649
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Fangrui Song [Tue, 14 May 2019 04:22:51 +0000 (04:22 +0000)]
[Object] Change ObjectFile::getSectionContents to return Expected<ArrayRef<uint8_t>>
Change
std::error_code getSectionContents(DataRefImpl, StringRef &) const;
to
Expected<ArrayRef<uint8_t>> getSectionContents(DataRefImpl) const;
Many object formats use ArrayRef<uint8_t> as the underlying type, which
is generally better than StringRef to represent binary data, so change
the type to decrease the number of type conversions.
Reviewed By: ruiu, sbc100
Differential Revision: https://reviews.llvm.org/D61781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360648
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David L. Jones [Tue, 14 May 2019 04:13:59 +0000 (04:13 +0000)]
gn build: add Hexagon target
Differential Revision: https://reviews.llvm.org/D61819
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360647
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David L. Jones [Tue, 14 May 2019 04:02:50 +0000 (04:02 +0000)]
gn build: add Sparc target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360645
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David L. Jones [Tue, 14 May 2019 03:52:33 +0000 (03:52 +0000)]
gn build: add Lanai target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360644
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Jinsong Ji [Tue, 14 May 2019 03:11:24 +0000 (03:11 +0000)]
[PowerPC][NFC] Fix typos in triples
Found by bzEq (Kai Luo).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360643
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Craig Topper [Tue, 14 May 2019 03:07:56 +0000 (03:07 +0000)]
[X86] Use X86 instead of X32 as a check prefix in atomic-idempotent.ll. NFC
X32 can refer to a 64-bit ABI that uses 32-bit ints, longs, and pointers.
I plan to add gnux32 command lines to this test so this prepares for that.
Also remove some check lines that have a prefix that is not in any run lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360642
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Sanjay Patel [Tue, 14 May 2019 00:57:31 +0000 (00:57 +0000)]
[SDAG] fix unused variable warning and unneeded indirection; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360640
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Sanjay Patel [Tue, 14 May 2019 00:39:40 +0000 (00:39 +0000)]
[SDAG, x86] allow targets to override test for binop opcodes
This follows the pattern of the existing isCommutativeBinOp().
x86 shows improvements from vector narrowing for the min/max opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360639
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Gor Nishanov [Mon, 13 May 2019 23:58:24 +0000 (23:58 +0000)]
[coroutines] Fix spills of static array allocas
Summary:
CoroFrame was not considering static array allocas, and was only ever reserving a single element in the coroutine frame.
This meant that stores to the non-zero'th element would corrupt later frame data.
Store static array allocas as field arrays in the coroutine frame.
Added test.
Committed by Gor Nishanov on behalf of ben-clayton
Reviewers: GorNishanov, modocache
Reviewed By: GorNishanov
Subscribers: Orlando, capn, EricWF, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D61372
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360636
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Vitaly Buka [Mon, 13 May 2019 22:30:53 +0000 (22:30 +0000)]
[gn] Fix build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360629
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Craig Topper [Mon, 13 May 2019 22:17:13 +0000 (22:17 +0000)]
[X86] Use ISD::MERGE_VALUES to return from lowerAtomicArith instead of calling ReplaceAllUsesOfValueWith and returning SDValue().
Returning SDValue() makes the caller think that nothing happened and it will
end up executing the Expand path. This generates extra nodes that will need to
be pruned as dead code.
Returning an ISD::MERGE_VALUES will tell the caller that we'd like to make a
change and it will take care of replacing uses. This will prevent falling into
the Expand path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360627
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Stanislav Mekhanoshin [Mon, 13 May 2019 21:59:03 +0000 (21:59 +0000)]
[AMDGPU] gfx1010 SearchableTableEmitter patch for NSA
This part was accidentally missing from NSA image support commit.
Differential Revision: https://reviews.llvm.org/D61868
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360623
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Nemanja Ivanovic [Mon, 13 May 2019 21:14:36 +0000 (21:14 +0000)]
[Pass Pipeline][NFC] Add a test prior to committing D61726
This patch just adds a test case to show the differences in code emitted
by opt before and after https://reviews.llvm.org/D61726.
Previous attempt to commit this did not include the registered target
requirement so it caused buildbot breaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360620
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Craig Topper [Mon, 13 May 2019 21:01:24 +0000 (21:01 +0000)]
[X86] Various type corrections to the code that creates LOCK_OR32mi8/OR32mi8Locked to the stack for idempotent atomic rmw and atomic fence.
These are updates to match how isel table would emit a LOCK_OR32mi8 node.
-Use i32 for the immediate zero even though only 8 bits are encoded.
-Use i16 for segment register.
-Use LOCK_OR32mi8 for idempotent atomic operations in 32-bit mode to match
64-bit mode. I'm not sure why OR32mi8Locked and LOCK_OR32mi8 both exist. The
only difference seems to be that OR32mi8Locked is marked as UnmodeledSideEffects=1.
-Emit an extra i32 result for the flags output.
I don't know if the types here really matter just noticed it was inconsistent
with normal behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360619
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Lang Hames [Mon, 13 May 2019 20:52:30 +0000 (20:52 +0000)]
[JITLink][MachO] Honor the no-dead-strip flag on nlist entries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360618
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David L. Jones [Mon, 13 May 2019 20:32:53 +0000 (20:32 +0000)]
[Support] Ensure redirected outputs don't contain output from previous tests.
stdout may be buffered, and may not flush on every write. Explicitly flushing
before redirecting the output ensures that the captured output does not contain
output from other tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360617
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Nikita Popov [Mon, 13 May 2019 19:40:18 +0000 (19:40 +0000)]
[WebAssembly] Don't assume that zext/sext result is i32/i64 in fast isel (PR41841)
Usually this will abort fast-isel at the instruction using the
non-legal result, but if the only use is in a different basic block,
we'll incorrectly assume that the zext/sext is to i32 (rather than
i128 in this case).
Differential Revision: https://reviews.llvm.org/D61823
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360616
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