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Craig Topper [Tue, 20 Mar 2018 20:24:16 +0000 (20:24 +0000)]
[TableGen] Use range based for loop. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328034
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Craig Topper [Tue, 20 Mar 2018 20:24:14 +0000 (20:24 +0000)]
[TableGen] Use vector::append instead of looping and calling push_back. NFC
Both vectors contain unsigned so we can just use append to do the copying. Not only is this shorter, but it should be able to predict the final size and only grow the vector once if needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328033
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Craig Topper [Tue, 20 Mar 2018 20:24:12 +0000 (20:24 +0000)]
[TableGen] Use llvm::transform to simplify some loops. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328032
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Craig Topper [Tue, 20 Mar 2018 20:24:10 +0000 (20:24 +0000)]
[TableGen] Pass result of std::unique to vector::erase instead of calculating a size and calling resize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328031
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Alexey Bataev [Tue, 20 Mar 2018 20:21:38 +0000 (20:21 +0000)]
[DEBUGINFO] Add -no-dwarf-debug-ranges option.
Summary:
Added option -no-dwarf-debug-ranges option to disable emission of
.debug_ranges section.
Reviewers: probinson, echristo
Subscribers: aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D44384
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328030
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Andrea Di Biagio [Tue, 20 Mar 2018 20:18:36 +0000 (20:18 +0000)]
[llvm-mca] add keyword override to a couple of methods in BackendStatistics.
This should fix the buildbots after r328011.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328029
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Derek Schuff [Tue, 20 Mar 2018 20:06:35 +0000 (20:06 +0000)]
[WebAssembly] Added initial AsmParser implementation.
It uses the MC framework and the tablegen matcher to do the
heavy lifting. Can handle both explicit and implicit locals
(-disable-wasm-explicit-locals). Comes with a small regression
test.
This is a first basic implementation that can parse most llvm .s
output and round-trips most instructions succesfully, but in order
to keep the commit small, does not address all issues.
There are a fair number of mismatches between what MC / assembly
matcher think a "CPU" should look like and what WASM provides,
some already have workarounds in this commit (e.g. the way it
deals with register operands) and some that require further work.
Some of that further work may involve changing what the
Disassembler outputs (and what s2wasm parses), so are probably
best left to followups.
Some known things missing:
- Many directives are ignored and not emitted.
- Vararg calls are parsed but extra args not emitted.
- Loop signatures are likely incorrect.
- $drop= is not emitted.
- Disassembler does not output SIMD types correctly, so assembler
can't test them.
Patch by Wouter van Oortmerssen
Differential Revision: https://reviews.llvm.org/D44329
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328028
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Evandro Menezes [Tue, 20 Mar 2018 20:00:29 +0000 (20:00 +0000)]
[AArch64] Adjust the cost model for Exynos M3
Fix typo in the number of integer dividers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328027
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Alexander Shaposhnikov [Tue, 20 Mar 2018 19:50:14 +0000 (19:50 +0000)]
[llvm-objcopy] Revert the tests from r328012
Temporarily revert the tests from r328012 as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328026
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Alexander Shaposhnikov [Tue, 20 Mar 2018 19:46:00 +0000 (19:46 +0000)]
[llvm-objcopy] Revert r328012
Temporarily revert r328012 (since it broke down the big-endian bots),
will resubmit an updated version later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328024
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Krzysztof Parzyszek [Tue, 20 Mar 2018 19:35:09 +0000 (19:35 +0000)]
[Hexagon] Add a few more lit tests, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328023
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Krzysztof Parzyszek [Tue, 20 Mar 2018 19:26:27 +0000 (19:26 +0000)]
[Hexagon] Add heuristic to exclude critical path cost for scheduling
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328022
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Krzysztof Parzyszek [Tue, 20 Mar 2018 19:23:18 +0000 (19:23 +0000)]
[Hexagon] Fix fall-through warnings in HexagonMCDuplexInfo.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328021
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Nirav Dave [Tue, 20 Mar 2018 19:12:41 +0000 (19:12 +0000)]
[MC,X86] Cleanup some X86 parser functions to use MCParser helpers. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328019
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Andrea Di Biagio [Tue, 20 Mar 2018 19:06:34 +0000 (19:06 +0000)]
[llvm-mca] Remove const from a bunch of ArrayRef. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328018
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Craig Topper [Tue, 20 Mar 2018 18:49:28 +0000 (18:49 +0000)]
[PowerPC][LegalizeFloatTypes] Move the PPC hacks for (i32 fp_to_sint/fp_to_uint (ppcf128 X)) out of LegalizeFloatTypes and into PPC specific code
I'm not entirely sure these hacks are still needed. If you remove the hacks completely, the name of the library call that gets generated doesn't match the grep the test previously had. So the test wasn't really checking anything.
If the hack is still needed it belongs in PPC specific code. I believe the FP_TO_SINT code here is the only place in the tree where a FP_ROUND_INREG node is created today. And I don't think its even being used correctly because the legalization returned a BUILD_PAIR with the same value twice. That doesn't seem right to me. By moving the code entirely to PPC we can avoid creating the FP_ROUND_INREG at all.
I replaced the grep in the existing test with full checks generated by hacking update_llc_test_check.py to support ppc32 just long enough to generate it.
Differential Revision: https://reviews.llvm.org/D44061
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328017
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Krzysztof Parzyszek [Tue, 20 Mar 2018 18:46:55 +0000 (18:46 +0000)]
[X86] Add phony registers for high halves of regs with low halves
Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters
that cover the low halves of these registers. This change adds artificial
subregisters for the high halves in order to differentiate (in terms of
register units) between the 32- and the low 16-bit registers.
This patch contains parts that aim to preserve the calculated register
pressure. This is in order to preserve the current codegen (minimize the
impact of this patch). The approach of having artificial subregisters
could be used to fix PR23423, but the pressure calculation would need
to be changed.
Differential Revision: https://reviews.llvm.org/D43353
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328016
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Philip Reames [Tue, 20 Mar 2018 18:43:44 +0000 (18:43 +0000)]
[MustExecute] Use the annotation style printer
As suggested in the original review (https://reviews.llvm.org/D44524), use an annotation style printer instead.
Note: The switch from -analyze to -disable-output in tests was driven by the fact that seems to be the idiomatic style used in annoation passes. I tried to keep both working, but the old style pass API for printers really doesn't make this easy. It invokes (runOnFunction, print(Module)) repeatedly. I decided the extra state wasn't worth it given the old pass manager is going away soonish anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328015
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Zachary Turner [Tue, 20 Mar 2018 18:37:03 +0000 (18:37 +0000)]
Revert "Resubmit "Support embedding natvis files in PDBs.""
This is still failing on a different bot this time due to some
issue related to hashing absolute paths. Reverting until I can
figure it out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328014
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Alexander Shaposhnikov [Tue, 20 Mar 2018 18:20:42 +0000 (18:20 +0000)]
[llvm-objcopy] Implement support for section groups
This diff adds support for SHT_GROUP sections to llvm-objcopy.
Some sections are interrelated and comprise a group.
For example, a definition of an inline function might require,
in addition to the section containing its instructions,
a read-only data section containing literals referenced inside the function.
A section of the type SHT_GROUP contains the indices of the group members,
therefore, it needs to be updated whenever the indices change.
Similarly, the fields sh_link, sh_info should be recalculated as well.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D43996
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328012
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Andrea Di Biagio [Tue, 20 Mar 2018 18:20:39 +0000 (18:20 +0000)]
[llvm-mca] Move the logic that computes the scheduler's queue usage to the BackendStatistics view.
This patch introduces two new callbacks in the event listener interface to
handle the "buffered resource reserved" event and the "buffered resource
released" event. Every time a buffered resource is used, an event is generated.
Before this patch, the Scheduler (with the help of the ResourceManager) was
responsible for tracking the scheduler's queue usage. However, that design
forced the Scheduler to 'publish' scheduler's queue pressure information through
the Backend interface.
The goal of this patch is to break the dependency between the BackendStatistics
view, and the Backend. Now the Scheduler knows how to notify "buffer
reserved/released" events. The scheduler's queue usage analysis has been moved
to the BackendStatistics.
Differential Revision: https://reviews.llvm.org/D44686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328011
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Artem Belevich [Tue, 20 Mar 2018 17:18:59 +0000 (17:18 +0000)]
[NVPTX] Make tensor load/store intrinsics overloaded.
This way we can support address-space specific variants without explicitly
encoding the space in the name of the intrinsic. Less intrinsics to deal with ->
less boilerplate.
Added a bit of tablegen magic to match/replace an intrinsics with a pointer
argument in particular address space with the space-specific instruction
variant.
Updated tests to use non-default address spaces.
Differential Revision: https://reviews.llvm.org/D43268
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328006
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Philip Reames [Tue, 20 Mar 2018 17:09:21 +0000 (17:09 +0000)]
Add an analysis printer for must execute reasoning
Many of our loop passes make use of so called "must execute" or "guaranteed to execute" facts to prove the legality of code motion. The basic notion is that we know (by assumption) an instruction didn't fault at it's original location, so if the location we move it to is strictly post dominated by the original, then we can't have introduced a new fault.
At the moment, the testing for this logic is somewhat adhoc and done mostly through LICM. Since I'm working on that code, I want to improve the testing. This patch is the first step in that direction. It doesn't actually test the variant used by the loop passes - I need to move that to the Analysis library first - but instead exercises an alternate implementation used by SCEV. (I plan on merging both implementations.)
Note: I'll be replacing the printing logic within this with an annotation based version in the near future. Anna suggested this in review, and it seems like a strictly better format.
Differential Revision: https://reviews.llvm.org/D44524
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328004
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Rafael Espindola [Tue, 20 Mar 2018 17:07:25 +0000 (17:07 +0000)]
MC: fix layering violation introduced in r325139.
Move AsmToken from MC/MCParser/MCAsmLexer.h into MC/MCAsmMacro.h in
order to avoid MCAsmMacro definition depending on MCParser.
Patch by Roger Pau Monné <royger@freebsd.org>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328003
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Zachary Turner [Tue, 20 Mar 2018 17:06:39 +0000 (17:06 +0000)]
Resubmit "Support embedding natvis files in PDBs."
The issue causing this to fail in certain configurations
should be fixed.
It was due to the fact that DIA apparently expects there to be
a null string at ID 1 in the string table. I'm not sure why this
is important but it seems to make a difference, so set it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328002
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Sanjay Patel [Tue, 20 Mar 2018 17:05:19 +0000 (17:05 +0000)]
[LangRef] fix link formatting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328001
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Krzysztof Parzyszek [Tue, 20 Mar 2018 17:03:27 +0000 (17:03 +0000)]
[Hexagon] Correct the computation of TopReadyCycle and BotReadyCycle of SU
TopReadyCycle and BotReadyCycle were off by one cycle when an SU is either
the first instruction or the last instruction in a packet.
Patch by Ikhlas Ajbar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328000
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Michael Zolotukhin [Tue, 20 Mar 2018 17:02:29 +0000 (17:02 +0000)]
[XRay] Lazily compute MachineLoopInfo instead of requiring it.
Summary:
Currently X-Ray Instrumentation pass has a dependency on MachineLoopInfo
(and thus on MachineDominatorTree as well) and we have to compute them
even if X-Ray is not used. This patch changes it to a lazy computation
to save compile time by avoiding these redundant computations.
Reviewers: dberris, kubamracek
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D44666
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327999
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Sanjay Patel [Tue, 20 Mar 2018 16:38:22 +0000 (16:38 +0000)]
[LangRef] describe the default FP environment
Follow-up for D44216: add a section and examples to describe the FP env.
Also, add pointers from the FP instructions to this new section to reduce
bloat.
Differential Revision: https://reviews.llvm.org/D44318
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327998
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Krzysztof Parzyszek [Tue, 20 Mar 2018 16:22:06 +0000 (16:22 +0000)]
[Hexagon] Check weak dependences when only 1 instruction is available
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327997
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Sanjay Patel [Tue, 20 Mar 2018 16:08:47 +0000 (16:08 +0000)]
[AArch64] add fabs tests for PR36600; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327995
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Alexey Bataev [Tue, 20 Mar 2018 16:04:40 +0000 (16:04 +0000)]
[DEBUGINFO] Add flag -no-dwarf-pub-sections to disable pub sections.
Summary:
Added a flag -no-dwarf-pub-sections, which allows to disable
emission of DWARF public sections.
Reviewers: probinson, echristo
Subscribers: aprantl, JDevlieghere, llvm-commits
Differential Revision: https://reviews.llvm.org/D44385
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327994
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Simon Pilgrim [Tue, 20 Mar 2018 15:44:47 +0000 (15:44 +0000)]
[X86][Haswell][Znver1] Fix typo in fldl instregexs
Missing comma was casing 2 instregex entries to be concatenated together by mistake.
Found while investigating PR35548
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327992
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Sjoerd Meijer [Tue, 20 Mar 2018 15:37:15 +0000 (15:37 +0000)]
[Kaleidoscope] doc fix
This fixes the compile command of the example in Chapter 2.
Differential Revision: https://reviews.llvm.org/D43196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327989
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Krzysztof Parzyszek [Tue, 20 Mar 2018 14:54:01 +0000 (14:54 +0000)]
[Hexagon] Improve scheduling heuristic for large basic blocks
This patch changes the isLatencyBound heuristic to look at the
path length based upon the number of packets needed to schedule
a basic block. For small basic blocks, the heuristic uses a small
threshold for isLatencyBound. For large basic blocks, the
heuristic uses a large threshold.
The goal is to increase the priority of an instruction in a small
basic block that has a large height or depth relative to the code
size. For large functions, the height and depth are ignored
because it increases the live range of a register and causes more
spills. That is, for large functions, it is more important to
schedule instructions when available, and attempt to keep the defs
and uses closer together.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327987
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Geoff Berry [Tue, 20 Mar 2018 13:46:35 +0000 (13:46 +0000)]
[AArch64][Falkor] Correct load/store increment scheduling details
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327982
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Krzysztof Parzyszek [Tue, 20 Mar 2018 13:28:46 +0000 (13:28 +0000)]
[Hexagon] Fix division by zero in machine scheduler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327980
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Alex Bradbury [Tue, 20 Mar 2018 13:26:12 +0000 (13:26 +0000)]
[RISCV] Add codegen for RV32F floating point load/store
As part of this, add support for load/store from the constant pool. This is
used to materialise f32 constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327979
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Andrea Di Biagio [Tue, 20 Mar 2018 12:58:34 +0000 (12:58 +0000)]
[llvm-mca] Use llvm::make_unique in a few places. NFC
Also, clang-format a couple of DEBUG functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327978
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Alex Bradbury [Tue, 20 Mar 2018 12:45:35 +0000 (12:45 +0000)]
[RISCV] Add codegen for RV32F arithmetic and conversion operations
Currently, only a soft floating point ABI is supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327976
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Krzysztof Parzyszek [Tue, 20 Mar 2018 12:28:43 +0000 (12:28 +0000)]
[Hexagon] Improve scheduling based on register pressure
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327975
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Simon Pilgrim [Tue, 20 Mar 2018 12:26:55 +0000 (12:26 +0000)]
[X86][SandyBridge] Merge multiple InstrRW entries that map to the same SchedWriteRes group (NFCI) (PR35955)
I've also merged some VEX/non-VEX instregex strings with a (V?) prefix - there are still a lot more of these to do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327974
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Andrea Di Biagio [Tue, 20 Mar 2018 12:25:54 +0000 (12:25 +0000)]
[llvm-mca] Move the routine that computes processor resource masks to its own file.
Function computeProcResourceMasks is used by the ResourceManager (owned by the
Scheduler) to compute resource masks for processor resources. Before this
refactoring, there was an implicit dependency between the Scheduler and the
InstrBuilder. That is because InstrBuilder has to know about resource masks when
computing the set of processor resources consumed by a new instruction.
With this patch, the functionality that computes resource masks has been
extracted from the ResourceManager, and moved to a separate file (Support.h).
This helps removing the dependency between the Scheduler and the InstrBuilder.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327973
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Xin Tong [Tue, 20 Mar 2018 12:03:25 +0000 (12:03 +0000)]
[MergeICmps] Break eargerly out of loop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327972
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Xin Tong [Tue, 20 Mar 2018 11:57:54 +0000 (11:57 +0000)]
[MergeICmp] Fix a bug in entry block shuffled to middle of the chain
Summary: Fix a bug in entry block shuffled to middle of the chain.
Reviewers: davide, courbet
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327971
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Igor Laevsky [Tue, 20 Mar 2018 11:32:13 +0000 (11:32 +0000)]
[llvm-opt-fuzzer] Add irce to the fuzzing options
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327969
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Jonas Devlieghere [Tue, 20 Mar 2018 11:26:50 +0000 (11:26 +0000)]
Revert "Fix layering between llvm-c and Support by factoring out some typedefs into Support"
This reverts r327940 because it fails on several GreenDragon bots.
http://green.lab.llvm.org/green/job/clang-stage2-configure-Rlto/
http://green.lab.llvm.org/green/job/clang-stage2-coverage-R/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327968
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Dylan McKay [Tue, 20 Mar 2018 11:23:03 +0000 (11:23 +0000)]
[AVR] Add a regression test for struct return lowering
The test is taken from
https://github.com/avr-rust/rust/issues/57
The originally implementation of struct return lowering was made in
r325474.
Patch by Peter Nimmervoll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327967
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Andrea Di Biagio [Tue, 20 Mar 2018 10:25:36 +0000 (10:25 +0000)]
[Release Notes] Add release note for llvm-mca.
Differential Revision: https://reviews.llvm.org/D44636
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327965
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Bjorn Pettersson [Tue, 20 Mar 2018 09:06:37 +0000 (09:06 +0000)]
[CGP] Avoid segmentation fault when doing PHI node simplifications
Summary:
Made PHI node simplifiations more robust in several ways:
- Minor refactoring to let the SimplificationTracker own the
sets with new PHI/Select nodes that are introduced. This is
maybe not mapping to the original intention with the
SimplificationTracker, but IMHO it encapsulates the logic behind
those sets a little bit better.
- MatchPhiNode can sometimes populate the Matched set with
several entries, where it maps one PHI node to different candidates
for replacement. The Matched set is changed into a SmallSetVector
to make sure we get a deterministic iteration when doing
the replacements.
- As described above we may get several different replacements
for a single PHI node. The loop in MatchPhiSet that is doing
the replacements could end up calling eraseFromParent several
times for the same PHI node, resulting in segmentation faults.
This problem was supposed to be fixed in rL327250, but due to
the non-determinism(?) it only appeared to be fixed (I still
got crashes sometime when turning on/off -print-after-all etc
to get different iteration order in the DenseSets).
With this patch we follow the deterministic ordering in the
Matched set when replacing the PHI nodes. If we find a new
replacement for an already replaced PHI node we replace the
new replacement by the old replacement instead. This is quite
similar to what happened in the rl327250 patch, but here we
also recursively verify that the old replacement hasn't been
replaced already.
- It was really hard to track down the fault described above
(segementation fault due to doing eraseFromParent multiple
times for the same instruction). The fault was intermittent and
small changes in the code, or simply turning on -print-after-all
etc could make the problem go away. This was basically due to
the iteration over PhiNodesToMatch in MatchPhiSet no being
deterministic. Therefore I've changed the data structure for
the SimplificationTracker::AllPhiNodes into an SmallSetVector.
This gives a deterministic behavior.
Reviewers: skatkov, john.brawn
Reviewed By: skatkov
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327961
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Andrei Elovikov [Tue, 20 Mar 2018 09:04:39 +0000 (09:04 +0000)]
[LV] Let recordVectorLoopValueForInductionCast to check if IV was created from the cast.
Summary:
It turned out to be error-prone to expect the callers to handle that - better to
leave the decision to this routine and make the required data to be explicitly
passed to the function.
This handles the case that was missed in the r322473 and fixes the assert
mentioned in PR36524.
Reviewers: dorit, mssimpso, Ayal, dcaballe
Reviewed By: dcaballe
Subscribers: Ka-Ka, hiraditya, dneilson, hsaito, llvm-commits
Differential Revision: https://reviews.llvm.org/D43812
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327960
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Jonas Paulsson [Tue, 20 Mar 2018 08:29:19 +0000 (08:29 +0000)]
[SystemZ] Add "REQUIRES: asserts" to test case to fix build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327958
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Martin Storsjo [Tue, 20 Mar 2018 06:19:38 +0000 (06:19 +0000)]
[X86] Properly implement the calling convention for f80 for mingw/x86_64
In these cases, both parameters and return values are passed
as a pointer to a stack allocation.
MSVC doesn't use the f80 data type at all, while it is used
for long doubles on mingw.
Normally, this part of the calling convention is handled
within clang, but for intrinsics that are lowered to libcalls,
it may need to be handled within llvm as well.
Differential Revision: https://reviews.llvm.org/D44592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327957
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Lang Hames [Tue, 20 Mar 2018 05:56:58 +0000 (05:56 +0000)]
[ORC] Don't fully qualify explicit destructor call -- it confuses some compilers.
This should fix the builder failure at
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/19224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327955
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Craig Topper [Tue, 20 Mar 2018 05:00:20 +0000 (05:00 +0000)]
[X86] Rename MOVSX32_NOREXrr8 to MOVSX32rr8_NOREX so that the scheduler model regular expressions will pick it up with the regular version.
Do the same for MOVSX32_NOREXrm8, MOVZX32_NOREXrr8, and MOVZX32_NOREXrm8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327948
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Craig Topper [Tue, 20 Mar 2018 03:55:17 +0000 (03:55 +0000)]
[X86] Fix the SchedRW for memory forms of CMP and TEST.
They were incorrectly marked as RMW operations. Some of the CMP instrucions worked, but the ones that use a similar encoding as RMW form of ADD ended up marked as RMW.
TEST used the same tablegen class as some of the CMPs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327947
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Lang Hames [Tue, 20 Mar 2018 03:49:29 +0000 (03:49 +0000)]
[ORC] Rename SymbolSource to MaterializationUnit, and make the materialization
operation all-or-nothing, rather than allowing materialization on a per-symbol
basis.
This addresses a shortcoming of per-symbol materialization: If a
MaterializationUnit (/SymbolSource) wants to materialize more symbols than
requested (which is likely: most materializers will want to materialize whole
modules) then it needs a way to notify the symbol table about the extra symbols
being materialized. This process (checking what has been requested against what
is being provided and notifying the symbol table about the difference) has to
be repeated at every level of the JIT stack. Making materialization
all-or-nothing eliminates this issue, simplifying both materializer
implementations and the symbol table (VSO class) API. The cost is that
per-symbol materialization (e.g. for individual symbols in a module) now
requires multiple MaterializationUnits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327946
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Craig Topper [Tue, 20 Mar 2018 03:02:03 +0000 (03:02 +0000)]
[X86] Add TEST16mi/TEST32mi/TEST64mi32 to the Sandybridge/Haswell/Broadwell/Skylake scheduler models.
Move it from a load+store group on SNB to a load only group, the same group as CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327944
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Craig Topper [Tue, 20 Mar 2018 03:01:59 +0000 (03:01 +0000)]
[X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Bridge scheduler model.
I assume these match the generic immediate version like they do in the other models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327943
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Quentin Colombet [Tue, 20 Mar 2018 02:44:40 +0000 (02:44 +0000)]
[ShrinkWrap] Take into account landing pad
When scanning the function for CSRs uses and defs, also check if
the basic block are landing pads.
Consider that landing pads needs the CSRs to be properly set.
That way we force the prologue/epilogue to always be pushed out
of the problematic "throw" region. The "throw" region is
problematic because the jumps are not properly modeled.
Fixes PR36513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327942
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David Blaikie [Tue, 20 Mar 2018 02:14:50 +0000 (02:14 +0000)]
Fix layering between llvm-c and Support by factoring out some typedefs into Support
llvm-c depends on Support, but Support (TargetRegistry) uses some of
llvm-c's typedefs. Move those into a Support header to be used from both
llvm-c and Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327940
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Shiva Chen [Tue, 20 Mar 2018 01:39:17 +0000 (01:39 +0000)]
[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
E.g.
bar (int x)
{
char p[x];
push outgoing variables for foo.
call foo
}
We need to generate stack adjustment instructions for outgoing arguments by
eliminateCallFramePseudoInstr when the function contains variable size
objects to avoid outgoing variables corrupt the variable size object.
Default hasReservedCallFrame will return !hasFP().
We don't want to generate extra sp adjustment instructions when hasFP()
return true, So We override hasReservedCallFrame as !hasVarSizedObjects().
Differential Revision: https://reviews.llvm.org/D43752
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327938
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Craig Topper [Tue, 20 Mar 2018 01:30:21 +0000 (01:30 +0000)]
[X86] Fix the SNB scheduler for BLENDVB.
PBLENDVBrr0 was with the memory version of VBLENDVB and PBLENDVBrm0 was missing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327937
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Rafael Espindola [Tue, 20 Mar 2018 01:06:29 +0000 (01:06 +0000)]
Run dos2unix on a test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327934
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Aaron Smith [Tue, 20 Mar 2018 01:04:21 +0000 (01:04 +0000)]
[DebugInfoPDB] Add backward support flags to PDB_NameSearchFlags
For NS_CaseInFileNameExt support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327933
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Vitaly Buka [Tue, 20 Mar 2018 00:45:03 +0000 (00:45 +0000)]
Object: Fix handling of @@@ in .symver directive
Summary:
name@@@nodename is going to be replaced with name@@nodename if symbols is
defined in the assembled file, or name@nodename if undefined.
https://sourceware.org/binutils/docs/as/Symver.html
Fixes PR36623
Reviewers: pcc, espindola
Subscribers: mehdi_amini, hiraditya
Differential Revision: https://reviews.llvm.org/D44274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327930
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Vitaly Buka [Tue, 20 Mar 2018 00:38:33 +0000 (00:38 +0000)]
Object: Move attribute calculation into RecordStreamer. NFC
Summary: Preparation for D44274
Reviewers: pcc, espindola
Subscribers: hiraditya
Differential Revision: https://reviews.llvm.org/D44276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327928
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Aaron Smith [Mon, 19 Mar 2018 22:58:50 +0000 (22:58 +0000)]
[SelectionDAG] Transfer DbgValues when integer operations are promoted
Summary:
DbgValue nodes were not transferred when integer DAG nodes were promoted. For example, if an i32 add node was promoted to an i64 add node by DAGTypeLegalizer::PromoteIntegerResult(), its DbgValue node was not transferred to the new node. The simple fix is to update SetPromotedInteger() to transfer DbgValues.
Add AArch64/dbg-value-i8.ll to test this change and fix ARM/debug-info-d16-reg.ll which had the wrong DILocalVariable nodes with arg numbers even though they are not for function parameters.
Patch by Se Jong Oh!
Reviewers: vsk, JDevlieghere, aprantl
Reviewed By: JDevlieghere
Subscribers: javed.absar, kristof.beyls, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D44546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327919
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Jessica Paquette [Mon, 19 Mar 2018 22:48:40 +0000 (22:48 +0000)]
[MachineOutliner] AArch64: Emit CFI instructions when outlining calls
When outlining calls, the outliner needs to update CFI to ensure that, say,
exception handling works. This commit adds that functionality and adds a test
just for call outlining.
Call outlining stuff in machine-outliner.mir should be moved into
machine-outliner-calls.mir in a later commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327917
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Craig Topper [Mon, 19 Mar 2018 22:25:26 +0000 (22:25 +0000)]
[DAGCombiner] Fix type in comment. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327916
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Craig Topper [Mon, 19 Mar 2018 21:58:02 +0000 (21:58 +0000)]
[X86] Simplify the AVX512 code in LowerTruncate a little.
We don't need to create an ISD::TRUNCATE node to return, we started with one and can return it. Also remove the call to getExtendInVec, the result is just going to be a getNode of that value passed in.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327914
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Serge Guelton [Mon, 19 Mar 2018 21:35:30 +0000 (21:35 +0000)]
Accept any filepath in llvm_check_source_file_list
Cmake function llvm_check_source_file_list currently only accepts paths
relative to current CMAKE_SOURCE_DIR or relative to argument SOURCE_DIR.
Extend it to accept any path, including absolute ones.
Differential revision: https://reviews.llvm.org/D44625
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327912
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Aaron Smith [Mon, 19 Mar 2018 21:20:04 +0000 (21:20 +0000)]
[PDB] Add a method to get the full path of the source file for PDBSymbolCompiland
Summary:
Redefine PDBSymbolCompiland::getSourceFileName() to return the filename (w/o directory) of the source file that is used to compile the compiland. This is because the result returned previously is ambiguous. It could be the filename, relative path or full path of the source file.
Move the implementation of SymbolFilePDB::GetSourceFileNameForPDBCompiland() into a new method PDBSymbolCompiland::getSourceFileFullPath().
Reviewers: zturner, rnk, llvm-commits
Reviewed By: zturner
Differential Revision: https://reviews.llvm.org/D44458
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327910
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Aaron Smith [Mon, 19 Mar 2018 21:18:39 +0000 (21:18 +0000)]
[PDB] Add exclusive methods to derived symbol class
Summary: This commit adds two methods to the PDBSymboFunc class used in parsing symbols. getLineNumbers() is used to determine a Function symbol's declaration and getCompilandId() is used to initialize the SymbolContext field sc.comp_unit.
Reviewers: zturner, rnk, llvm-commits
Reviewed By: zturner
Differential Revision: https://reviews.llvm.org/D44457
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327909
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Krzysztof Parzyszek [Mon, 19 Mar 2018 21:05:21 +0000 (21:05 +0000)]
[Hexagon] Add REQUIRES: asserts to test/CodeGen/Hexagon/v6vec_inc1.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327907
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Zachary Turner [Mon, 19 Mar 2018 20:41:59 +0000 (20:41 +0000)]
Revert "Support embedding natvis files in PDBs."
This is causing a test failure on a certain bot, so I'm removing
this temporarily until we can figure out the source of the error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327903
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Zachary Turner [Mon, 19 Mar 2018 20:22:48 +0000 (20:22 +0000)]
Remove an unused private variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327900
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Craig Topper [Mon, 19 Mar 2018 20:20:22 +0000 (20:20 +0000)]
[X86] Replace a couple calls to getExtendInVec with getNode and the appropriate target independent EXTEND_VECTOR_INREG opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327899
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Nirav Dave [Mon, 19 Mar 2018 20:19:46 +0000 (20:19 +0000)]
[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"
Reland ISel cycle checking improvements after simplifying node id
invariant traversal and correcting typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327898
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Martin Storsjo [Mon, 19 Mar 2018 20:06:50 +0000 (20:06 +0000)]
[ARM, AArch64] Check the no-stack-arg-probe attribute for dynamic stack probes
This extends the use of this attribute on ARM and AArch64 from
SVN r325900 (where it was only checked for fixed stack
allocations on ARM/AArch64, but for all stack allocations on X86).
This also adds a testcase for the existing use of disabling the
fixed stack probe with the attribute on ARM and AArch64.
Differential Revision: https://reviews.llvm.org/D44291
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327897
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Alina Sbirlea [Mon, 19 Mar 2018 20:05:01 +0000 (20:05 +0000)]
Add cast to Type*, fix failure from r327894.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327896
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Zachary Turner [Mon, 19 Mar 2018 19:53:51 +0000 (19:53 +0000)]
Support embedding natvis files in PDBs.
Natvis is a debug language supported by Visual Studio for
specifying custom visualizers. The /NATVIS option is an
undocumented link.exe flag which will take a .natvis file
and "inject" it into the PDB. This way, you can ship the
debug visualizers for a program along with the PDB, which
is very useful for postmortem debugging.
This is implemented by adding a new "named stream" to the
PDB with a special name of /src/files/<natvis file name>
and simply copying the contents of the xml into this file.
Additionally, we need to emit a single stream named
/src/headerblock which contains a hash table of embedded
files to records describing them.
This patch adds this functionality, including the /NATVIS
option to lld-link.
Differential Revision: https://reviews.llvm.org/D44328
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327895
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Alina Sbirlea [Mon, 19 Mar 2018 19:49:28 +0000 (19:49 +0000)]
Make ConstantDataArray::get constructor templated. Will support signed integers.
Summary: Make ConstantDataArray::get() constructors a single templated one.
Reviewers: timshen, rsmith
Subscribers: sanjoy, llvm-commits, jlebar
Differential Revision: https://reviews.llvm.org/D44337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327894
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Sanjay Patel [Mon, 19 Mar 2018 19:26:22 +0000 (19:26 +0000)]
[AMDGPU] change test to avoid NaN math
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327891
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Sanjay Patel [Mon, 19 Mar 2018 19:23:53 +0000 (19:23 +0000)]
[AMDGPU] adjust tests to be nan-free
As suggested in D44521 - bitcast to integer for the math,
so we preserve the intent of these tests when NaN math
gets folded away.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327890
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Lei Huang [Mon, 19 Mar 2018 19:22:52 +0000 (19:22 +0000)]
[Power9]Legalize and emit code for quad-precision copySign/abs/nabs/neg/sqrt
Legalize and emit code for quad-precision floating point operations:
* xscpsgnqp
* xsabsqp
* xsnabsqp
* xsnegqp
* xssqrtqp
Differential Revision: https://reviews.llvm.org/D44530
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327889
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Andrea Di Biagio [Mon, 19 Mar 2018 19:14:06 +0000 (19:14 +0000)]
[llvm-mca] Remove unused method from ResourceManager. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327888
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Andrea Di Biagio [Mon, 19 Mar 2018 19:09:38 +0000 (19:09 +0000)]
[llvm-mca] Simplify code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327886
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Krzysztof Parzyszek [Mon, 19 Mar 2018 19:03:18 +0000 (19:03 +0000)]
[Hexagon] Add a few more lit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327884
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Craig Topper [Mon, 19 Mar 2018 19:00:37 +0000 (19:00 +0000)]
[X86] Add JMP16r and JMP32r to Sandybridge scheduler model.
Fixes PR36010
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327883
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Craig Topper [Mon, 19 Mar 2018 19:00:35 +0000 (19:00 +0000)]
[X86] Remove OUT32rr/OUT8rr/OUT32ri/OUT8ri from Sandybridge scheduler model.
PR35590 was already filed for this information being wrong. It's probably better to default to WriteSystem behavior instead of using something completely wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327882
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Craig Topper [Mon, 19 Mar 2018 19:00:32 +0000 (19:00 +0000)]
[X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skylake scheduler models.
JRCXZ was already present, but not the others.
We never codegen this instruction so this doesn't affect much just trying to get them all into a single generated scheduler class in the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327881
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Craig Topper [Mon, 19 Mar 2018 19:00:29 +0000 (19:00 +0000)]
[X86] Correct regular expression in Zen scheduler model that was excluding JECXZ instruction.
The regex was looking for JECXZ_32 or JECXZ_64, but their is just one instruction called JECXZ. They used to exist as separate instructions, but were merged over 3 years ago.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327880
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Craig Topper [Mon, 19 Mar 2018 19:00:26 +0000 (19:00 +0000)]
[X86] Correct the SchedRW on (V)MOVAPSrr_REV and similar to match their non _REV counterparts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327879
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Lei Huang [Mon, 19 Mar 2018 18:52:20 +0000 (18:52 +0000)]
[PowerPC][Power9]Legalize and emit code for quad-precision add/div/mul/sub
Legalize and emit code for quad-precision floating point operations:
* xsaddqp
* xssubqp
* xsdivqp
* xsmulqp
Differential Revision: https://reviews.llvm.org/D44506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327878
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Nemanja Ivanovic [Mon, 19 Mar 2018 18:50:02 +0000 (18:50 +0000)]
[PowerPC] Make AddrSpaceCast noop
PowerPC targets do not use address spaces. As a result, we can get selection
failures with address space casts. This patch makes those casts noops.
Patch by Valentin Churavy.
Differential revision: https://reviews.llvm.org/D43781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327877
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Craig Topper [Mon, 19 Mar 2018 17:58:41 +0000 (17:58 +0000)]
[X86] Add the rest of the TEST with immediate instructions to the scheduler models to match their 8-bit counterpart.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327874
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Craig Topper [Mon, 19 Mar 2018 17:46:59 +0000 (17:46 +0000)]
[X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to match MOV8ri. Correct SchedRW and itinerary for MOV32ri64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327872
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Craig Topper [Mon, 19 Mar 2018 17:31:41 +0000 (17:31 +0000)]
[X86] Remove sse41 specific code from lowering v16i8 multiply
With the SRAs removed from the SSE2 code in D44267, then there doesn't appear to be any advantage to the sse41 code. The punpcklbw instruction and pmovsx seem to have the same latency and throughput on most CPUs. And the SSE41 code requires moving the upper 64-bits into the lower 64-bit before the sign extend can be done. The unpckhbw in sse2 code can do better than that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327869
91177308-0d34-0410-b5e6-
96231b3b80d8
Craig Topper [Mon, 19 Mar 2018 16:38:33 +0000 (16:38 +0000)]
[X86] Make the multiply and divide itineraries more consistent.
Sometimes we used the same itinerary for MEM and REG forms, but that seems inconsistent with our usual usage.
We also used the MUL8 itinerary for MULX32/64 which was also weird.
The test changes are because we were using IIC_IMUL32_RR and IIC_IMUL64_RR instead of IIC_IMUL32_REG/IIC_IMUL64_REG for the 32 and 64 bit multiplies that produce double width result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327866
91177308-0d34-0410-b5e6-
96231b3b80d8