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Craig Topper [Fri, 24 Nov 2017 19:32:34 +0000 (19:32 +0000)]
Revert 318963 "[APInt] Don't print debug messages from the APInt knuth division algorithm by default"
I seem to have botched the logic when switching to push_macro
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318964
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Craig Topper [Fri, 24 Nov 2017 19:13:24 +0000 (19:13 +0000)]
[APInt] Don't print debug messages from the APInt knuth division algorithm by default
Debug builds currently print out low level details of the Knuth division algorithm when -debug is used. This information isn't useful in most cases and just adds noise to the log.
This adds a new preprocessor flag to enable the prints in the knuth division code in APInt.
Differential Revision: https://reviews.llvm.org/D40404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318963
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Simon Dardis [Fri, 24 Nov 2017 16:45:28 +0000 (16:45 +0000)]
[CodeGenPrepare] Check that erased sunken address are not reused
CodeGenPrepare sinks address computations from one basic block to another
and attempts to reuse address computations that have already been sunk. If
the same address computation appears twice with the first instance as an
operand of a load whose result is an operand to a simplifable select,
CodeGenPrepare simplifies the select and recursively erases the now dead
instructions. CodeGenPrepare then attempts to use the erased address
computation for the second load.
Fix this by erasing the cached address value if it has zero uses before
looking for the address value in the sunken address map.
This partially resolves PR35209.
Thanks to Alexander Richardson for reporting the issue!
This fixed version relands r318032 which was reverted in r318049 due to
sanitizer buildbot failures.
Reviewers: john.brawn
Differential Revision: https://reviews.llvm.org/D39841
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318956
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Dmitry Preobrazhensky [Fri, 24 Nov 2017 15:37:14 +0000 (15:37 +0000)]
[AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16
See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629
Reviewers: artem.tamazov, SamWot, arsenm
Differential Revision: https://reviews.llvm.org/D39488
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318955
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Dylan McKay [Fri, 24 Nov 2017 15:36:43 +0000 (15:36 +0000)]
[AVR] Use the short form of 'clr <reg>'
r318895 made it so that the simpler instruction aliases are printed
rather than their expanded form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318954
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Benjamin Kramer [Fri, 24 Nov 2017 14:55:41 +0000 (14:55 +0000)]
Make helpers static. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318953
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Javed Absar [Fri, 24 Nov 2017 14:35:38 +0000 (14:35 +0000)]
[SCEV] : Simplify loop to range-loop.NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318952
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John Brawn [Fri, 24 Nov 2017 14:10:45 +0000 (14:10 +0000)]
[CGP] Make optimizeMemoryInst able to combine more kinds of ExtAddrMode fields
This patch extends the recent work in optimizeMemoryInst to make it able to
combine more ExtAddrMode fields than just the BaseReg.
This fixes some benchmark regressions introduced by r309397, where GVN PRE is
hoisting a getelementptr such that it can no longer be combined into the
addressing mode of the load or store that uses it.
Differential Revision: https://reviews.llvm.org/D38133
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318949
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Aleksandar Beserminji [Fri, 24 Nov 2017 14:00:47 +0000 (14:00 +0000)]
[mips] Set microMIPS ASE flag
This patch fixes an issue where microMIPS ASE flag is not set
when a function has micromips attribute or when .set micromips
directive is used.
Differential Revision: https://reviews.llvm.org/D40316
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318948
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Dmitry Preobrazhensky [Fri, 24 Nov 2017 13:22:38 +0000 (13:22 +0000)]
[AMDGPU][MC][GFX9] Added support of 'inst_offset' modifier for compatibility with SP3
See bug 35329: https://bugs.llvm.org//show_bug.cgi?id=35329
Reviewers: arsenm, vpykhtin, artem.tamazov
Differential Revision: https://reviews.llvm.org/D40350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318947
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Benjamin Kramer [Thu, 23 Nov 2017 21:07:11 +0000 (21:07 +0000)]
[YAMLParser] Fix unused variable warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318936
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Benjamin Kramer [Thu, 23 Nov 2017 20:57:20 +0000 (20:57 +0000)]
[YAMLParser] Don't crash on null keys in KeyValueNodes.
Found by clangd-fuzzer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318935
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Craig Topper [Thu, 23 Nov 2017 19:25:45 +0000 (19:25 +0000)]
[X86] Don't invert NewCC variable while processing the jcc/setcc/cmovcc instructions in optimizeCompareInstr.
The NewCC variable is calculated outside of the loop that processes jcc/setcc/cmovcc instructions. If we invert it during the loop it can cause an incorrect value to be used by a later iteration. Instead only read it during the loop and use a new variable to store the possibly inverted value.
Fixes PR35399.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318934
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Craig Topper [Thu, 23 Nov 2017 18:41:21 +0000 (18:41 +0000)]
[X86] Teach isel that X86ISD::CMPM_RND zeros the upper bits of the mask register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318933
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Craig Topper [Thu, 23 Nov 2017 18:41:20 +0000 (18:41 +0000)]
[X86] Remove some unneeded opcodes from getVectorMaskingNode. NFC
We never reach here with these opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318932
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Craig Topper [Thu, 23 Nov 2017 18:41:19 +0000 (18:41 +0000)]
[X86] Add X86ISD::CMPM_RND to getVectorMaskingNode to select ISD::AND instead of ISD::VSELECT
A later DAG combine will turn the VSELECT into an AND, but we have the other mask compare opcodes here so add this one too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318931
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Craig Topper [Thu, 23 Nov 2017 18:41:18 +0000 (18:41 +0000)]
[X86] Remove some dead code leftover from when i1 was a legal type. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318930
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Craig Topper [Thu, 23 Nov 2017 18:41:17 +0000 (18:41 +0000)]
[X86] Remove some dead code. NFC
AVX512 code never reaches here so we don't need to handle X86ISD::CMPM as an opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318929
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Alexander Potapenko [Thu, 23 Nov 2017 15:06:51 +0000 (15:06 +0000)]
MSan: remove an unnecessary cast. NFC for userspace instrumenetation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318923
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Simon Pilgrim [Thu, 23 Nov 2017 13:50:27 +0000 (13:50 +0000)]
[X86][SSE] Use (V)PHMINPOSUW for vXi16 SMAX/SMIN/UMAX/UMIN horizontal reductions (PR32841)
(V)PHMINPOSUW determines the UMIN element in an v8i16 input, with suitable bit flipping it can also be used for SMAX/SMIN/UMAX cases as well.
This patch matches vXi16 SMAX/SMIN/UMAX/UMIN horizontal reductions and reduces the input down to a v8i16 vector before calling (V)PHMINPOSUW.
A later patch will use this for v16i8 reductions as well (PR32841).
Differential Revision: https://reviews.llvm.org/D39729
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318917
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Diana Picus [Thu, 23 Nov 2017 13:26:07 +0000 (13:26 +0000)]
[ARM GlobalISel] Support G_FDIV for s32 and s64
TableGen already generates code for selecting a G_FDIV, so we only need
to add a test.
For the legalizer and reg bank select, we do the same thing as for the
other floating point binary operations: either mark as legal if we have
a FP unit or lower to a libcall, and map to the floating point
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318915
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Ying Yi [Thu, 23 Nov 2017 13:23:21 +0000 (13:23 +0000)]
Reverted rL318911 since it broke the sanitizer-windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318914
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Ying Yi [Thu, 23 Nov 2017 12:48:41 +0000 (12:48 +0000)]
[lit] Implement non-pipelined ‘mkdir’, ‘diff’ and ‘rm’ commands internally
Summary:
The internal shell already supports 'cd', ‘export’ and ‘echo’ commands.
This patch adds implementation of non-pipelined ‘mkdir’, ‘diff’ and ‘rm’
commands as the internal shell builtins.
Reviewers: Zachary Turner, Reid Kleckner
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39567
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318911
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Diana Picus [Thu, 23 Nov 2017 12:44:20 +0000 (12:44 +0000)]
[ARM GlobalISel] Support G_FMUL for s32 and s64
TableGen already generates code for selecting a G_FMUL, so we only need
to add a test for that part.
For the legalizer and reg bank select, we do the same thing as the other
floating point binary operators: either mark as legal if we have a FP
unit or lower to a libcall, and map to the floating point registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318910
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Simon Dardis [Thu, 23 Nov 2017 12:38:04 +0000 (12:38 +0000)]
[mips] Use the delay slot filler to convert branches for microMIPSR6.
The MIPS delay slot filler converts delay slot branches into compact
forms for the MIPS ISAs which support them. For branches that compare
(in)equality with with zero, it converts them into branches with implict
zero register operands. These branches have a slightly greater range
than normal two register operands branches.
Changing the branches at this point in the pipeline offers the long
branch pass the ability to mark better judgements if a long branch
sequence is required.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D40314
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318908
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Coby Tayree [Thu, 23 Nov 2017 11:15:50 +0000 (11:15 +0000)]
[x86][icelake]BITALG
2/3
vpshufbitqmb encoding
3/3
vpshufbitqmb intrinsics
Differential Revision: https://reviews.llvm.org/D40222
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318904
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Alexander Potapenko [Thu, 23 Nov 2017 08:34:32 +0000 (08:34 +0000)]
[MSan] Move the access address check before the shadow access for that address
MSan used to insert the shadow check of the store pointer operand
_after_ the shadow of the value operand has been written.
This happens to work in the userspace, as the whole shadow range is
always mapped. However in the kernel the shadow page may not exist, so
the bug may cause a crash.
This patch moves the address check in front of the shadow access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318901
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George Rimar [Thu, 23 Nov 2017 06:52:44 +0000 (06:52 +0000)]
Revert r318822 "[llvm-tblgen] - Stop using std::string in RecordKeeper."
It reported to have problems with memory sanitizers and DBUILD_SHARED_LIBS=ON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318899
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Max Kazantsev [Thu, 23 Nov 2017 06:14:39 +0000 (06:14 +0000)]
[IRCE][NFC] Add no wrap flags to no-wrapping SCEV calculation
In a lambda where we expect to have result within bounds, add respective `nsw/nuw` flags to
help SCEV just in case if it fails to figure them out on its own.
Differential Revision: https://reviews.llvm.org/D40168
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318898
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Leslie Zhai [Thu, 23 Nov 2017 04:11:11 +0000 (04:11 +0000)]
Add backend name to AVR Target to enable runtime info to be fed back into TableGen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318895
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Craig Topper [Thu, 23 Nov 2017 03:24:01 +0000 (03:24 +0000)]
[X86] Turn an if condition that should always be true into an assert. NFCI
If Values.size() == 0, we should have returned 0 or undef earlier. If it was 1, it's a splat and we already handled that too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318894
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Craig Topper [Thu, 23 Nov 2017 03:24:00 +0000 (03:24 +0000)]
[X86] Remove unnecessary check for is128BitVector. NFC
256 and 512 bit vectors were picked off earlier in the function. Lots of code between there and here already assumed 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318893
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Craig Topper [Thu, 23 Nov 2017 03:23:59 +0000 (03:23 +0000)]
[X86] Simplify some bitmasking and use llvm_unreachable to mark an impossible case. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318892
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Craig Topper [Thu, 23 Nov 2017 03:23:58 +0000 (03:23 +0000)]
[X86] Remove a ternary operator that can only ever be false. NFC
We are checking for AVX512 in an SSE1 only block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318891
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Yaxun Liu [Thu, 23 Nov 2017 03:08:51 +0000 (03:08 +0000)]
[NFC] CodeGen: Handle shift amount type in DAGTypeLegalizer::SplitInteger
This patch reverts change to X86TargetLowering::getScalarShiftAmountTy in
rL318727 and move the logic to DAGTypeLegalizer::SplitInteger.
The reason is that getScalarShiftAmountTy returns a shift amount type that
is suitable for common use cases in CodeGen. DAGTypeLegalizer::SplitInteger
is a rare situation which requires a shift amount type larger than what
getScalarShiftAmountTy. In this case, it is more reasonable to do special
handling of shift amount type in DAGTypeLegalizer::SplitInteger only. If
similar situations arises the logic may be moved to a separate function.
Differential Revision: https://reviews.llvm.org/D40320
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318890
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David Blaikie [Thu, 23 Nov 2017 00:08:40 +0000 (00:08 +0000)]
Instrumentation.h: Remove dead/untested code for DFSan JIT support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318887
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Craig Topper [Wed, 22 Nov 2017 23:35:12 +0000 (23:35 +0000)]
[X86] Regenerate the vector-popcnt and vector-tzcnt tests to get BITALG CHECK linse on all functions not just the vXi16/vXi8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318885
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Evandro Menezes [Wed, 22 Nov 2017 22:48:50 +0000 (22:48 +0000)]
[AArch64] Adjust the cost model for Exynos M1 and M2
Fix the modeling of some loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318884
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Fedor Sergeev [Wed, 22 Nov 2017 20:59:53 +0000 (20:59 +0000)]
IR printing improvement for loop passes
Summary:
Loop-pass printing is somewhat deficient since it does not provide the
context around the loop (e.g. preheader). This context information becomes
pretty essential when analyzing transformations that move stuff out of the loop.
Extending printLoop to cover preheader and exit blocks (if any).
Reviewers: sanjoy, silvas, weimingz
Reviewed By: sanjoy
Subscribers: apilipenko, skatkov, llvm-commits
Differential Revision: https://reviews.llvm.org/D40246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318878
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:56:23 +0000 (20:56 +0000)]
[Hexagon] Implement buildVector32 and buildVector64 as utility functions
Change LowerBUILD_VECTOR to use those functions. This commit will tempora-
rily affect constant vector generation (it will generate constant-extended
values instead of non-extended combines), but the code for the general case
should be better. The constant selection part will be fixed later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318877
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:55:41 +0000 (20:55 +0000)]
[Hexagon] Add patterns to select A2_combine_ll and its variants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318876
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Krzysztof Parzyszek [Wed, 22 Nov 2017 20:43:00 +0000 (20:43 +0000)]
[Hexagon] Remove trailing spaces, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318875
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Paul Robinson [Wed, 22 Nov 2017 20:31:39 +0000 (20:31 +0000)]
Add a missing include found by modules bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318873
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Craig Topper [Wed, 22 Nov 2017 20:05:57 +0000 (20:05 +0000)]
[X86] Support v32i16/v64i8 CTLZ using lookup table.
Had to tweak the setcc's used by the code to use a vXi1 result type with a sign extend back to vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318871
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Craig Topper [Wed, 22 Nov 2017 20:05:54 +0000 (20:05 +0000)]
[X86] Move the BITALG setOperationAction code into the hasBWI section to match what is done for VPOPCNTDQ in the AVX512F block. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318870
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Craig Topper [Wed, 22 Nov 2017 20:05:51 +0000 (20:05 +0000)]
[X86] Sink the MGATHER setOperationActions for AVX2 into the AVX block where most of the rest of the AVX2 legalization lives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318869
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Rafael Espindola [Wed, 22 Nov 2017 20:02:57 +0000 (20:02 +0000)]
Remove unnecessary code.
There is already an RAII in place to discard the temporary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318868
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Rafael Espindola [Wed, 22 Nov 2017 19:59:05 +0000 (19:59 +0000)]
Allow TempFile::discard to be called twice.
We already allowed keep+discard. It is important to be able to discard
a temporary if a rename fail. It is also convenient as it allows the
use of RAII for discarding.
Allow discarding twice for similar reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318867
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Paul Robinson [Wed, 22 Nov 2017 18:39:26 +0000 (18:39 +0000)]
Remove unnecessary include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318861
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Peter Collingbourne [Wed, 22 Nov 2017 18:27:31 +0000 (18:27 +0000)]
CachePruning: Allow limiting the number of files in the cache directory.
The default limit is
1000000 but it can be configured with a cache
policy. The motivation is that some filesystems (notably ext4) have
a limit on the number of files that can be contained in a directory
(separate from the inode limit).
Differential Revision: https://reviews.llvm.org/D40327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318857
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Paul Robinson [Wed, 22 Nov 2017 18:23:55 +0000 (18:23 +0000)]
[DwarfDump] -debug-line=offset applies to .dwo too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318856
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Craig Topper [Wed, 22 Nov 2017 18:23:40 +0000 (18:23 +0000)]
[X86] Spell penryn correctly in some comments. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318855
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Yaxun Liu [Wed, 22 Nov 2017 16:13:35 +0000 (16:13 +0000)]
[AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argument
SITargetLowering::LowerCall uses dummy pointer info for byval argument, which causes
flat load instead of buffer load.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D40040
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318844
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Paul Robinson [Wed, 22 Nov 2017 15:48:30 +0000 (15:48 +0000)]
[DebugInfo] Dump a .debug_line section, including line-number program,
without any compile units.
Differential Revision: https://reviews.llvm.org/D40114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318842
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Dmitry Preobrazhensky [Wed, 22 Nov 2017 15:47:27 +0000 (15:47 +0000)]
[AMDGPU][mc][tests] Updated generated lit tests for GFX8/9
Summary:
Added tests to better cover features introduced by commit rL318675.
See http://llvm.org/viewvc/llvm-project?view=revision&revision=318675
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318841
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Paul Robinson [Wed, 22 Nov 2017 15:33:17 +0000 (15:33 +0000)]
[DWARFv5] Support DW_FORM_strp in the .debug_line.dwo header.
As a side effect, the .debug_line section will be dumped in physical
order, rather than in the order that compile units refer to their
associated portions of the .debug_line section. These are probably
always the same order anyway, and no tests noticed the difference.
Differential Revision: https://reviews.llvm.org/D39854
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318839
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Paul Robinson [Wed, 22 Nov 2017 15:14:49 +0000 (15:14 +0000)]
[DWARF] Fix handling of extended line-number opcodes
Differential Revision: https://reviews.llvm.org/D40200
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318838
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Nicolai Haehnle [Wed, 22 Nov 2017 12:25:21 +0000 (12:25 +0000)]
AMDGPU: Consider memory dependencies with moved instructions in SILoadStoreOptimizer
Summary:
This bug seems to have gone unnoticed because critical cases with LDS
instructions are eliminated by the peephole optimizer.
However, equivalent situations arise with buffer loads and stores
as well, so this fixes regressions since r317751 ("AMDGPU: Merge
S_BUFFER_LOAD_DWORD_IMM into x2, x4").
Fixes at least:
KHR-GL45.shader_storage_buffer_object.basic-operations-case1-cs
KHR-GL45.cull_distance.functional
piglit tes-input-gl_ClipDistance.shader_test
... and probably more
Change-Id: I0e371536288eb8e6afeaa241a185266fd45d129d
Reviewers: arsenm, mareko, rampitec
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D40303
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318829
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Jonas Paulsson [Wed, 22 Nov 2017 08:58:30 +0000 (08:58 +0000)]
[DAGCombiner] Bugfix in isAlias().
Since i1 is a legal type, this:
NumBytes = Op1->getMemoryVT().getSizeInBits() >> 3;
is wrong and should be instead
NumBytes = Op0->getMemoryVT().getStoreSize();
There seems to be more places where this should be fixed outside DAGCombiner.
Review: Hal Finkel
https://bugs.llvm.org/show_bug.cgi?id=35366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318824
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Craig Topper [Wed, 22 Nov 2017 08:10:54 +0000 (08:10 +0000)]
[X86] Add an X86ISD::MSCATTER node for consistency with the X86ISD::MGATHER.
This makes the fact that X86 needs an explicit mask output not part of the type constraint for the ISD::MSCATTER.
This also gives the X86ISD::MGATHER/MSCATTER nodes a common base class simplifying the address selection code in X86ISelDAGToDAG.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318823
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George Rimar [Wed, 22 Nov 2017 07:53:48 +0000 (07:53 +0000)]
[llvm-tblgen] - Stop using std::string in RecordKeeper.
RecordKeeper::getDef() is a hot place, it shows up in profiling
and it creates std::string instance for each search in RecordMap
though RecordKeeper::RecordMap can use StringRef as a key
instead to avoid that. Patch do that change.
Differential revision: https://reviews.llvm.org/D40170
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318822
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Craig Topper [Wed, 22 Nov 2017 07:11:03 +0000 (07:11 +0000)]
[X86] Lower all ISD::MGATHER nodes to X86ISD:MGATHER.
Now we consistently represent the mask result without relying on isel ignoring it.
We now have a more general SDNode and type constraints to represent these nodes in isel patterns. This allows us to present both both vXi1 and XMM/YMM mask types with a single set of constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318821
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Craig Topper [Wed, 22 Nov 2017 07:11:01 +0000 (07:11 +0000)]
[SelectionDAG] Add a isel matcher op to check the type of node results other than result 0.
I plan to use this to check the type of the mask result of masked gathers in the X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318820
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Max Kazantsev [Wed, 22 Nov 2017 06:21:39 +0000 (06:21 +0000)]
[SCEV] Strengthen variance condition in calculateLoopDisposition
Given loops `L1` and `L2` with AddRecs `AR1` and `AR2` varying in them respectively.
When identifying loop disposition of `AR2` w.r.t. `L1`, we only say that it is varying if
`L1` contains `L2`. But there is also a possible situation where `L1` and `L2` are
consecutive sibling loops within the parent loop. In this case, `AR2` is also varying
w.r.t. `L1`, but we don't correctly identify it.
It can lead, for exaple, to attempt of incorrect folding. Consider:
AR1 = {a,+,b}<L1>
AR2 = {c,+,d}<L2>
EXAR2 = sext(AR1)
MUL = mul AR1, EXAR2
If we incorrectly assume that `EXAR2` is invariant w.r.t. `L1`, we can end up trying to
construct something like: `{a * {c,+,d}<L2>,+,b * {c,+,d}<L2>}<L1>`, which is incorrect
because `AR2` is not available on entrance of `L1`.
Both situations "`L1` contains `L2`" and "`L1` preceeds sibling loop `L2`" can be handled
with one check: "header of `L1` dominates header of `L2`". This patch replaces the old
insufficient check with this one.
Differential Revision: https://reviews.llvm.org/D39453
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318819
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Davide Italiano [Wed, 22 Nov 2017 03:04:55 +0000 (03:04 +0000)]
[SCCP] Pick the right lattice value for constants.
After the dataflow algorithm proves that an argument is constant,
it replaces it value with the integer constant and drops the lattice
value associated to the DEF.
e.g. in the example we have @f() that's called twice:
call @f(undef, ...)
call @f(2, ...)
`undef` MEET 2 = 2 so we replace the argument and all its uses with
the constant 2.
Shortly after, tryToReplaceWithConstantRange() tries to get the lattice
value for the argument we just replaced, causing an assertion.
This function is a little peculiar as it runs when we're doing replacement
and not as part of the solver but still queries the solver.
The fix is that of checking whether we replaced the value already and
get a temporary lattice value for the constant.
Thanks to Zhendong Su for the report!
Fixes PR35357.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318817
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Craig Topper [Tue, 21 Nov 2017 23:36:42 +0000 (23:36 +0000)]
[X86] Move the information about the feature bits used by compiler-rt and shared by Host.cpp to a .def file and TargetParser.h so clang can make use of it.
Since we keep Host.cpp and compiler-rt relatively in sync, clang can use this information as a proxy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318814
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Krzysztof Parzyszek [Tue, 21 Nov 2017 22:13:16 +0000 (22:13 +0000)]
[Hexagon] Add HexagonSubtarget::getVectorLength()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318807
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Peter Collingbourne [Tue, 21 Nov 2017 22:06:20 +0000 (22:06 +0000)]
Object: Improve COFF irsymtab comdat representation.
Change the representation of COFF comdats so that a COFF linker
is able to accurately resolve comdats between IR and native object
files. Specifically, apply name mangling to comdat names consistently
with native object files, and do not export comdats with an internal
leader because they do not affect symbol resolution.
Differential Revision: https://reviews.llvm.org/D40278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318805
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Evandro Menezes [Tue, 21 Nov 2017 21:33:52 +0000 (21:33 +0000)]
[TableGen] Improve error reporting
When searching for a resource unit, use the reference location instead of
the definition location in case of an error.
Differential revision: https://reviews.llvm.org/D40263
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318803
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Krzysztof Parzyszek [Tue, 21 Nov 2017 21:05:51 +0000 (21:05 +0000)]
[Hexagon] Make sure that RDF does not remove EH_LABELs
Since EH_LABELs (and other labels) no longer have "side-effects", they
should be checked for separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318801
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Craig Topper [Tue, 21 Nov 2017 21:05:21 +0000 (21:05 +0000)]
[X86] Allow vpclmulqdq instructions to be commuted during isel to allow load folding.
The commuting patterns for the AVX version actually still had priority over the new patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318800
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Craig Topper [Tue, 21 Nov 2017 21:05:18 +0000 (21:05 +0000)]
[X86] Add BITALG, VAES, VBMI2, VNNI, VPCLMULQDQ, and VPOPCNTDQ instructions to icelake CPU.
This is based on table 1-1 of the October 2017 revision of Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318799
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Nirav Dave [Tue, 21 Nov 2017 19:28:13 +0000 (19:28 +0000)]
Avoid unecessary opsize byte in segment move to memory
Segment moves to memory are always 16-bit. Remove invalid 32 and 64
bit variants.
Recommiting with missing clang inline assembly test change.
Fixes PR34478.
Reviewers: rnk, craig.topper
Subscribers: llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318797
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Craig Topper [Tue, 21 Nov 2017 18:50:41 +0000 (18:50 +0000)]
[X86] Sort bits in getHostCPUFeatures again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318792
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Chad Rosier [Tue, 21 Nov 2017 18:08:34 +0000 (18:08 +0000)]
[AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects.
This partially reverts r298851. The the underlying issue is that we don't
currently model the dependency between mrs (read system register) and
msr (write system register) instructions.
Something like the below should never be reordered:
msr TPIDR_EL0, x0 ;; set thread pointer
mrs x8, TPIDR_EL0 ;; read thread pointer
but was being reordered after r298851. The functional part of the patch
that wasn't reverted needed to remain in place in order to not break
r299462.
PR35317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318788
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Hans Wennborg [Tue, 21 Nov 2017 18:00:01 +0000 (18:00 +0000)]
Fix r318786
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318787
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Nuno Lopes [Tue, 21 Nov 2017 17:53:19 +0000 (17:53 +0000)]
removed unused private method decl. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318786
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Hans Wennborg [Tue, 21 Nov 2017 17:22:19 +0000 (17:22 +0000)]
Rename test/Transforms/CountingFunctionInserter -> EntryExitInstrumenter
The pass was renamed in r318195.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318784
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Hans Wennborg [Tue, 21 Nov 2017 17:22:19 +0000 (17:22 +0000)]
EntryExitInstrumenter: support __cyg_profile_func_enter_bare
It works just like __cyg_profile_func_enter but takes no arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318783
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Oliver Stannard [Tue, 21 Nov 2017 16:20:25 +0000 (16:20 +0000)]
[ARM] Remove pre-UAL FLDM/FSTM aliases
These are pre-UAL syntax, and we don't support any other pre-UAL instructions,
with the exception of FLDMX/FSTMX, which don't have a UAL equivalent. Therefore
there's no reason to keep them or their AsmParser hacks around.
With the AsmParser hacks removed, the FLDMX and FSTMX instructions get the same
operand diagnostics as the UAL instructions.
Differential revision: https://reviews.llvm.org/D39196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318777
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Alina Sbirlea [Tue, 21 Nov 2017 15:45:46 +0000 (15:45 +0000)]
Add MemorySSA as loop dependency, disabled by default [NFC].
Summary:
First step in adding MemorySSA as dependency for loop pass manager.
Adding the dependency under a flag.
New pass manager: MSSA pointer in LoopStandardAnalysisResults can be null.
Legacy and new pass manager: Use cl::opt EnableMSSALoopDependency. Disabled by default.
Reviewers: sanjoy, davide, gberry
Subscribers: mehdi_amini, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D40274
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318772
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Oliver Stannard [Tue, 21 Nov 2017 15:34:15 +0000 (15:34 +0000)]
[ARM] Don't omit non-default predication code
This was causing the (invalid) predicated versions of the NEON VRINTX and
VRINTZ instructions to be accepted, with the condition code being ignored.
Also, there is no NEON VRINTR instruction, so that part of the check was not
necessary.
Differential revision: https://reviews.llvm.org/D39193
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318771
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Oliver Stannard [Tue, 21 Nov 2017 15:16:50 +0000 (15:16 +0000)]
[Asm] Improve "too few operands" errors
- We can still emit this error if the actual instruction has two or more
operands missing compared to the expected one.
- We should only emit this error once per instruction.
Differential revision: https://reviews.llvm.org/D36746
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318770
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Oliver Stannard [Tue, 21 Nov 2017 15:12:05 +0000 (15:12 +0000)]
[Asm] Finish matching once end of formal and actual lists reached (NFC)
This is NFC, as the matcher would continue looping up to the maximum
number of operands with no effect, but this should improve performance a
bit, and makes the debug trace clearer.
Differential revision: https://reviews.llvm.org/D36744
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318769
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Sander de Smalen [Tue, 21 Nov 2017 15:07:43 +0000 (15:07 +0000)]
Revert r318759 due to make check-all failure on Windows
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318768
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Oliver Stannard [Tue, 21 Nov 2017 15:06:01 +0000 (15:06 +0000)]
[ARM] Add diagnostics for SPR/DPR lists
Differential revision: https://reviews.llvm.org/D39195
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318766
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Alexey Bataev [Tue, 21 Nov 2017 14:49:13 +0000 (14:49 +0000)]
[InstCombine] Test for PR35354: unable to vectorize loop with std::max
on floats, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318764
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Sam Kolton [Tue, 21 Nov 2017 14:11:59 +0000 (14:11 +0000)]
[AMDGPU] SDWA: remove omod src operand for VOP2b instructions
Summary: VOP2b instructions (v_subbrev_u32, v_add_i32 ...) shouldn't support OMod operand in SDWA encoding
Reviewers: rampitec, dp
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye
Differential Revision: https://reviews.llvm.org/D40172
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318761
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Alex Bradbury [Tue, 21 Nov 2017 12:41:41 +0000 (12:41 +0000)]
[RISCV][NFC] Remove unnecessary {} around single statement if block
Almost too trivial to worry about, but it seems worth having consistency with
upcoming commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318760
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Sander de Smalen [Tue, 21 Nov 2017 12:26:06 +0000 (12:26 +0000)]
[TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.
This is because the code will only update the diagnostic if it is more specific than the previous diagnostic. However, when having validated operands and 'moved on' to a next operand (for some instruction/alias for which all previous operands are valid), if the diagnostic is InvalidOperand, than that should be set as the diagnostic, not the more specific message about a previous operand for some other instruction/alias candidate.
Reviewers: craig.topper, olista01, rengolin, stoklund
Reviewed By: olista01
Subscribers: javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D40011
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318759
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Simon Pilgrim [Tue, 21 Nov 2017 12:02:18 +0000 (12:02 +0000)]
[X86][XOP] Add missing scheduler classes to XOP instructions
All match equivalent basic classes (WritePHAdd, WriteFAdd etc.) according to both the AMD 15h SOG and Agner's tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318758
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Alex Bradbury [Tue, 21 Nov 2017 12:00:19 +0000 (12:00 +0000)]
[RISCV][NFC] Clean up RISCVDAGToDAGISel::Select
As pointed out in post-commit review of r318738, `return ReplaceNode(..)` when
both ReplaceNode and the current function return void is confusing. This patch
moves to using a more obvious early return, and moves to just using an if to
catch the one case we currently care about. A future patch that adds further
custom instruction selection can introduce a switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318757
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Martell Malone [Tue, 21 Nov 2017 11:30:20 +0000 (11:30 +0000)]
[ARM] Use SEH exceptions on thumbv7-windows
Reviewers: mstorsjo
Differential Revision: https://reviews.llvm.org/D40286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318756
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Simon Pilgrim [Tue, 21 Nov 2017 11:17:11 +0000 (11:17 +0000)]
[X86][LWP] Add missing LWP itinerary class to lwpins instructions
It's on all other LWP instruction but I missed it from lwpins, despite similar scheduling behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318751
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Eugene Leviant [Tue, 21 Nov 2017 11:01:28 +0000 (11:01 +0000)]
[MI scheduler] Fix VADD and VSUB in cortex-a57 model
This patch fixes instregex for interger vector add/sub instructions
Differential revision: https://reviews.llvm.org/D40254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318749
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Coby Tayree [Tue, 21 Nov 2017 10:32:42 +0000 (10:32 +0000)]
[x86][icelake]BITALG
vpopcnt{b,w}
Differential Revision: https://reviews.llvm.org/D40213
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318748
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Diana Picus [Tue, 21 Nov 2017 10:17:02 +0000 (10:17 +0000)]
[ARM GlobalISel] Add comment for r318398. NFC.
Mention the purpose of the BICri tests added by r318398, as requested in
post-commit review.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318747
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Coby Tayree [Tue, 21 Nov 2017 10:04:28 +0000 (10:04 +0000)]
[x86][icelake]VNNI
Introducing Vector Neural Network Instructions, consisting of:
vpdpbusd{s}
vpdpwssd{s}
Differential Revision: https://reviews.llvm.org/D40208
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318746
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Coby Tayree [Tue, 21 Nov 2017 09:48:44 +0000 (09:48 +0000)]
[x86][icelake]vbmi2
introducing vbmi2, consisting of
vpcompress{b,w}
vpexpand{b,w}
vpsh{l,r}d{w,d,q}
vpsh{l,r}dv{w,d,q}
Differential Revision: https://reviews.llvm.org/D40206
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318745
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NAKAMURA Takumi [Tue, 21 Nov 2017 09:41:01 +0000 (09:41 +0000)]
SLPVectorizer.cpp: Avoid std::stable_sort(properlyDominates()).
properlyDominates() shouldn't be used as sort key. It causes different output between stdlibc++ and libc++.
Instead, I introduced RPOT. In most cases, it works for CSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318743
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