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12 months agohw/vfio/pci-quirks: Sanitize capability pointer
Alex Williamson [Fri, 30 Jun 2023 22:36:08 +0000 (16:36 -0600)]
hw/vfio/pci-quirks: Sanitize capability pointer

Coverity reports a tained scalar when traversing the capabilities
chain (CID 1516589).  In practice I've never seen a device with a
chain so broken as to cause an issue, but it's also pretty easy to
sanitize.

Fixes: f6b30c1984f7 ("hw/vfio/pci-quirks: Support alternate offset for GPUDirect Cliques")
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Cédric Le Goater <clg@redhat.com>
12 months agoMerge tag 'pull-tcg-20230709' of https://gitlab.com/rth7680/qemu into staging
Richard Henderson [Sun, 9 Jul 2023 14:01:43 +0000 (15:01 +0100)]
Merge tag 'pull-tcg-20230709' of https://gitlab.com/rth7680/qemu into staging

crypto: Provide aes-round.h and host accel

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# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 09 Jul 2023 02:55:54 PM BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate]

* tag 'pull-tcg-20230709' of https://gitlab.com/rth7680/qemu: (37 commits)
  crypto: Unexport AES_*_rot, AES_TeN, AES_TdN
  crypto: Remove AES_imc
  crypto: Implement aesdec_IMC with AES_imc_rot
  crypto: Remove AES_shifts, AES_ishifts
  target/riscv: Use aesdec_ISB_ISR_IMC_AK
  target/riscv: Use aesenc_SB_SR_MC_AK
  target/riscv: Use aesdec_IMC
  target/riscv: Use aesdec_ISB_ISR_AK
  target/riscv: Use aesenc_SB_SR_AK
  target/arm: Use aesdec_IMC
  target/arm: Use aesenc_MC
  target/arm: Use aesdec_ISB_ISR_AK
  target/arm: Use aesenc_SB_SR_AK
  target/arm: Demultiplex AESE and AESMC
  target/i386: Use aesdec_ISB_ISR_IMC_AK
  target/i386: Use aesenc_SB_SR_MC_AK
  target/i386: Use aesdec_IMC
  target/i386: Use aesdec_ISB_ISR_AK
  target/i386: Use aesenc_SB_SR_AK
  target/ppc: Use aesdec_ISB_ISR_AK_IMC
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoMerge tag 'linux-user-fcntl64-pull-request' of https://github.com/hdeller/qemu-hppa...
Richard Henderson [Sun, 9 Jul 2023 14:01:02 +0000 (15:01 +0100)]
Merge tag 'linux-user-fcntl64-pull-request' of https://github.com/hdeller/qemu-hppa into staging

linux-user: Fix fcntl64() and accept4() for 32-bit targets

A set of 3 patches:
The first two patches fix fcntl64() and accept4().
the 3rd patch enhances the strace output for pread64/pwrite64().

This pull request does not includes Richard's mmap2 patch:
https://patchew.org/QEMU/20230630132159.376995-1-richard.henderson@linaro.org/20230630132159.376995-12-richard.henderson@linaro.org/

Changes:
v3:
- added r-b from Richard to patches #1 and #2
v2:
- rephrased commmit logs
- return O_LARGFILE for fcntl() syscall too
- dropped #ifdefs in accept4() patch
- Dropped my mmap2() patch (former patch #3)
- added r-b from Richard to 3rd patch

Helge

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# =hd4O
# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 08 Jul 2023 03:57:09 PM BST
# gpg:                using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown]
# gpg:                 aka "Helge Deller <deller@kernel.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 4544 8228 2CD9 10DB EF3D  25F8 3E5F 3D04 A7A2 4603
#      Subkey fingerprint: BCE9 123E 1AD2 9F07 C049  BBDE F712 B510 A23A 0F5F

* tag 'linux-user-fcntl64-pull-request' of https://github.com/hdeller/qemu-hppa:
  linux-user: Improve strace output of pread64() and pwrite64()
  linux-user: Fix accept4(SOCK_NONBLOCK) syscall
  linux-user: Fix fcntl() and fcntl64() to return O_LARGEFILE for 32-bit targets

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Unexport AES_*_rot, AES_TeN, AES_TdN
Richard Henderson [Sat, 3 Jun 2023 01:39:00 +0000 (01:39 +0000)]
crypto: Unexport AES_*_rot, AES_TeN, AES_TdN

These arrays are no longer used outside of aes.c.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Remove AES_imc
Richard Henderson [Sat, 3 Jun 2023 01:30:12 +0000 (01:30 +0000)]
crypto: Remove AES_imc

This array is no longer used.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Implement aesdec_IMC with AES_imc_rot
Richard Henderson [Sat, 3 Jun 2023 01:26:20 +0000 (01:26 +0000)]
crypto: Implement aesdec_IMC with AES_imc_rot

This method uses one uint32_t * 256 table instead of 4,
which means its data cache overhead is less.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Remove AES_shifts, AES_ishifts
Richard Henderson [Sat, 3 Jun 2023 01:14:22 +0000 (01:14 +0000)]
crypto: Remove AES_shifts, AES_ishifts

These arrays are no longer used, replaced by AES_SH_*, AES_ISH_*.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/riscv: Use aesdec_ISB_ISR_IMC_AK
Richard Henderson [Fri, 2 Jun 2023 22:31:24 +0000 (15:31 -0700)]
target/riscv: Use aesdec_ISB_ISR_IMC_AK

This implements the AES64DSM instruction.  This was the last use
of aes64_operation and its support macros, so remove them all.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/riscv: Use aesenc_SB_SR_MC_AK
Richard Henderson [Fri, 2 Jun 2023 21:14:04 +0000 (14:14 -0700)]
target/riscv: Use aesenc_SB_SR_MC_AK

This implements the AES64ESM instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/riscv: Use aesdec_IMC
Richard Henderson [Fri, 2 Jun 2023 09:29:40 +0000 (02:29 -0700)]
target/riscv: Use aesdec_IMC

This implements the AES64IM instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/riscv: Use aesdec_ISB_ISR_AK
Richard Henderson [Fri, 2 Jun 2023 08:33:15 +0000 (01:33 -0700)]
target/riscv: Use aesdec_ISB_ISR_AK

This implements the AES64DS instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/riscv: Use aesenc_SB_SR_AK
Richard Henderson [Fri, 2 Jun 2023 06:22:20 +0000 (23:22 -0700)]
target/riscv: Use aesenc_SB_SR_AK

This implements the AES64ES instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/arm: Use aesdec_IMC
Richard Henderson [Fri, 2 Jun 2023 09:07:44 +0000 (02:07 -0700)]
target/arm: Use aesdec_IMC

This implements the AESIMC instruction.  We have converted everything
to crypto/aes-round.h; crypto/aes.h is no longer needed.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/arm: Use aesenc_MC
Richard Henderson [Fri, 2 Jun 2023 08:52:09 +0000 (01:52 -0700)]
target/arm: Use aesenc_MC

This implements the AESMC instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/arm: Use aesdec_ISB_ISR_AK
Richard Henderson [Fri, 2 Jun 2023 08:15:31 +0000 (01:15 -0700)]
target/arm: Use aesdec_ISB_ISR_AK

This implements the AESD instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/arm: Use aesenc_SB_SR_AK
Richard Henderson [Fri, 2 Jun 2023 05:50:47 +0000 (22:50 -0700)]
target/arm: Use aesenc_SB_SR_AK

This implements the AESE instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agolinux-user: Improve strace output of pread64() and pwrite64()
Helge Deller [Sun, 12 Mar 2023 22:17:13 +0000 (23:17 +0100)]
linux-user: Improve strace output of pread64() and pwrite64()

Make the strace look nicer for those two syscalls.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12 months agolinux-user: Fix accept4(SOCK_NONBLOCK) syscall
Helge Deller [Sat, 8 Jul 2023 05:24:00 +0000 (07:24 +0200)]
linux-user: Fix accept4(SOCK_NONBLOCK) syscall

The Linux accept4() syscall allows two flags only: SOCK_NONBLOCK and
SOCK_CLOEXEC, and returns -EINVAL if any other bits have been set.

Change the qemu implementation accordingly, which means we can not use
the fcntl_flags_tbl[] translation table which allows too many other
values.

Beside the correction in behaviour, this actually fixes the accept4()
emulation for hppa, mips and alpha targets for which SOCK_NONBLOCK is
different than TARGET_SOCK_NONBLOCK (aka O_NONBLOCK).

The fix can be verified with the testcase of the debian lwt package,
which hangs forever in a read() syscall without this patch.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12 months agolinux-user: Fix fcntl() and fcntl64() to return O_LARGEFILE for 32-bit targets
Helge Deller [Sat, 8 Jul 2023 05:00:25 +0000 (07:00 +0200)]
linux-user: Fix fcntl() and fcntl64() to return O_LARGEFILE for 32-bit targets

When running a 32-bit guest on a 64-bit host, fcntl[64](F_GETFL) should
return with the TARGET_O_LARGEFILE flag set, because all 64-bit hosts
support large files unconditionally.

But on 64-bit hosts, O_LARGEFILE has the value 0, so the flag
translation can't be done with the fcntl_flags_tbl[]. Instead add the
TARGET_O_LARGEFILE flag afterwards.

Note that for 64-bit guests the compiler will optimize away this code,
since TARGET_O_LARGEFILE is zero.

Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/arm: Demultiplex AESE and AESMC
Richard Henderson [Fri, 2 Jun 2023 05:42:43 +0000 (22:42 -0700)]
target/arm: Demultiplex AESE and AESMC

Split these helpers so that we are not passing 'decrypt'
within the simd descriptor.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/i386: Use aesdec_ISB_ISR_IMC_AK
Richard Henderson [Fri, 2 Jun 2023 22:29:28 +0000 (15:29 -0700)]
target/i386: Use aesdec_ISB_ISR_IMC_AK

This implements the AESDEC instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/i386: Use aesenc_SB_SR_MC_AK
Richard Henderson [Fri, 2 Jun 2023 21:09:00 +0000 (14:09 -0700)]
target/i386: Use aesenc_SB_SR_MC_AK

This implements the AESENC instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/i386: Use aesdec_IMC
Richard Henderson [Fri, 2 Jun 2023 09:05:37 +0000 (02:05 -0700)]
target/i386: Use aesdec_IMC

This implements the AESIMC instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/i386: Use aesdec_ISB_ISR_AK
Richard Henderson [Fri, 2 Jun 2023 08:12:36 +0000 (01:12 -0700)]
target/i386: Use aesdec_ISB_ISR_AK

This implements the AESDECLAST instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/i386: Use aesenc_SB_SR_AK
Richard Henderson [Fri, 2 Jun 2023 05:20:12 +0000 (22:20 -0700)]
target/i386: Use aesenc_SB_SR_AK

This implements the AESENCLAST instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/ppc: Use aesdec_ISB_ISR_AK_IMC
Richard Henderson [Fri, 2 Jun 2023 22:42:06 +0000 (15:42 -0700)]
target/ppc: Use aesdec_ISB_ISR_AK_IMC

This implements the VNCIPHER instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/ppc: Use aesenc_SB_SR_MC_AK
Richard Henderson [Fri, 2 Jun 2023 21:28:15 +0000 (14:28 -0700)]
target/ppc: Use aesenc_SB_SR_MC_AK

This implements the VCIPHER instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/ppc: Use aesdec_ISB_ISR_AK
Richard Henderson [Fri, 2 Jun 2023 22:43:42 +0000 (15:43 -0700)]
target/ppc: Use aesdec_ISB_ISR_AK

This implements the VNCIPHERLAST instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/ppc: Use aesenc_SB_SR_AK
Richard Henderson [Fri, 2 Jun 2023 06:04:48 +0000 (23:04 -0700)]
target/ppc: Use aesenc_SB_SR_AK

This implements the VCIPHERLAST instruction.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agohost/include/ppc: Implement aes-round.h
Richard Henderson [Mon, 5 Jun 2023 18:57:55 +0000 (21:57 +0300)]
host/include/ppc: Implement aes-round.h

Detect CRYPTO in cpuinfo; implement the accel hooks.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agohost/include/aarch64: Implement aes-round.h
Richard Henderson [Fri, 2 Jun 2023 07:43:40 +0000 (07:43 +0000)]
host/include/aarch64: Implement aes-round.h

Detect AES in cpuinfo; implement the accel hooks.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agohost/include/i386: Implement aes-round.h
Richard Henderson [Fri, 2 Jun 2023 06:58:52 +0000 (23:58 -0700)]
host/include/i386: Implement aes-round.h

Detect AES in cpuinfo; implement the accel hooks.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Add aesdec_ISB_ISR_AK_IMC
Richard Henderson [Fri, 2 Jun 2023 22:40:04 +0000 (15:40 -0700)]
crypto: Add aesdec_ISB_ISR_AK_IMC

Add a primitive for InvSubBytes + InvShiftRows +
AddRoundKey + InvMixColumns.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Add aesdec_ISB_ISR_IMC_AK
Richard Henderson [Fri, 2 Jun 2023 22:23:18 +0000 (15:23 -0700)]
crypto: Add aesdec_ISB_ISR_IMC_AK

Add a primitive for InvSubBytes + InvShiftRows +
InvMixColumns + AddRoundKey.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Add aesenc_SB_SR_MC_AK
Richard Henderson [Fri, 2 Jun 2023 10:54:39 +0000 (03:54 -0700)]
crypto: Add aesenc_SB_SR_MC_AK

Add a primitive for SubBytes + ShiftRows + MixColumns + AddRoundKey.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Add aesdec_IMC
Richard Henderson [Fri, 2 Jun 2023 09:01:23 +0000 (02:01 -0700)]
crypto: Add aesdec_IMC

Add a primitive for InvMixColumns.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Add aesenc_MC
Richard Henderson [Fri, 2 Jun 2023 08:49:21 +0000 (01:49 -0700)]
crypto: Add aesenc_MC

Add a primitive for MixColumns.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Add aesdec_ISB_ISR_AK
Richard Henderson [Fri, 2 Jun 2023 07:57:02 +0000 (00:57 -0700)]
crypto: Add aesdec_ISB_ISR_AK

Add a primitive for InvSubBytes + InvShiftRows + AddRoundKey.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto: Add aesenc_SB_SR_AK
Richard Henderson [Fri, 2 Jun 2023 04:57:10 +0000 (21:57 -0700)]
crypto: Add aesenc_SB_SR_AK

Start adding infrastructure for accelerating guest AES.
Begin with a SubBytes + ShiftRows + AddRoundKey primitive.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agocrypto/aes: Add AES_SH, AES_ISH macros
Richard Henderson [Thu, 1 Jun 2023 23:05:29 +0000 (16:05 -0700)]
crypto/aes: Add AES_SH, AES_ISH macros

These macros will constant fold and avoid the indirection through
memory when fully unrolling some new primitives.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/arm: Move aesmc and aesimc tables to crypto/aes.c
Richard Henderson [Thu, 1 Jun 2023 22:46:26 +0000 (15:46 -0700)]
target/arm: Move aesmc and aesimc tables to crypto/aes.c

We do not currently have a table in crypto/ for just MixColumns.
Move both tables for consistency.

Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotests/multiarch: Add test-aes
Richard Henderson [Thu, 1 Jun 2023 18:28:17 +0000 (11:28 -0700)]
tests/multiarch: Add test-aes

Use a shared driver and backends for i386, aarch64, ppc64, riscv64.

Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoutil: Add cpuinfo-ppc.c
Richard Henderson [Mon, 5 Jun 2023 15:29:04 +0000 (18:29 +0300)]
util: Add cpuinfo-ppc.c

Move the code from tcg/.  Fix a bug in that PPC_FEATURE2_ARCH_3_10
is actually spelled PPC_FEATURE2_ARCH_3_1.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoMerge tag 'trivial-patches-20230708' of https://gitlab.com/mjt0k/qemu into staging
Richard Henderson [Sat, 8 Jul 2023 06:24:30 +0000 (07:24 +0100)]
Merge tag 'trivial-patches-20230708' of https://gitlab.com/mjt0k/qemu into staging

qemu trivial patches for 2023-07-08

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# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [undefined]
# gpg:                 aka "Michael Tokarev <mjt@debian.org>" [undefined]
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* tag 'trivial-patches-20230708' of https://gitlab.com/mjt0k/qemu:
  hw/arm/virt-acpi-build.c: Add missing header
  migration: unexport migrate_fd_error()
  migration: factor out "resume_requested" in qmp_migrate()
  qemu-options.hx: Fix indentation of some option descriptions
  vdpa: Sort vdpa_feature_bits array alphabetically
  vdpa: Delete duplicated VIRTIO_NET_F_RSS in vdpa_feature_bits
  hw: Simplify calls to pci_nic_init_nofail()
  trivial: man page: document display::gtk::zoom-to-fit
  target/avr: Fix handling of interrupts above 33.
  hw/riscv/virt.c: fix typo in 'aia' description

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agohw/arm/virt-acpi-build.c: Add missing header
Peng Liang [Thu, 6 Jul 2023 17:06:10 +0000 (20:06 +0300)]
hw/arm/virt-acpi-build.c: Add missing header

virt-acpi-build.c uses warn_report. However, it doesn't include
qemu/error-report.h directly, it include qemu/error-report.h via trace.h
if we enable log trace backend. But if we disable the log trace backend
(e.g., --enable-trace-backends=nop), then virt-acpi-build.c will not
include qemu/error-report.h any more and it will lead to build errors.
Include qemu/error-report.h directly in virt-acpi-build.c to avoid the
errors.

Fixes: 451b157041 ("acpi: Align the size to 128k")
Signed-off-by: Peng Liang <tcx4c70@gmail.com>
Reviewed-by: Ani Sinha <anisinha@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(mjt: move the #include higher as suggested by Ani Sinha)

12 months agomigration: unexport migrate_fd_error()
Laszlo Ersek [Thu, 6 Jul 2023 10:29:37 +0000 (12:29 +0200)]
migration: unexport migrate_fd_error()

The only migrate_fd_error() call sites are in "migration/migration.c",
which is also where we define migrate_fd_error(). Make the function
static, and remove its declaration from "migration/migration.h".

Cc: Juan Quintela <quintela@redhat.com> (maintainer:Migration)
Cc: Leonardo Bras <leobras@redhat.com> (reviewer:Migration)
Cc: Peter Xu <peterx@redhat.com> (reviewer:Migration)
Cc: qemu-trivial@nongnu.org
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2018404
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12 months agomigration: factor out "resume_requested" in qmp_migrate()
Laszlo Ersek [Thu, 6 Jul 2023 10:29:36 +0000 (12:29 +0200)]
migration: factor out "resume_requested" in qmp_migrate()

It cuts back on those awkward, duplicated !(has_resume && resume)
expressions.

Cc: Juan Quintela <quintela@redhat.com> (maintainer:Migration)
Cc: Leonardo Bras <leobras@redhat.com> (reviewer:Migration)
Cc: Peter Xu <peterx@redhat.com> (reviewer:Migration)
Cc: qemu-trivial@nongnu.org
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=2018404
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12 months agoqemu-options.hx: Fix indentation of some option descriptions
Thomas Huth [Mon, 3 Jul 2023 07:56:46 +0000 (09:56 +0200)]
qemu-options.hx: Fix indentation of some option descriptions

The description of the options starts at column 16, so fix
this in some runaway lines for a more uniform output.

While we're at it, replace the capital "NOTE" with "Note"
since this seems to be the more common capitalization in
qemu-options.hx.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12 months agovdpa: Sort vdpa_feature_bits array alphabetically
Hawkins Jiawei [Fri, 30 Jun 2023 13:21:48 +0000 (21:21 +0800)]
vdpa: Sort vdpa_feature_bits array alphabetically

This patch sorts the vdpa_feature_bits array
alphabetically in ascending order to avoid future duplicates.

Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12 months agovdpa: Delete duplicated VIRTIO_NET_F_RSS in vdpa_feature_bits
Hawkins Jiawei [Fri, 30 Jun 2023 13:21:47 +0000 (21:21 +0800)]
vdpa: Delete duplicated VIRTIO_NET_F_RSS in vdpa_feature_bits

This entry was duplicated on referenced commit. Removing it.

Fixes: 402378407dbd ("vhost-vdpa: multiqueue support")
Signed-off-by: Hawkins Jiawei <yin31149@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12 months agohw: Simplify calls to pci_nic_init_nofail()
Thomas Huth [Thu, 29 Jun 2023 12:54:49 +0000 (14:54 +0200)]
hw: Simplify calls to pci_nic_init_nofail()

pci_nic_init_nofail() calls qemu_find_nic_model(), and this function
sets nd->model = g_strdup(default_model) if it has not been initialized
yet. So we don't have to set nd->model to the default_nic in the
calling sites.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12 months agotrivial: man page: document display::gtk::zoom-to-fit
Jan Kratochvil [Wed, 28 Jun 2023 10:23:36 +0000 (18:23 +0800)]
trivial: man page: document display::gtk::zoom-to-fit

Document display::gtk::zoom-to-fit.

info from: https://superuser.com/questions/1752209/qemu-zoom-to-fit-shortcut-or-cli-switch

Signed-off-by: Jan Kratochvil <jan@jankratochvil.net>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12 months agotarget/avr: Fix handling of interrupts above 33.
Lucas Dietrich [Wed, 14 Jun 2023 14:07:49 +0000 (16:07 +0200)]
target/avr: Fix handling of interrupts above 33.

This commit addresses a bug in the AVR interrupt handling code.
The modification involves replacing the usage of the ctz32 function
with ctz64 to ensure proper handling of interrupts above 33 in the AVR
target.

Previously, timers 3, 4, and 5 interrupts were not functioning correctly
because most of their interrupt vectors are numbered above 33.

Signed-off-by: Lucas Dietrich <ld.adecy@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
(Mjt: updated subject line to have subsytem prefix)

12 months agohw/riscv/virt.c: fix typo in 'aia' description
Daniel Henrique Barboza [Thu, 15 Jun 2023 09:21:48 +0000 (06:21 -0300)]
hw/riscv/virt.c: fix typo in 'aia' description

Cc: qemu-trivial@nongnu.org
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12 months agoMerge tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu into staging
Richard Henderson [Fri, 7 Jul 2023 21:23:17 +0000 (22:23 +0100)]
Merge tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2023-07-07:

In this last queue for 8.1 we have a lot of fixes and improvements all
around: SMT support for powerNV, XIVE fixes, PPC440 cleanups, exception
handling cleanups and kvm_pph.h cleanups just to name a few.

Thanks everyone in the qemu-ppc community for all the contributions for
the next QEMU 8.1 release.

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* tag 'pull-ppc-20230707-1' of https://gitlab.com/danielhb/qemu: (59 commits)
  ppc/pnv: Add QME region for P10
  target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h'
  target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c
  target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h
  target/ppc: Move CPU QOM definitions to cpu-qom.h
  target/ppc: Reorder #ifdef'ry in kvm_ppc.h
  target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'
  target/ppc: Machine check on invalid real address access on POWER9/10
  tests/qtest: Add xscom tests for powernv10 machine
  ppc/pnv: Set P10 core xscom region size to match hardware
  ppc/pnv: Log all unimp warnings with similar message
  ppc440_pcix: Rename QOM type define abd move it to common header
  ppc4xx_pci: Add define for ppc4xx-host-bridge type name
  ppc4xx_pci: Rename QOM type name define
  ppc440_pcix: Stop using system io region for PCI bus
  ppc440_pcix: Don't use iomem for regs
  ppc/sam460ex: Remove address_space_mem local variable
  ppc440: Remove ppc460ex_pcie_init legacy init function
  ppc440: Add busnum property to PCIe controller model
  ppc440: Stop using system io region for PCIe buses
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoMerge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
Richard Henderson [Fri, 7 Jul 2023 19:23:01 +0000 (20:23 +0100)]
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* Granite Rapids CPU model
* Miscellaneous bugfixes

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# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
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# gpg: WARNING: This key is not certified with a trusted signature!
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
  target/i386: Add new CPU model GraniteRapids
  target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model
  target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
  target/i386: Allow MCDT_NO if host supports
  target/i386: Add support for MCDT_NO in CPUID enumeration
  target/i386: Adjust feature level according to FEAT_7_1_EDX
  qemu_cleanup: begin drained section after vm_shutdown()
  meson.build: Remove the logic to link C code with the C++ linker
  python: bump minimum requirements so they are compatible with 3.12

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/i386: Add new CPU model GraniteRapids
Tao Su [Thu, 6 Jul 2023 05:49:49 +0000 (13:49 +0800)]
target/i386: Add new CPU model GraniteRapids

The GraniteRapids CPU model mainly adds the following new features
based on SapphireRapids:
- PREFETCHITI CPUID.(EAX=7,ECX=1):EDX[bit 14]
- AMX-FP16 CPUID.(EAX=7,ECX=1):EAX[bit 21]

And adds the following security fix for corresponding vulnerabilities:
- MCDT_NO CPUID.(EAX=7,ECX=2):EDX[bit 5]
- SBDR_SSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 13]
- FBSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 14]
- PSDP_NO MSR_IA32_ARCH_CAPABILITIES[bit 15]
- PBRSB_NO MSR_IA32_ARCH_CAPABILITIES[bit 24]

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Tested-by: Xuelian Guo <xuelian.guo@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20230706054949.66556-7-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agotarget/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU...
Lei Wang [Thu, 6 Jul 2023 05:49:48 +0000 (13:49 +0800)]
target/i386: Add few security fix bits in ARCH_CAPABILITIES into SapphireRapids CPU model

SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES
enabled, which are related to some security fixes.

Add version 2 of SapphireRapids CPU model with those bits enabled also.

Signed-off-by: Lei Wang <lei4.wang@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Message-ID: <20230706054949.66556-6-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agotarget/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES
Tao Su [Thu, 6 Jul 2023 05:49:47 +0000 (13:49 +0800)]
target/i386: Add new bit definitions of MSR_IA32_ARCH_CAPABILITIES

Currently, bit 13, 14, 15 and 24 of MSR_IA32_ARCH_CAPABILITIES are
disclosed for fixing security issues, so add those bit definitions.

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-ID: <20230706054949.66556-5-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agotarget/i386: Allow MCDT_NO if host supports
Tao Su [Thu, 6 Jul 2023 05:49:46 +0000 (13:49 +0800)]
target/i386: Allow MCDT_NO if host supports

MCDT_NO bit indicates HW contains the security fix and doesn't need to
be mitigated to avoid data-dependent behaviour for certain instructions.
It needs no hypervisor support. Treat it as supported regardless of what
KVM reports.

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20230706054949.66556-4-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agotarget/i386: Add support for MCDT_NO in CPUID enumeration
Tao Su [Thu, 6 Jul 2023 05:49:45 +0000 (13:49 +0800)]
target/i386: Add support for MCDT_NO in CPUID enumeration

CPUID.(EAX=7,ECX=2):EDX[bit 5] enumerates MCDT_NO. Processors enumerate
this bit as 1 do not exhibit MXCSR Configuration Dependent Timing (MCDT)
behavior and do not need to be mitigated to avoid data-dependent behavior
for certain instructions.

Since MCDT_NO is in a new sub-leaf, add a new CPUID feature word
FEAT_7_2_EDX. Also update cpuid_level_func7 by FEAT_7_2_EDX.

Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20230706054949.66556-3-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agotarget/i386: Adjust feature level according to FEAT_7_1_EDX
Tao Su [Thu, 6 Jul 2023 05:49:44 +0000 (13:49 +0800)]
target/i386: Adjust feature level according to FEAT_7_1_EDX

If FEAT_7_1_EAX is 0 and FEAT_7_1_EDX is non-zero, as is the case
with a Granite Rapids host and
'-cpu host,-avx-vnni,-avx512-bf16,-fzrm,-fsrs,-fsrc,-amx-fp16', we can't
get CPUID_7_1 leaf even though CPUID_7_1_EDX has non-zero value.

Update cpuid_level_func7 according to CPUID_7_1_EDX, otherwise
guest may report wrong maximum number sub-leaves in leaf 07H.

Fixes: eaaa197d5b11 ("target/i386: Add support for AVX-VNNI-INT8 in CPUID enumeration")
Cc: qemu-stable@nongnu.org
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Message-ID: <20230706054949.66556-2-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agoqemu_cleanup: begin drained section after vm_shutdown()
Fiona Ebner [Thu, 6 Jul 2023 13:14:18 +0000 (15:14 +0200)]
qemu_cleanup: begin drained section after vm_shutdown()

in order to avoid requests being stuck in a BlockBackend's request
queue during cleanup. Having such requests can lead to a deadlock [0]
with a virtio-scsi-pci device using iothread that's busy with IO when
initiating a shutdown with QMP 'quit'.

There is a race where such a queued request can continue sometime
(maybe after bdrv_child_free()?) during bdrv_root_unref_child() [1].
The completion will hold the AioContext lock and wait for the BQL
during SCSI completion, but the main thread will hold the BQL and
wait for the AioContext as part of bdrv_root_unref_child(), leading to
the deadlock [0].

[0]:

> Thread 3 (Thread 0x7f3bbd87b700 (LWP 135952) "qemu-system-x86"):
> #0  __lll_lock_wait (futex=futex@entry=0x564183365f00 <qemu_global_mutex>, private=0) at lowlevellock.c:52
> #1  0x00007f3bc1c0d843 in __GI___pthread_mutex_lock (mutex=0x564183365f00 <qemu_global_mutex>) at ../nptl/pthread_mutex_lock.c:80
> #2  0x0000564182939f2e in qemu_mutex_lock_impl (mutex=0x564183365f00 <qemu_global_mutex>, file=0x564182b7f774 "../softmmu/physmem.c", line=2593) at ../util/qemu-thread-posix.c:94
> #3  0x000056418247cc2a in qemu_mutex_lock_iothread_impl (file=0x564182b7f774 "../softmmu/physmem.c", line=2593) at ../softmmu/cpus.c:504
> #4  0x00005641826d5325 in prepare_mmio_access (mr=0x5641856148a0) at ../softmmu/physmem.c:2593
> #5  0x00005641826d6fe7 in address_space_stl_internal (as=0x56418679b310, addr=4276113408, val=16418, attrs=..., result=0x0, endian=DEVICE_LITTLE_ENDIAN) at /home/febner/repos/qemu/memory_ldst.c.inc:318
> #6  0x00005641826d7154 in address_space_stl_le (as=0x56418679b310, addr=4276113408, val=16418, attrs=..., result=0x0) at /home/febner/repos/qemu/memory_ldst.c.inc:357
> #7  0x0000564182374b07 in pci_msi_trigger (dev=0x56418679b0d0, msg=...) at ../hw/pci/pci.c:359
> #8  0x000056418237118b in msi_send_message (dev=0x56418679b0d0, msg=...) at ../hw/pci/msi.c:379
> #9  0x0000564182372c10 in msix_notify (dev=0x56418679b0d0, vector=8) at ../hw/pci/msix.c:542
> #10 0x000056418243719c in virtio_pci_notify (d=0x56418679b0d0, vector=8) at ../hw/virtio/virtio-pci.c:77
> #11 0x00005641826933b0 in virtio_notify_vector (vdev=0x5641867a34a0, vector=8) at ../hw/virtio/virtio.c:1985
> #12 0x00005641826948d6 in virtio_irq (vq=0x5641867ac078) at ../hw/virtio/virtio.c:2461
> #13 0x0000564182694978 in virtio_notify (vdev=0x5641867a34a0, vq=0x5641867ac078) at ../hw/virtio/virtio.c:2473
> #14 0x0000564182665b83 in virtio_scsi_complete_req (req=0x7f3bb000e5d0) at ../hw/scsi/virtio-scsi.c:115
> #15 0x00005641826670ce in virtio_scsi_complete_cmd_req (req=0x7f3bb000e5d0) at ../hw/scsi/virtio-scsi.c:641
> #16 0x000056418266736b in virtio_scsi_command_complete (r=0x7f3bb0010560, resid=0) at ../hw/scsi/virtio-scsi.c:712
> #17 0x000056418239aac6 in scsi_req_complete (req=0x7f3bb0010560, status=2) at ../hw/scsi/scsi-bus.c:1526
> #18 0x000056418239e090 in scsi_handle_rw_error (r=0x7f3bb0010560, ret=-123, acct_failed=false) at ../hw/scsi/scsi-disk.c:242
> #19 0x000056418239e13f in scsi_disk_req_check_error (r=0x7f3bb0010560, ret=-123, acct_failed=false) at ../hw/scsi/scsi-disk.c:265
> #20 0x000056418239e482 in scsi_dma_complete_noio (r=0x7f3bb0010560, ret=-123) at ../hw/scsi/scsi-disk.c:340
> #21 0x000056418239e5d9 in scsi_dma_complete (opaque=0x7f3bb0010560, ret=-123) at ../hw/scsi/scsi-disk.c:371
> #22 0x00005641824809ad in dma_complete (dbs=0x7f3bb000d9d0, ret=-123) at ../softmmu/dma-helpers.c:107
> #23 0x0000564182480a72 in dma_blk_cb (opaque=0x7f3bb000d9d0, ret=-123) at ../softmmu/dma-helpers.c:127
> #24 0x00005641827bf78a in blk_aio_complete (acb=0x7f3bb00021a0) at ../block/block-backend.c:1563
> #25 0x00005641827bfa5e in blk_aio_write_entry (opaque=0x7f3bb00021a0) at ../block/block-backend.c:1630
> #26 0x000056418295638a in coroutine_trampoline (i0=-1342102448, i1=32571) at ../util/coroutine-ucontext.c:177
> #27 0x00007f3bc0caed40 in ?? () from /lib/x86_64-linux-gnu/libc.so.6
> #28 0x00007f3bbd8757f0 in ?? ()
> #29 0x0000000000000000 in ?? ()
>
> Thread 1 (Thread 0x7f3bbe3e9280 (LWP 135944) "qemu-system-x86"):
> #0  __lll_lock_wait (futex=futex@entry=0x5641856f2a00, private=0) at lowlevellock.c:52
> #1  0x00007f3bc1c0d8d1 in __GI___pthread_mutex_lock (mutex=0x5641856f2a00) at ../nptl/pthread_mutex_lock.c:115
> #2  0x0000564182939f2e in qemu_mutex_lock_impl (mutex=0x5641856f2a00, file=0x564182c0e319 "../util/async.c", line=728) at ../util/qemu-thread-posix.c:94
> #3  0x000056418293a140 in qemu_rec_mutex_lock_impl (mutex=0x5641856f2a00, file=0x564182c0e319 "../util/async.c", line=728) at ../util/qemu-thread-posix.c:149
> #4  0x00005641829532d5 in aio_context_acquire (ctx=0x5641856f29a0) at ../util/async.c:728
> #5  0x000056418279d5df in bdrv_set_aio_context_commit (opaque=0x5641856e6e50) at ../block.c:7493
> #6  0x000056418294e288 in tran_commit (tran=0x56418630bfe0) at ../util/transactions.c:87
> #7  0x000056418279d880 in bdrv_try_change_aio_context (bs=0x5641856f7130, ctx=0x56418548f810, ignore_child=0x0, errp=0x0) at ../block.c:7626
> #8  0x0000564182793f39 in bdrv_root_unref_child (child=0x5641856f47d0) at ../block.c:3242
> #9  0x00005641827be137 in blk_remove_bs (blk=0x564185709880) at ../block/block-backend.c:914
> #10 0x00005641827bd689 in blk_remove_all_bs () at ../block/block-backend.c:583
> #11 0x0000564182798699 in bdrv_close_all () at ../block.c:5117
> #12 0x000056418248a5b2 in qemu_cleanup () at ../softmmu/runstate.c:821
> #13 0x0000564182738603 in qemu_default_main () at ../softmmu/main.c:38
> #14 0x0000564182738631 in main (argc=30, argv=0x7ffd675a8a48) at ../softmmu/main.c:48
>
> (gdb) p *((QemuMutex*)0x5641856f2a00)
> $1 = {lock = {__data = {__lock = 2, __count = 2, __owner = 135952, ...
> (gdb) p *((QemuMutex*)0x564183365f00)
> $2 = {lock = {__data = {__lock = 2, __count = 0, __owner = 135944, ...

[1]:

> Thread 1 "qemu-system-x86" hit Breakpoint 5, bdrv_drain_all_end () at ../block/io.c:551
> #0  bdrv_drain_all_end () at ../block/io.c:551
> #1  0x00005569810f0376 in bdrv_graph_wrlock (bs=0x0) at ../block/graph-lock.c:156
> #2  0x00005569810bd3e0 in bdrv_replace_child_noperm (child=0x556982e2d7d0, new_bs=0x0) at ../block.c:2897
> #3  0x00005569810bdef2 in bdrv_root_unref_child (child=0x556982e2d7d0) at ../block.c:3227
> #4  0x00005569810e8137 in blk_remove_bs (blk=0x556982e42880) at ../block/block-backend.c:914
> #5  0x00005569810e7689 in blk_remove_all_bs () at ../block/block-backend.c:583
> #6  0x00005569810c2699 in bdrv_close_all () at ../block.c:5117
> #7  0x0000556980db45b2 in qemu_cleanup () at ../softmmu/runstate.c:821
> #8  0x0000556981062603 in qemu_default_main () at ../softmmu/main.c:38
> #9  0x0000556981062631 in main (argc=30, argv=0x7ffd7a82a418) at ../softmmu/main.c:48
> [Switching to Thread 0x7fe76dab2700 (LWP 103649)]
>
> Thread 3 "qemu-system-x86" hit Breakpoint 4, blk_inc_in_flight (blk=0x556982e42880) at ../block/block-backend.c:1505
> #0  blk_inc_in_flight (blk=0x556982e42880) at ../block/block-backend.c:1505
> #1  0x00005569810e8f36 in blk_wait_while_drained (blk=0x556982e42880) at ../block/block-backend.c:1312
> #2  0x00005569810e9231 in blk_co_do_pwritev_part (blk=0x556982e42880, offset=3422961664, bytes=4096, qiov=0x556983028060, qiov_offset=0, flags=0) at ../block/block-backend.c:1402
> #3  0x00005569810e9a4b in blk_aio_write_entry (opaque=0x556982e2cfa0) at ../block/block-backend.c:1628
> #4  0x000055698128038a in coroutine_trampoline (i0=-2090057872, i1=21865) at ../util/coroutine-ucontext.c:177
> #5  0x00007fe770f50d40 in ?? () from /lib/x86_64-linux-gnu/libc.so.6
> #6  0x00007ffd7a829570 in ?? ()
> #7  0x0000000000000000 in ?? ()

Signed-off-by: Fiona Ebner <f.ebner@proxmox.com>
Message-ID: <20230706131418.423713-1-f.ebner@proxmox.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson.build: Remove the logic to link C code with the C++ linker
Thomas Huth [Thu, 6 Jul 2023 06:47:36 +0000 (08:47 +0200)]
meson.build: Remove the logic to link C code with the C++ linker

We are not mixing C++ with C code anymore, the only remaining
C++ code in qga/vss-win32/ is used for a plain C++ executable.
Thus we can remove the hacks for linking C code with the C++ linker
now to simplify meson.build a little bit, and also to avoid that
some C++ code sneaks in by accident again.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20230706064736.178962-1-thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agopython: bump minimum requirements so they are compatible with 3.12
Paolo Bonzini [Wed, 5 Jul 2023 10:40:46 +0000 (12:40 +0200)]
python: bump minimum requirements so they are compatible with 3.12

There are many Python 3.12 issues right now, but a particularly
problematic one when debugging them is that one cannot even use
minreqs.txt in a Python 3.12 virtual environment to test with
locked package versions.

Bump the mypy and wrapt versions to fix this, while remaining
within the realm of versions compatible with Python 3.7.

This requires a workaround for a mypy false positive

    qemu/qmp/qmp_tui.py:350: error: Non-overlapping equality check (left operand type: "Literal[Runstate.DISCONNECTING]", right operand type: "Literal[Runstate.IDLE]")  [comparison-overlap]

where mypy does not realize that self.disconnect() could change
the value of self.runstate.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agoppc/pnv: Add QME region for P10
Joel Stanley [Fri, 7 Jul 2023 07:12:13 +0000 (16:42 +0930)]
ppc/pnv: Add QME region for P10

The Quad Management Engine (QME) manages power related settings for its
quad. The xscom region is separate from the quad xscoms, therefore a new
region is added. The xscoms in a QME select a given core by selecting
the forth nibble.

Implement dummy reads for the stop state history (SSH) and special
wakeup (SPWU) registers. This quietens some sxcom errors when skiboot
boots on p10.

Power9 does not have a QME.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Message-ID: <20230707071213.9924-1-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoMerge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
Richard Henderson [Fri, 7 Jul 2023 09:23:46 +0000 (10:23 +0100)]
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging

# -----BEGIN PGP SIGNATURE-----
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# gpg: Signature made Fri 07 Jul 2023 09:37:02 AM BST
# gpg:                using RSA key EF04965B398D6211
# gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 215D 46F4 8246 689E C77F  3562 EF04 965B 398D 6211

* tag 'net-pull-request' of https://github.com/jasowang/qemu:
  igb: Remove obsolete workaround for Windows
  e1000e: Add ICR clearing by corresponding IMS bit
  net: socket: remove net_init_socket()
  net: socket: move fd type checking to its own function
  net: socket: prepare to cleanup net_init_socket()
  hw/net: ftgmac100: Drop the small packet check in the receive path
  hw/net: sunhme: Remove the logic of padding short frames in the receive path
  hw/net: sungem: Remove the logic of padding short frames in the receive path
  hw/net: rtl8139: Remove the logic of padding short frames in the receive path
  hw/net: pcnet: Remove the logic of padding short frames in the receive path
  hw/net: ne2000: Remove the logic of padding short frames in the receive path
  hw/net: i82596: Remove the logic of padding short frames in the receive path
  hw/net: vmxnet3: Remove the logic of padding short frames in the receive path
  hw/net: e1000: Remove the logic of padding short frames in the receive path
  virtio-net: correctly report maximum tx_queue_size value

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoigb: Remove obsolete workaround for Windows
Akihiko Odaki [Mon, 29 May 2023 02:37:04 +0000 (11:37 +0900)]
igb: Remove obsolete workaround for Windows

I confirmed it works with Windows even without this workaround. It is
likely to be a mistake so remove it.

Fixes: 3a977deebe ("Intrdocue igb device emulation")
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agoe1000e: Add ICR clearing by corresponding IMS bit
Akihiko Odaki [Fri, 2 Jun 2023 07:25:16 +0000 (16:25 +0900)]
e1000e: Add ICR clearing by corresponding IMS bit

The datasheet does not say what happens when interrupt was asserted
(ICR.INT_ASSERT=1) and auto mask is *not* active.
However, section of 13.3.27 the PCIe* GbE Controllers Open Source
Software Developer’s Manual, which were written for older devices,
namely 631xESB/632xESB, 82563EB/82564EB82571EB/82572EI &
82573E/82573V/82573L, does say:
> If IMS = 0b, then the ICR register is always clear-on-read. If IMS is
> not 0b, but some ICR bit is set where the corresponding IMS bit is not
> set, then a read does not clear the ICR register. For example, if
> IMS = 10101010b and ICR = 01010101b, then a read to the ICR register
> does not clear it. If IMS = 10101010b and ICR = 0101011b, then a read
> to the ICR register clears it entirely (ICR.INT_ASSERTED = 1b).

Linux does no longer activate auto mask since commit
0a8047ac68e50e4ccbadcfc6b6b070805b976885 and the real hardware clears
ICR even in such a case so we also should do so.

Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1707441
Signed-off-by: Andrew Melnychenko <andrew@daynix.com>
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agonet: socket: remove net_init_socket()
Laurent Vivier [Fri, 9 Jun 2023 07:27:48 +0000 (09:27 +0200)]
net: socket: remove net_init_socket()

Move the file descriptor type checking before doing anything with it.
If it's not usable, don't close it as it could be in use by another
part of QEMU, only fail and report an error.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agonet: socket: move fd type checking to its own function
Laurent Vivier [Fri, 9 Jun 2023 07:27:47 +0000 (09:27 +0200)]
net: socket: move fd type checking to its own function

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agonet: socket: prepare to cleanup net_init_socket()
Laurent Vivier [Fri, 9 Jun 2023 07:27:46 +0000 (09:27 +0200)]
net: socket: prepare to cleanup net_init_socket()

Use directly net_socket_fd_init_stream() and net_socket_fd_init_dgram()
when the socket type is already known.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: ftgmac100: Drop the small packet check in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:21 +0000 (09:53 +0800)]
hw/net: ftgmac100: Drop the small packet check in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, the small packet check logic in the receive
path is no longer needed.

Suggested-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: sunhme: Remove the logic of padding short frames in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:20 +0000 (09:53 +0800)]
hw/net: sunhme: Remove the logic of padding short frames in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: sungem: Remove the logic of padding short frames in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:19 +0000 (09:53 +0800)]
hw/net: sungem: Remove the logic of padding short frames in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: rtl8139: Remove the logic of padding short frames in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:18 +0000 (09:53 +0800)]
hw/net: rtl8139: Remove the logic of padding short frames in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: pcnet: Remove the logic of padding short frames in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:17 +0000 (09:53 +0800)]
hw/net: pcnet: Remove the logic of padding short frames in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: ne2000: Remove the logic of padding short frames in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:16 +0000 (09:53 +0800)]
hw/net: ne2000: Remove the logic of padding short frames in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: i82596: Remove the logic of padding short frames in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:15 +0000 (09:53 +0800)]
hw/net: i82596: Remove the logic of padding short frames in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: vmxnet3: Remove the logic of padding short frames in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:14 +0000 (09:53 +0800)]
hw/net: vmxnet3: Remove the logic of padding short frames in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.

This actually reverts commit 40a87c6c9b11ef9c14e0301f76abf0eb2582f08e.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agohw/net: e1000: Remove the logic of padding short frames in the receive path
Bin Meng [Sun, 25 Jun 2023 01:53:13 +0000 (09:53 +0800)]
hw/net: e1000: Remove the logic of padding short frames in the receive path

Now that we have implemented unified short frames padding in the
QEMU networking codes, remove the same logic in the NIC codes.

This actually reverts commit 78aeb23eded2d0b765bf9145c71f80025b568acd.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agovirtio-net: correctly report maximum tx_queue_size value
Laurent Vivier [Mon, 5 Jun 2023 14:21:25 +0000 (16:21 +0200)]
virtio-net: correctly report maximum tx_queue_size value

Maximum value for tx_queue_size depends on the backend type.
1024 for vDPA/vhost-user, 256 for all the others.

The value is returned by virtio_net_max_tx_queue_size() to set the
parameter:

    n->net_conf.tx_queue_size = MIN(virtio_net_max_tx_queue_size(n),
                                    n->net_conf.tx_queue_size);

But the parameter checking uses VIRTQUEUE_MAX_SIZE (1024).

So the parameter is silently ignored and ethtool reports a different
value than the one provided by the user.

   ... -netdev tap,... -device virtio-net,tx_queue_size=1024

    # ethtool -g enp0s2
    Ring parameters for enp0s2:
    Pre-set maximums:
    RX: 256
    RX Mini: n/a
    RX Jumbo: n/a
    TX: 256
    Current hardware settings:
    RX: 256
    RX Mini: n/a
    RX Jumbo: n/a
    TX: 256

   ... -netdev vhost-user,... -device virtio-net,tx_queue_size=2048

    Invalid tx_queue_size (= 2048), must be a power of 2 between 256 and 1024

With this patch the correct maximum value is checked and displayed.

For vDPA/vhost-user:

    Invalid tx_queue_size (= 2048), must be a power of 2 between 256 and 1024

For all the others:

    Invalid tx_queue_size (= 512), must be a power of 2 between 256 and 256

Fixes: 2eef278b9e63 ("virtio-net: fix tx queue size for !vhost-user")
Cc: mst@redhat.com
Cc: qemu-stable@nongnu.org
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
12 months agotarget/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h'
Philippe Mathieu-Daudé [Tue, 27 Jun 2023 11:51:24 +0000 (13:51 +0200)]
target/ppc: Remove pointless checks of CONFIG_USER_ONLY in 'kvm_ppc.h'

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-ID: <20230627115124.19632-7-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agotarget/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c
Philippe Mathieu-Daudé [Tue, 27 Jun 2023 11:51:23 +0000 (13:51 +0200)]
target/ppc: Restrict 'kvm_ppc.h' to sysemu in cpu_init.c

User emulation shouldn't need any of the KVM prototypes
declared in "kvm_ppc.h".

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-ID: <20230627115124.19632-6-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agotarget/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h
Philippe Mathieu-Daudé [Tue, 27 Jun 2023 11:51:22 +0000 (13:51 +0200)]
target/ppc: Define TYPE_HOST_POWERPC_CPU in cpu-qom.h

TYPE_HOST_POWERPC_CPU is used in various places of cpu_init.c,
in order to restrict "kvm_ppc.h" to sysemu, move this QOM-related
definition to cpu-qom.h.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-ID: <20230627115124.19632-5-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agotarget/ppc: Move CPU QOM definitions to cpu-qom.h
Philippe Mathieu-Daudé [Tue, 27 Jun 2023 11:51:21 +0000 (13:51 +0200)]
target/ppc: Move CPU QOM definitions to cpu-qom.h

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230627115124.19632-4-philmd@linaro.org>
[dhb: keep cpu_list define in target/ppc/cpu.h]
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agotarget/ppc: Reorder #ifdef'ry in kvm_ppc.h
Philippe Mathieu-Daudé [Tue, 27 Jun 2023 11:51:20 +0000 (13:51 +0200)]
target/ppc: Reorder #ifdef'ry in kvm_ppc.h

Keep a single if/else/endif block checking CONFIG_KVM.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230627115124.19632-3-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agotarget/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'
Philippe Mathieu-Daudé [Tue, 27 Jun 2023 11:51:19 +0000 (13:51 +0200)]
target/ppc: Have 'kvm_ppc.h' include 'sysemu/kvm.h'

"kvm_ppc.h" declares:

  int kvm_handle_nmi(PowerPCCPU *cpu, struct kvm_run *run);

'struct kvm_run' is declared in "sysemu/kvm.h", include it.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230627115124.19632-2-philmd@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agotarget/ppc: Machine check on invalid real address access on POWER9/10
Nicholas Piggin [Mon, 3 Jul 2023 12:03:01 +0000 (22:03 +1000)]
target/ppc: Machine check on invalid real address access on POWER9/10

ppc currently silently accepts invalid real address access. Catch
these and turn them into machine checks on POWER9/10 machines.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230703120301.45313-1-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agotests/qtest: Add xscom tests for powernv10 machine
Nicholas Piggin [Thu, 6 Jul 2023 05:39:23 +0000 (15:39 +1000)]
tests/qtest: Add xscom tests for powernv10 machine

Add basic chip and core xscom tests for powernv10 machine, equivalent
to tests for powernv8 and 9.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230706053923.115003-3-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc/pnv: Set P10 core xscom region size to match hardware
Nicholas Piggin [Thu, 6 Jul 2023 05:39:22 +0000 (15:39 +1000)]
ppc/pnv: Set P10 core xscom region size to match hardware

The P10 core xscom memory regions overlap because the size is wrong.
The P10 core+L2 xscom region size is allocated as 0x1000 (with some
unused ranges). "EC" is used as a closer match, as "EX" includes L3
which has a disjoint xscom range that would require a different
region if it were implemented.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-ID: <20230706053923.115003-2-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc/pnv: Log all unimp warnings with similar message
Joel Stanley [Thu, 6 Jul 2023 02:45:28 +0000 (12:15 +0930)]
ppc/pnv: Log all unimp warnings with similar message

Add the function name so there's an indication as to where the message
is coming from. Change all prints to use the offset instead of the
address.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230706024528.40065-1-joel@jms.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc440_pcix: Rename QOM type define abd move it to common header
BALATON Zoltan [Thu, 6 Jul 2023 11:16:45 +0000 (13:16 +0200)]
ppc440_pcix: Rename QOM type define abd move it to common header

Rename TYPE_PPC440_PCIX_HOST_BRIDGE to better match its string value,
move it to common header and use it also in sam460ex to replace hard
coded type name.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <1a1c3fe4b120f345d1005ad7ceca4500783691f7.1688641673.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc4xx_pci: Add define for ppc4xx-host-bridge type name
BALATON Zoltan [Thu, 6 Jul 2023 11:16:44 +0000 (13:16 +0200)]
ppc4xx_pci: Add define for ppc4xx-host-bridge type name

Add a QOM type name define for ppc4xx-host-bridge in the common header
and replace direct use of the string name with the constant.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <f6e2956b3a09ee481b970ef7873b374c846ba0a8.1688641673.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc4xx_pci: Rename QOM type name define
BALATON Zoltan [Thu, 6 Jul 2023 11:16:43 +0000 (13:16 +0200)]
ppc4xx_pci: Rename QOM type name define

Rename the TYPE_PPC4xx_PCI_HOST_BRIDGE define and its string value to
match each other and other similar types and to avoid confusion with
"ppc4xx-host-bridge" type defined in same file.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <c59c28ef440633dbd1de0bda0a93b7862ef91104.1688641673.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc440_pcix: Stop using system io region for PCI bus
BALATON Zoltan [Thu, 6 Jul 2023 11:16:42 +0000 (13:16 +0200)]
ppc440_pcix: Stop using system io region for PCI bus

Reduce the iomem region to 64K and use it for the PCI io space and map
it directly from the board without an intermediate alias that is not
really needed.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <f4ad9af42197a92dd1d0b56c21316dbdad240ee4.1688641673.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc440_pcix: Don't use iomem for regs
BALATON Zoltan [Wed, 5 Jul 2023 20:12:58 +0000 (22:12 +0200)]
ppc440_pcix: Don't use iomem for regs

The iomem memory region is better used for the PCI IO space but
currently used for registers. Stop using it for that to allow this to
be cleaned up in the next patch.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <3def68f200edd4540393d6b3b03baabe15d649f2.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc/sam460ex: Remove address_space_mem local variable
BALATON Zoltan [Wed, 5 Jul 2023 20:12:52 +0000 (22:12 +0200)]
ppc/sam460ex: Remove address_space_mem local variable

Some places already use  get_system_memory() directly so replace the
remaining uses and drop the local variable.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-ID: <d134d64f13258d1f157b445fedb1e86cf3abb606.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc440: Remove ppc460ex_pcie_init legacy init function
BALATON Zoltan [Wed, 5 Jul 2023 20:12:54 +0000 (22:12 +0200)]
ppc440: Remove ppc460ex_pcie_init legacy init function

After previous changes we can now remove the legacy init function and
move the device creation to board code.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <29aafeea9f1c871c739600a7b093c5456e8a1dc8.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
12 months agoppc440: Add busnum property to PCIe controller model
BALATON Zoltan [Wed, 5 Jul 2023 20:12:53 +0000 (22:12 +0200)]
ppc440: Add busnum property to PCIe controller model

Instead of guessing controller number from dcrn_base add a property so
the device does not need knowledge about where it is used.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <fdb84344025e00fadf74d0be95665fcb0ac1e039.1688586835.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>