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Likun Gao [Mon, 9 Jul 2018 18:47:04 +0000 (13:47 -0500)]
drm/amdgpu/vg20: Change the load type of vega20 to psp (v2)
Modified the vega20 load type to psp now that psp
support is implemented.
v2: squash in fixes history (Alex)
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Fri, 11 May 2018 06:54:50 +0000 (14:54 +0800)]
drm/amdgpu: Add psp 11.0 support for vega20. (v2)
Add psp 11.0 code for vega20 and enable it. PSP is the
security processor for the GPU. It handles firmware
loading and GPU resets among other things.
v2: whitespace fix, enable support, adjust reg includes (Alex)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 2 May 2018 07:45:54 +0000 (15:45 +0800)]
drm/amdgpu: enable vega20 powerplay support
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 21 May 2018 02:43:31 +0000 (10:43 +0800)]
drm/amd/powerplay: update vega20 clocks threshold settings on power state adjust
UVD, VCE and SOC clocks need to be taken into consideration. Also, the
thresholds need be updated correspondingly when stable power state is selected.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 21 May 2018 02:24:57 +0000 (10:24 +0800)]
drm/amd/powerplay: revise vega20 PPSMC_MSG_SetSoftMin/[Max]ByFreq settings
UVD, VCE and Socclk also need to be taken into consideration when
setting PPSMC_MSG_SetSoftMinByFreq and PPSMC_MSG_SetSoftMaxByFreq.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 21 May 2018 02:19:06 +0000 (10:19 +0800)]
drm/amd/powerplay: new interfaces for overdrive vega20 sclk and mclk
Add support for the new SMU firmware interface for clock adjustment.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 21 May 2018 02:16:41 +0000 (10:16 +0800)]
drm/amd/powerplay: initialize vega20 overdrive settings
The initialized overdrive settings are taken from vbios and SMU(
by PPSMC_MSG_TransferTableSmu2Dram).
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 11 May 2018 08:10:51 +0000 (16:10 +0800)]
drm/amd/powerplay: conv the vega20 pstate sclk/mclk into necessary 10KHz unit
Powerplay uses 10KHz units.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 9 May 2018 03:14:06 +0000 (11:14 +0800)]
drm/amd/powerplay: add vega20 pre_display_config_changed callback
fix possible handshake hang and video playback crash
Corner cases:
- Handshake between SMU and DCE causes hangs when CRTC is not
enabled
- System crash occurs when starting 4K playback with Movies and TV
in an SLS configuration
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 8 May 2018 10:23:16 +0000 (18:23 +0800)]
drm/amd/powerplay: export vega20 stable pstate clocks
Needed for querying the stable pstate clocks.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 8 May 2018 10:27:03 +0000 (18:27 +0800)]
drm/amd/powerplay: correct force clock level related settings for vega20 (v2)
1. The min/max level is determined by soft_min_level/soft_max_level.
2. Vega20 comes with pptable v3 which has no vdd related
table(vdd_dep_on_socclk, vdd_dep_on_mclk) support.
3. Vega20 does not support separate fan feature control(enable or
disable).
v2: squash in fixes:
- bug fix for force dpm level settings
- fix wrong data type
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 4 May 2018 07:20:15 +0000 (15:20 +0800)]
drm/amd/powerplay: init vega20 uvd/vce powergate status on dpm setup
This is essentially necessary when uvd/vce dpm is not enabled yet.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 6 Jul 2018 19:00:37 +0000 (14:00 -0500)]
drm/amd/powerplay: support workload profile query and setup for vega20
Support the power profile API.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Aug 2018 20:55:33 +0000 (15:55 -0500)]
drm/amd/powerplay: add the hw manager for vega20 (v3)
hwmgr is the interface for the driver to setup state
structures which are used by the smu for managing the
power state.
v2: squash in fixes:
- update set_watermarks_for_clocks_ranges to use common code
- drop unsupported apis
- correct MAX_REGULAR_DPM_NUMBER value
- multimonitor fixes
- add check for vbios pptable version
- revise dpm table setup
- init fclk dpm state
- Remove unused definition in vega20_hwmgr
- support power limit setup
- enable vega20 to honour DAL clock limits
- comment out dump_table debugging
v3: switch to SOC15 register access macros
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Fri, 11 May 2018 02:56:25 +0000 (10:56 +0800)]
drm/amd/powerplay: new interfaces for ActivityMonitor table with SMU
Vega20 has a new activity monitor table that is stored in memory. Add
API to get and set the new table.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 2 Aug 2018 20:52:41 +0000 (15:52 -0500)]
drm/amd/powerplay: add the smu manager for vega20 (v2)
The SMU manager handles the driver interaction with the SMU
which handles clock and voltage controls.
v2: switch to SOC15 register access macros
reserve space for ActivityMonitor table
enable SMU fw loading
Drop dead code from bringup
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Mar 2018 08:36:08 +0000 (16:36 +0800)]
drm/amd/powerplay: add vega20_pptable.h (v2)
v2: squash in table size fixes
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Mar 2018 08:21:51 +0000 (16:21 +0800)]
drm/amd/powerplay: add vega20_ppsmc.h (v2)
v2: update to latest.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Mar 2018 08:16:41 +0000 (16:16 +0800)]
drm/amd/powerplay: add smu11_driver_if.h (v4)
v2: cleanup
v3: fit the latest 40.6 smc fw
v4: update to latest.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 21 Mar 2018 06:10:21 +0000 (14:10 +0800)]
drm/amd/powerplay: add vega20_inc.h (v2)
v2: use thm 11.0.2 headers
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 2 May 2018 07:50:10 +0000 (15:50 +0800)]
drm/amdgpu: update atomfirmware.h
Add struct atom_smc_dpm_info_v4_3
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Fri, 23 Mar 2018 19:44:28 +0000 (14:44 -0500)]
drm/amdgpu: Add nbio 7.4 support for vega20 (v3)
Some register offset in nbio v7.4 are different with v7.0.
We need a seperate nbio_v7_4.c for vega20.
v2: fix doorbell range for sdma (Alex)
v3: squash in static fix (kbuild test robot)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 3 Apr 2018 20:49:56 +0000 (15:49 -0500)]
Revert "drm/amdgpu: Add nbio support for vega20 (v2)"
Revert this to add proper nbio 7.4 support.
This reverts commit
f5b2e1fa321eff20a9418ebd497d8a466f024a85.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Thu, 10 May 2018 13:23:58 +0000 (21:23 +0800)]
drm/amdgpu/include: Add mp 11.0 header files. (v2)
Add the system management controller v11.0 header files.
v2: cleanup
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Mon, 26 Mar 2018 07:29:48 +0000 (15:29 +0800)]
drm/amdgpu/include: add thm 11.0.2 headers
Headers for thermal controller.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Wed, 17 Jan 2018 11:42:33 +0000 (19:42 +0800)]
drm/amdgpu/include: Add sdma0/1 4.2 register headerfiles. (v3)
These are the System DMA register headers for vega20.
v2: cleanups (Alex)
v3: add missing licenses (Alex)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Feifei Xu [Wed, 17 Jan 2018 12:05:19 +0000 (20:05 +0800)]
drm/amdgpu/include: Add nbio 7.4 header files (v4)
v2: Cleanups (Alex)
v3: More updates (Alex)
v4: more cleanups (Alex)
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Rossi [Sun, 12 Aug 2018 19:43:03 +0000 (21:43 +0200)]
drm/radeon: enable ABGR and XBGR formats (v2)
Add support for DRM_FORMAT_{A,X}BGR8888 in atombios_crtc
Swapping of red and blue channels is implemented for radeon chipsets:
DCE2/R6xx and later - crossbar registers defined where needed and used
DCE1/R5xx - AVIVO_D1GRPH_SWAP_RB bit is used
(v2) Set AVIVO_D1GRPH_SWAP_RB bit in fb_format, using bitwise OR for DCE1 path
Use bitwise OR where required for big endian settings in fb_swap
Use existing code style CHIP_R600 condition, fix typo in R600 blue crossbar
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Rossi [Sun, 12 Aug 2018 19:43:02 +0000 (21:43 +0200)]
drm/amdgpu: enable ABGR and XBGR formats (v2)
Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled
(v2) Crossbar registers are defined and used to swap red and blue channels,
keeping the existing coding style in each of the dce modules.
After setting crossbar bits in fb_swap, use bitwise OR for big endian
where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Rossi [Sun, 12 Aug 2018 19:43:01 +0000 (21:43 +0200)]
drm/amd/display: enable ABGR and XBGR formats (v4)
SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 is supported in amd/display/dc/dc_hw_types.h
and the necessary crossbars register controls to swap red and blue channels
are already implemented in drm/amd/display/dc/dce/dce_mem_input.c
(v4) Logic to handle new formats is added only in amdgpu_dm module.
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Aug 2018 18:21:09 +0000 (13:21 -0500)]
drm/amdgpu/powerplay/vega10: enable AVFS control via ppfeaturemask
Allow the user to disable AFVS via ppfeaturemask for debugging.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Aug 2018 18:19:26 +0000 (13:19 -0500)]
drm/amdgpu/powerplay/smu7: enable AVFS control via ppfeaturemask
Allow the user to disable AFVS via ppfeaturemask for debugging.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Fri, 10 Aug 2018 18:09:43 +0000 (13:09 -0500)]
drm/amdgpu: add AVFS control to PP_FEATURE_MASK
Add a ppfeaturemask flag to disable AVFS control.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Thu, 19 Jul 2018 00:29:13 +0000 (20:29 -0400)]
drm/amd/display: dc 3.1.62
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Steven Chiu <Steven.Chiu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Leo (Sunpeng) Li [Wed, 1 Aug 2018 14:20:53 +0000 (10:20 -0400)]
drm/amd/display: Remove redundant non-zero and overflow check
[Why]
Unsigned int is guaranteed to be >= 0, and read_channel_reply checks for
overflows. read_channel_reply also returns -1 on error, which is what
dc_link_aux_transfer is expected to return on error.
[How]
Remove the if-statement. Return result of read_channel_reply directly.
Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Mikita Lipski <Mikita.Lipski@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Wed, 1 Aug 2018 00:14:26 +0000 (20:14 -0400)]
drm/amd/display: add retimer log for HWQ tuning use.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Tue, 17 Jul 2018 21:15:48 +0000 (17:15 -0400)]
drm/amd/display: fix dml handling of mono8/16 pixel formats
mono formats are treated exactly the same as equivallent bpp
444 formats. Dml validation however lacks 444 8 bit format
while dml perf param calculation lacks mono format support
This change makes them equivallent as far as the enum is concerned
to avoid having to update dml
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dmytro Laktyushkin [Mon, 30 Jul 2018 18:41:01 +0000 (14:41 -0400)]
drm/amd/display: Add dprefclk value to dce_dccg
This allows us to avoid any vbios bugs when initializing clocks
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gloria Li [Thu, 26 Jul 2018 15:32:14 +0000 (11:32 -0400)]
drm/amd/display: fix PIP bugs on Dal3
[Why]
There are outstanding bugs for PIP in Dal3:
-Crash when toggling PIP visibility
-Global Alpha is not working, Adjusting global alpha
doesn’t have an effect
-Cursor is not working with pip plane and pipe splits
-One flash occurs when cursor enters PIP plane from
top/bottom
-Crash when moving PIP plane off the screen
[How]
Resolve divide by 0 error
Implement global alpha
Program cursor on all pipes
Add dst rects' x and y offests into cursor position
Disable cursor when it is beyond bottom/top edge
Signed-off-by: Gloria Li <geling.li@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Thu, 19 Jul 2018 00:28:54 +0000 (20:28 -0400)]
drm/amd/display: dc 3.1.61
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Steven Chiu <Steven.Chiu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 9 Aug 2018 07:26:06 +0000 (15:26 +0800)]
drm/amdgpu: Cancel gfx off delay work when driver fini/suspend
there may be gfx off delay work pending when suspend/driver
unload, need to cancel them first.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 9 Aug 2018 19:24:08 +0000 (14:24 -0500)]
drm/amdgpu/powerplay: check vrefresh when when changing displays
Compare the current vrefresh in addition to the number of displays
when determining whether or not the smu needs updates when changing
modes. The SMU needs to be updated if the vbi timeout changes due
to a different refresh rate. Fixes flickering around mode changes
in some cases on polaris parts.
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:29:29 +0000 (16:29 -0400)]
drm/amdgpu: fix emit frame size and comments for jpeg
Fix vcn jpeg ring emit fence size in dword, and fix the naming in comments.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:26:28 +0000 (16:26 -0400)]
drm/amdgpu: add emit trap for vcn jpeg
Add emit trap command in jpeg emit fence call.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:25:42 +0000 (16:25 -0400)]
drm/amdgpu: enable system interrupt for jrbc
Enable system interrupt for jrbc during engine starting time.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:24:18 +0000 (16:24 -0400)]
drm/amdgpu: add system interrupt mask for jrbc
Add new mask for enabling system interrupt for jrbc.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 18 Jul 2018 20:13:29 +0000 (16:13 -0400)]
drm/amdgpu: add system interrupt register offset header
Add new register offset for enabling system interrupt.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Boyuan Zhang [Wed, 11 Jul 2018 18:40:18 +0000 (14:40 -0400)]
drm/amdgpu: add emit reg write reg wait for vcn jpeg
The emit_reg_write_reg_wait function was not assigned for vcn jpeg.
This patch adds it back.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 7 Aug 2018 21:30:50 +0000 (16:30 -0500)]
drm/amdgpu/pp: endian fixes for processpptables.c
Properly swap when reading from the vbios.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Tue, 7 Aug 2018 20:17:09 +0000 (15:17 -0500)]
drm/amdgpu/pp: endian fixes for process_pptables_v1_0.c
Properly swap when reading from the vbios.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 8 Aug 2018 11:07:11 +0000 (13:07 +0200)]
drm/scheduler: change entities rq even earlier
Looks like for correct debugging we need to know the scheduler even
earlier. So move picking a rq for an entity into job creation.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 7 Aug 2018 12:52:13 +0000 (14:52 +0200)]
drm/scheduler: fix last_scheduled handling
Make sure we access last_scheduled only after checking that there are no
more jobs on the entity.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Fri, 3 Aug 2018 11:07:36 +0000 (13:07 +0200)]
drm/scheduler: Remove entity->rq NULL check
That is superflous now.
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 6 Aug 2018 12:14:51 +0000 (20:14 +0800)]
drm/amdgpu: move missed gfxoff entry into amdgpu_gfx header
Move missed gfxoff entry to amdgpu_gfx.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 3 Aug 2018 11:06:02 +0000 (19:06 +0800)]
drm/amdgpu: move vm definitions into amdgpu_vm header
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 3 Aug 2018 10:59:25 +0000 (18:59 +0800)]
drm/amdgpu: move gmc macros into amdgpu_gmc header
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 9 Aug 2018 14:50:12 +0000 (09:50 -0500)]
drm/amdgpu: move display definitions into amdgpu_display header
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 3 Aug 2018 10:37:58 +0000 (18:37 +0800)]
drm/amdgpu: remove useless gds switch macro
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Fri, 3 Aug 2018 10:33:06 +0000 (18:33 +0800)]
drm/amdgpu: move ring macros into amdgpu_ring header
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jia-Ju Bai [Sat, 4 Aug 2018 00:01:02 +0000 (08:01 +0800)]
gpu: drm: radeon: radeon_test: Replace mdelay() with msleep()
radeon_test_ring_sync() and radeon_test_ring_sync2() are never
called in atomic context.
They call mdelay() to busily wait, which is not necessary.
mdelay() can be replaced with msleep().
This is found by a static analysis tool named DCNS written by myself.
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jia-Ju Bai [Sat, 4 Aug 2018 00:33:44 +0000 (08:33 +0800)]
gpu: drm: radeon: si: Replace mdelay() with msleep() in si_pcie_gen3_enable()
si_pcie_gen3_enable() is never called in atomic context.
It calls mdelay() to busily wait, which is not necessary.
mdelay() can be replaced with msleep().
This is found by a static analysis tool named DCNS written by myself
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jia-Ju Bai [Sat, 4 Aug 2018 00:25:35 +0000 (08:25 +0800)]
gpu: drm: radeon: cik: Replace mdelay() with msleep() in cik_pcie_gen3_enable()
cik_pcie_gen3_enable() is never called in atomic context.
It calls mdelay() to busily wait, which is not necessary.
mdelay() can be replaced with msleep().
This is found by a static analysis tool named DCNS written by myself.
Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Mon, 6 Aug 2018 10:46:41 +0000 (12:46 +0200)]
drm/scheduler: bind job earlier to scheduler
Update job earlier with the scheduler it is supposed to be scheduled on.
Otherwise we could incorrectly optimize dependencies when moving an
entity from one scheduler to another.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 1 Aug 2018 14:22:39 +0000 (16:22 +0200)]
drm/scheduler: fix setting the priorty for entities (v2)
Since we now deal with multiple rq we need to update all of them, not
just the current one.
v2: Trivial: Removed unused variable (Alex)
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 6 Aug 2018 11:45:04 +0000 (19:45 +0800)]
drm/amdgpu: Delay 100ms to enable gfx off feature
Original 500ms delay seems a bit large.
Change to 100 ms suggested by Christian.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vitaly Prosyak [Thu, 12 Jul 2018 19:26:47 +0000 (14:26 -0500)]
drm/amd/display: Add check for num of entries in gamma
This check avoids potential bugs related to gamma.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vitaly Prosyak [Wed, 18 Jul 2018 20:10:10 +0000 (15:10 -0500)]
drm/amd/display: Use DGAM ROM or RAM
[Why]
Optimize gamma programming
[How]
Use ROM for optimization when it is possible.
Use RAM only when it is necessary.
Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nikola Cornij [Thu, 19 Jul 2018 18:03:14 +0000 (14:03 -0400)]
drm/amd/display: Print DPP DTN log info only for enabled pipes
[why]
There is currently a dependency on the order in which tests are executed.
This is because the non-relevant state info is being printed, which results
in the output based on the state from the previous test.
[how]
Print DPP DTN log only if the pipe is enabled.
In addition to the affected per-submission DTN golden logs, included in this
change is also DTN golden log update for pre-submission tests.
The other DTN golden logs affected by this change will be updated upon
nightly test run (which will generate the updated DTN logs).
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Martin Tsai [Fri, 27 Jul 2018 07:39:47 +0000 (15:39 +0800)]
drm/amd/display: correct image viewport calculation
[why]
We didn't transfer the camera/video viewport coordinate
when doing rotation and mirror.
[how]
To correct the viewport coordinate in calculate_viewport().
Signed-off-by: Martin Tsai <Martin.Tsai@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mikita Lipski [Thu, 26 Jul 2018 20:27:48 +0000 (16:27 -0400)]
drm/amd/display: pass the right num of modes added
[why]
In case if edid is null or corrupted we need to manually add
a single failsafe mode (640x480). If zero modes returned
DRM adds a different failsafe mode that is not accepted by
DP 1.2 compliance test
[how]
Return the number of modes manually added
Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Mon, 13 Aug 2018 16:41:35 +0000 (11:41 -0500)]
drm/amdgpu: move gem definitions into amdgpu_gem header
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 2 Aug 2018 09:54:21 +0000 (17:54 +0800)]
drm/amdgpu: move psp macro into amdgpu_psp header
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 2 Aug 2018 09:47:15 +0000 (17:47 +0800)]
drm/amdgpu: move firmware definitions into amdgpu_ucode header
Demangle amdgpu.h.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 2 Aug 2018 09:23:33 +0000 (17:23 +0800)]
drm/amdgpu: move sdma definitions into amdgpu_sdma header
Demangle amdgpu.h.
Furthermore, SDMA is used for moving and clearing the data buffer, so the header
also need be included in ttm.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 2 Aug 2018 08:24:52 +0000 (16:24 +0800)]
drm/amdgpu: move ih definitions into amdgpu_ih header
Demangle amdgpu.h
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 2 Aug 2018 08:12:39 +0000 (16:12 +0800)]
drm/amdgpu: move gfx definitions into amdgpu_gfx header
Demangle amdgpu.h
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 27 Jul 2018 06:10:45 +0000 (14:10 +0800)]
drm/amd/pp: Delete duplicated interface in hwmgr_func
gfx off support in smu can be via powergate_gfx interface.
so remove the gfx_off_control interface.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 27 Jul 2018 09:00:02 +0000 (17:00 +0800)]
drm/amdgpu: Disable gfx off if VCN is busy
this patch is a workaround for the gpu hang
at video begin/end time if gfx off is enabled.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 27 Jul 2018 06:55:09 +0000 (14:55 +0800)]
drm/amdgpu: Ctrl gfx off via amdgpu_gfx_off_ctrl
use amdgpu_gfx_off_ctrl function so driver can arbitrate
whether the gfx ip can be power off or power on.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Fri, 27 Jul 2018 13:06:30 +0000 (21:06 +0800)]
drm/amdgpu: Put enable gfx off feature to a delay thread
delay to enable gfx off feature to avoid gfx on/off frequently
suggested by Alex and Evan.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Mon, 30 Jul 2018 08:59:09 +0000 (16:59 +0800)]
drm/amdgpu: Add amdgpu_gfx_off_ctrl function
v2:
1. drop the special handling for the hw IP
suggested by hawking and Christian.
2. refine the variable name suggested by Flora.
This funciton as the entry of gfx off feature.
we arbitrat gfx off feature enable/disable in this
function.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Tue, 21 Aug 2018 19:36:49 +0000 (14:36 -0500)]
drm/amd/display: Add support for toggling DFS bypass
[Why]
If the hardware supports DFS bypass it will always be enabled after
creation of the DCCG. DFS bypass should only be enabled when
the current stream consists of a single embedded panel and the
minimum display clock is below the DFS bypass threshold.
[How]
Add a function to the DCCG table that updates the DFS bypass state
when setting the bandwidth. If the DFS bypass state is changed, the
clock needs to be reprogrammed to reflect this before the DPREFCLK
is updated for audio endpoints. The existing display clock value
is used as the target display clock value when reprogramming since the
resulting change will be equal or larger to the current value.
These changes only specifically target dce110 but do offer a framework
for support on other applicable targets.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Tue, 24 Jul 2018 13:42:23 +0000 (09:42 -0400)]
drm/amd/display: Enable DFS bypass support in DC config
[Why]
We explicitly disable DFS bypass support when creating DC. Support
for this feature should now be in place so it can be left implicitly
enabled.
[How]
Remove the line that disables DFS bypass support.
Note: This option was actually reset to false anyway for most of
the hardware I've tested on making this particular line misleading
in the first place. This patch also fixes this issue.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nicholas Kazlauskas [Tue, 24 Jul 2018 17:19:49 +0000 (13:19 -0400)]
drm/amd/display: Set DFS bypass flags for dce110
[Why]
While there is support for using and quering DFS bypass clocks the
hardware is never notified to enter DFS bypass mode for dce110.
[How]
Add a flag that can be set when programming the display engine PLL
to enable DFS bypass mode. If this flag is set then the hardware is
notified to enter DFS bypass mode and the correct display engine clock
frequency can be acquired.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tony Cheng [Thu, 19 Jul 2018 00:28:12 +0000 (20:28 -0400)]
drm/amd/display: dal 3.1.60
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jun Lei [Mon, 16 Jul 2018 14:40:31 +0000 (10:40 -0400)]
drm/amd/display: Move PME to function pointer call semantics
[why]
Legacy IRI style is not linux friendly.
[how]
New function pointer call
semantics will be used for all future PPLIB/DAL interfaces, and also
some existing will be refactored. This change defines how the
new function pointer structures will look, as well as implements
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Charlene Liu [Mon, 16 Jul 2018 18:05:11 +0000 (14:05 -0400)]
drm/amd/display: pass compat_level to hubp
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 5 Jul 2018 11:22:50 +0000 (19:22 +0800)]
drm/amd/pp: Implement get_performance_level for legacy dgpu
display can get clock info through this function.
implement this function for vega10 and old asics.
from vega12, there is no power state management,
so need to add new interface to notify display
the clock info
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Tue, 31 Jul 2018 14:52:25 +0000 (10:52 -0400)]
drm/amdgpu: Add job pipe sync dependecy trace
It's useful to trace any dependency a job has on prevoius
jobs.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Andrey Grodzovsky [Tue, 31 Jul 2018 14:48:52 +0000 (10:48 -0400)]
drm/scheduler: Add job dependency trace.
During debug sessions I encountered a need to trace
back a job dependecy a few steps back to the first failing
job. This trace helpped me a lot.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nayan Deshmukh [Wed, 1 Aug 2018 08:20:02 +0000 (13:50 +0530)]
drm/scheduler: move idle entities to scheduler with less load v2
This is the first attempt to move entities between schedulers to
have dynamic load balancing. We just move entities with no jobs for
now as moving the ones with jobs will lead to other compilcations
like ensuring that the other scheduler does not remove a job from
the current entity while we are moving.
v2: remove unused variable and an unecessary check
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nayan Deshmukh [Wed, 1 Aug 2018 08:20:01 +0000 (13:50 +0530)]
drm/scheduler: add new function to get least loaded sched v2
The function selects the run queue from the rq_list with the
least load. The load is decided by the number of jobs in a
scheduler.
v2: avoid using atomic read twice consecutively, instead store
it locally
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nayan Deshmukh [Wed, 1 Aug 2018 08:20:00 +0000 (13:50 +0530)]
drm/scheduler: add counter for total jobs in scheduler
To keep track of the scheduler load.
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Nayan Deshmukh [Wed, 1 Aug 2018 08:19:59 +0000 (13:49 +0530)]
drm/scheduler: add a list of run queues to the entity
These are the potential run queues on which the jobs from this
entity can be scheduled. We will use this to do load balancing.
Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sun, 29 Jul 2018 10:53:02 +0000 (18:53 +0800)]
drm/amgpu/acp: Implement set_powergating_state for acp
so driver can powergate acp block after asic initialized
to save power.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Sun, 29 Jul 2018 10:44:06 +0000 (18:44 +0800)]
drm/amdgpu/acp: Powrgate acp via smu
Call smu to power gate/ungate acp instand of only
powr down acp tiles in acp block.
when smu power gate acp:
smu will turn off clock, power down acp tiles,check and
enter in ULV state.
when smu ungate acp:
smu will exit ulv, turn on clocks, power on acp tiles.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Vijendar Mukunda [Sun, 29 Jul 2018 11:08:32 +0000 (19:08 +0800)]
drm/amd/amdgpu: Enabling Power Gating for Stoney platform
Removed condition checks to skip the power gating feature for
stoney platform.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Vijendar Mukunda <vijendar.mukunda@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 19 Jul 2018 16:48:36 +0000 (11:48 -0500)]
drm/amdgpu: Power down acp if board uses AZ (v2)
if board uses AZ rather than ACP, we power down acp
through smu to save power.
v2: handle S3/S4 and hw_fini (Alex)
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 19 Jul 2018 05:49:07 +0000 (13:49 +0800)]
drm/amd/pp: Add ACP PG support in SMU
when ACP block not enabled, we power off
acp block to save power.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rex Zhu [Thu, 16 Aug 2018 03:36:38 +0000 (11:36 +0800)]
drm/amd/display: Fix bug use wrong pp interface
Used wrong pp interface, the original interface is
exposed by dpm on SI and paritial CI.
Pointed out by Francis David <david.francis@amd.com>
v2: dal only need to set min_dcefclk and min_fclk to smu.
so use display_clock_voltage_request interface,
instand of update all display configuration.
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>