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Alex Bradbury [Tue, 14 Feb 2017 05:17:23 +0000 (05:17 +0000)]
[RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295027
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Alex Bradbury [Tue, 14 Feb 2017 05:15:24 +0000 (05:15 +0000)]
[RISCV] Fix unused variable in RISCVMCTargetDesc. NFC
Also, for better uniformity use TargetRegistry::RegisterMCAsmInfo rather than
RegisterMCAsmInfoFn. Again, no functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295026
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Peter Collingbourne [Tue, 14 Feb 2017 03:42:38 +0000 (03:42 +0000)]
ThinLTOBitcodeWriter: Write available_externally copies of VCP eligible functions to merged module.
Differential Revision: https://reviews.llvm.org/D29701
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295021
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Mehdi Amini [Tue, 14 Feb 2017 02:20:51 +0000 (02:20 +0000)]
[ThinLTO] Make a copy of buffer identifier in ThinLTOCodeGenerator
We can't assume that the `const char *` provided through libLTO has a
lifetime that expands beyond the codegenerator itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295018
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Philip Reames [Tue, 14 Feb 2017 01:38:31 +0000 (01:38 +0000)]
[LICM] Make store promotion work in the face of unordered atomics
Extend our store promotion code to deal with unordered atomic accesses. Ordered atomics continue to be unhandled.
Most of the change is straight-forward, the only complicated bit is in the reasoning around mixing of atomic and non-atomic memory access. Rather than trying to reason about the complex semantics in these cases, I simply disallowed promotion when both atomic and non-atomic accesses are present. This is conservatively correct.
It seems really tempting to just promote all access to atomics, but the original accesses might have been conditional. Since we can't lower an arbitrary atomic type, it might not be safe to promote all access to atomic. Consider a loop like the following:
while(b) {
load i128 ...
if (can lower i128 atomic)
store atomic i128 ...
else
store i128
}
It could be there's no race on the location and thus the code is perfectly well defined even if we can't lower a i128 atomically.
It's not clear we need to be this conservative - arguably the program above is brocken since it can't be lowered unless the branch is folded - but I didn't want to have to fix any fallout which might result.
Differential Revision: https://reviews.llvm.org/D15592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295015
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Reid Kleckner [Tue, 14 Feb 2017 01:38:14 +0000 (01:38 +0000)]
Undef MemoryFence, which is defined to _mm_mfence by winnt.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295014
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Reid Kleckner [Tue, 14 Feb 2017 01:21:39 +0000 (01:21 +0000)]
Use std::call_once on Windows
Previously we could not use it because std::once_flag's default
constructor was not constexpr. Today, all supported versions of VS
correctly mark it constexpr. I confirmed that MSVC 2015 does not emit
any problematic racy dynamic initialization code, so we should be safe
to use this now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295013
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Eugene Zelenko [Tue, 14 Feb 2017 00:33:36 +0000 (00:33 +0000)]
[MC] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
Same changes in files affected by reduced MC headers dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295009
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Peter Collingbourne [Tue, 14 Feb 2017 00:28:13 +0000 (00:28 +0000)]
FunctionAttrs: Factor out a function for querying memory access of a specific copy of a function. NFC.
This will later be used by ThinLTOBitcodeWriter to add copies of readnone
functions to the regular LTO module.
Differential Revision: https://reviews.llvm.org/D29695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295008
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Michael Kuperstein [Mon, 13 Feb 2017 23:42:27 +0000 (23:42 +0000)]
Silence redundant semicolon warnings. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295005
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Andrew Kaylor [Mon, 13 Feb 2017 23:38:52 +0000 (23:38 +0000)]
[X86] Add MXCSR register
This adds MXCSR to the set of recognized registers for X86 targets and updates the instructions that read or write it. I do not intend for all of the various floating point instructions that implicitly use the control bits or update the status bits of this register to ever have that usage modeled by default. However, when constrained floating point modes (such as strict FP exception status modeling or dynamic rounding modes) are enabled, implicit use/def information for MXCSR will be added to those instructions.
Until those additional updates are made this should cause (almost?) no functional changes. Theoretically, this will prevent instructions like LDMXCSR and STMXCSR from being moved past one another, but that should be prevented anyway and I haven't found a case where it is happening now.
Differential Revision: https://reviews.llvm.org/D29903
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295004
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Sanjoy Das [Mon, 13 Feb 2017 23:19:07 +0000 (23:19 +0000)]
[LangRef] Explicitly allow readnone and reaodnly functions to unwind
Summary:
This change edits the language reference to explicitly allow the
existence of readnone and readonly functions that can throw. Full
discussion at
http://lists.llvm.org/pipermail/llvm-dev/2017-January/108637.html
Reviewers: dberlin, chandlerc, hfinkel, majnemer
Reviewed By: majnemer
Subscribers: majnemer, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D28740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295000
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Sanjoy Das [Mon, 13 Feb 2017 23:14:03 +0000 (23:14 +0000)]
[LangRef] Update the TBAA section
Summary:
Update the TBAA section to mention the struct path TBAA that LLVM
implements today. This is not a proposal or change in semantics -- it
is intended only to **document** what LLVM already does today.
This is related to https://reviews.llvm.org/D26438 where I've tried to
implement some of the constraints as verifier checks.
Reviewers: anna, reames, rsmith, chandlerc, hfinkel, rjmccall, mehdi_amini, dexonsmith, manmanren
Reviewed By: manmanren
Subscribers: dberlin, dberris, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D26831
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294999
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Sanjay Patel [Mon, 13 Feb 2017 23:10:51 +0000 (23:10 +0000)]
[FunctionAttrs] try to extend nonnull-ness of arguments from a callsite back to its parent function
As discussed here:
http://lists.llvm.org/pipermail/llvm-dev/2016-December/108182.html
...we should be able to propagate 'nonnull' info from a callsite back to its parent.
The original motivation for this patch is our botched optimization of "dyn_cast" (PR28430),
but this won't solve that problem.
The transform is currently disabled by default while we wait for clang to work-around
potential security problems:
http://lists.llvm.org/pipermail/cfe-dev/2017-January/052066.html
Differential Revision: https://reviews.llvm.org/D27855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294998
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Amaury Sechet [Mon, 13 Feb 2017 23:00:23 +0000 (23:00 +0000)]
Revert autogenerated check result for test/CodeGen/X86/atomic-minmax-i6432.ll as they don't regenerate cleanly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294996
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Tim Northover [Mon, 13 Feb 2017 22:14:16 +0000 (22:14 +0000)]
GlobalISel: represent atomic loads & stores via the MachineMemOperand.
Also make sure the AArch64 backend doesn't try to convert them into normal
loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294993
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Tim Northover [Mon, 13 Feb 2017 22:14:08 +0000 (22:14 +0000)]
MIR: parse & print the atomic parts of a MachineMemOperand.
We're going to need them very soon for GlobalISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294992
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Reid Kleckner [Mon, 13 Feb 2017 21:33:26 +0000 (21:33 +0000)]
[CodeGen] Use bitfields instead of manual masks in ArgFlagsTy, NFC
This revealed that we actually have 8 more unused flag bits, and byval
size doesn't need to be a bitfield at all.
This came up during code review here:
https://reviews.llvm.org/D29668#inline-258469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294989
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Taewook Oh [Mon, 13 Feb 2017 21:12:27 +0000 (21:12 +0000)]
Address post-commit comments for https://reviews.llvm.org/D29596. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294985
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Arnold Schwaighofer [Mon, 13 Feb 2017 19:58:28 +0000 (19:58 +0000)]
swiftcc: Don't emit tail calls from callers with swifterror parameters
Backends don't support this yet. They would have to move to the swifterror
register before the tail call to make sure it is live-in to the call.
rdar://
30495920
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294982
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Peter Collingbourne [Mon, 13 Feb 2017 19:26:18 +0000 (19:26 +0000)]
IR: Type ID summary extensions for WPD; thread summary into WPD pass.
Make the whole thing testable by adding YAML I/O support for the WPD
summary information and adding some negative tests that exercise the
YAML support.
Differential Revision: https://reviews.llvm.org/D29782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294981
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Alexey Bataev [Mon, 13 Feb 2017 19:08:19 +0000 (19:08 +0000)]
[SLP] Test for extractelement cost fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294980
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Taewook Oh [Mon, 13 Feb 2017 18:15:31 +0000 (18:15 +0000)]
Make MachineBasicBlock::updateTerminator to update DebugLoc as well
Summary:
Currently MachineBasicBlock::updateTerminator simply drops DebugLoc for newly created branch instructions, which may cause incorrect stepping and/or imprecise sample profile data. Below is an example:
```
1 extern int bar(int x);
2
3 int foo(int *begin, int *end) {
4 int *i;
5 int ret = 0;
6 for (
7 i = begin ;
8 i != end ;
9 i++)
10 {
11 ret += bar(*i);
12 }
13 return ret;
14 }
```
Below is a bitcode of 'foo' at the end of LLVM-IR level optimizations with -O3:
```
define i32 @foo(i32* readonly %begin, i32* readnone %end) !dbg !4 {
entry:
%cmp6 = icmp eq i32* %begin, %end, !dbg !9
br i1 %cmp6, label %for.end, label %for.body.preheader, !dbg !12
for.body.preheader: ; preds = %entry
br label %for.body, !dbg !13
for.body: ; preds = %for.body.preheader, %for.body
%ret.08 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
%i.07 = phi i32* [ %incdec.ptr, %for.body ], [ %begin, %for.body.preheader ]
%0 = load i32, i32* %i.07, align 4, !dbg !13, !tbaa !15
%call = tail call i32 @bar(i32 %0), !dbg !19
%add = add nsw i32 %call, %ret.08, !dbg !20
%incdec.ptr = getelementptr inbounds i32, i32* %i.07, i64 1, !dbg !21
%cmp = icmp eq i32* %incdec.ptr, %end, !dbg !9
br i1 %cmp, label %for.end.loopexit, label %for.body, !dbg !12, !llvm.loop !22
for.end.loopexit: ; preds = %for.body
br label %for.end, !dbg !24
for.end: ; preds = %for.end.loopexit, %entry
%ret.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.end.loopexit ]
ret i32 %ret.0.lcssa, !dbg !24
}
```
where
```
!12 = !DILocation(line: 6, column: 3, scope: !11)
```
. As you can see, the terminator of 'entry' block, which is a loop control branch, has a DebugLoc of line 6, column 3. Howerver, after the execution of 'MachineBlock::updateTerminator' function, which is triggered by MachineSinking pass, the DebugLoc info is dropped as below (see there's no debug-location for JNE_1):
```
bb.0.entry:
successors: %bb.4(0x30000000), %bb.1.for.body.preheader(0x50000000)
liveins: %rdi, %rsi
%6 = COPY %rsi
%5 = COPY %rdi
%8 = SUB64rr %5, %6, implicit-def %eflags, debug-location !9
JNE_1 %bb.1.for.body.preheader, implicit %eflags
```
This patch addresses this issue and make newly created branch instructions to keep debug-location info.
Reviewers: aprantl, MatzeB, craig.topper, qcolombet
Reviewed By: qcolombet
Subscribers: qcolombet, llvm-commits
Differential Revision: https://reviews.llvm.org/D29596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294976
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Matthew Simpson [Mon, 13 Feb 2017 18:02:35 +0000 (18:02 +0000)]
Revert "[LV] Extend trunc optimization to all IVs with constant integer steps"
This reverts commit r294967. This patch caused execution time slowdowns in a
few LLVM test-suite tests, as reported by the clang-cmake-aarch64-quick bot.
I'm reverting to investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294973
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Quentin Colombet [Mon, 13 Feb 2017 17:38:59 +0000 (17:38 +0000)]
[FastISel] Add a diagnostic to warm on fallback.
This is consistent with what we do for GlobalISel. That way, it is easy
to see whether or not FastISel is able to fully select a function.
At some point we may want to switch that to an optimization remark.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294970
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James Molloy [Mon, 13 Feb 2017 17:18:00 +0000 (17:18 +0000)]
[ARM] Fix crash caused by r294945
I'd missed a creator of FCMP nodes - duplicateCmp().
Kindly and promptly reported by Gabor Ballabas, due to his CSiBE test suite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294968
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Matthew Simpson [Mon, 13 Feb 2017 16:48:00 +0000 (16:48 +0000)]
[LV] Extend trunc optimization to all IVs with constant integer steps
This patch extends the optimization of truncations whose operand is an
induction variable with a constant integer step. Previously we were only
applying this optimization to the primary induction variable. However, the cost
model assumes the optimization is applied to the truncation of all integer
induction variables (even regardless of step type). The transformation is now
applied to the other induction variables, and I've updated the cost model to
ensure it is better in sync with the transformation we actually perform.
Differential Revision: https://reviews.llvm.org/D29847
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294967
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Simon Dardis [Mon, 13 Feb 2017 16:42:35 +0000 (16:42 +0000)]
[mips] Fix failing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294966
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Sanjay Patel [Mon, 13 Feb 2017 16:17:29 +0000 (16:17 +0000)]
fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294964
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Davide Italiano [Mon, 13 Feb 2017 16:08:36 +0000 (16:08 +0000)]
[llvm-lto2] Fix typo spotted by Teresa (r294885 post-commit review).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294962
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Simon Dardis [Mon, 13 Feb 2017 16:06:48 +0000 (16:06 +0000)]
[mips] divide macro instruction cleanup.
Clean up the implementation of divide macro expansion by getting rid of a
FIXME regarding magic numbers and branch instructions. Match GAS' behaviour
for expansion of ddiv / div in the two and three operand cases. Add the two
operand alias for MIPSR6. Finally, optimize macro expansion cases where the
divisior is the $zero register.
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D29887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294960
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Simon Pilgrim [Mon, 13 Feb 2017 15:31:08 +0000 (15:31 +0000)]
Fix indentation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294959
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Davide Italiano [Mon, 13 Feb 2017 15:26:22 +0000 (15:26 +0000)]
[PM] Hook up the instrumented PGO machinery in the new PM.
Differential Revision: https://reviews.llvm.org/D29308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294955
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Davide Italiano [Mon, 13 Feb 2017 14:39:51 +0000 (14:39 +0000)]
[LTO] Make sure we flush buffers to work around linker shenanigans.
lld, at least, doesn't call global destructors by default (unless
--full-shutdown is passed) because it's, allegedly, expensive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294953
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Simon Pilgrim [Mon, 13 Feb 2017 14:20:13 +0000 (14:20 +0000)]
[X86][SSE] Add v4f32 and v2f64 extract to store tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294952
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Sanne Wouda [Mon, 13 Feb 2017 14:07:45 +0000 (14:07 +0000)]
[CodeGen] fix alignment of JUMPTABLE_INSTS on v8M.base
Summary:
The attached test case fails with "fatal error: error in backend:
misaligned pc-relative fixup value" as the jump table is misaligned.
The EmitAlignment existed already for ARM and Thumb-1 code, but was
missing for Thumb-2.
The test checks that the fatal error disappears when generating an obj
file, as well as checking the align directive is there when producing an
asm file.
Reviewers: rengolin, grosbach, t.p.northover, jmolloy, SjoerdMeijer, samparker
Reviewed By: samparker
Subscribers: samparker, aemerson, llvm-commits
Differential Revision: https://reviews.llvm.org/D29650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294950
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James Molloy [Mon, 13 Feb 2017 14:07:39 +0000 (14:07 +0000)]
[Thumb-1] TBB generation: spot redefinitions of index register
We match a sequence of 3-4 instructions into a tTBB pseudo. One of our checks is that
a particular register in that sequence is killed (so it can be clobbered by the pseudo).
We weren't noticing if an errant MOV or other instruction had infiltrated the
sequence we were walking. If it had, and it defined the register we've already
identified as killed, it makes it live across the tBR_JT and thus unclobberable.
Notice this case and bail out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294949
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James Molloy [Mon, 13 Feb 2017 14:07:25 +0000 (14:07 +0000)]
[ARM] Register ConstantIslands with the pass manager
This allows us to use -stop-before/-stop-after/-run-pass - we can now write
.mir tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294948
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Sanne Wouda [Mon, 13 Feb 2017 13:58:00 +0000 (13:58 +0000)]
[Assembler] Improve diagnostics for inline assembly.
Summary:
Keep a vector of LocInfos around; one for each call to EmitInlineAsm.
Since each call to EmitInlineAsm creates a new buffer in the inline asm
SourceMgr, we can use the buffer number to map to the right LocInfo.
Reviewers: rengolin, grosbach, rnk, echristo
Reviewed By: rnk
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D29769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294947
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Simon Pilgrim [Mon, 13 Feb 2017 13:40:12 +0000 (13:40 +0000)]
[X86][SSE] Add more thorough extract to store tests
Added v4i32 and v2i64 tests and test on i686 as well as x86_64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294946
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James Molloy [Mon, 13 Feb 2017 12:32:47 +0000 (12:32 +0000)]
[ARM] Use VCMP, not VCMPE, for floating point equality comparisons
When generating a floating point comparison we currently unconditionally
generate VCMPE. This has the sideeffect of setting the cumulative Invalid
bit in FPSCR if any of the operands are QNaN.
It is expected that use of a relational predicate on a QNaN value should
raise Invalid. Quoting from the C standard:
The relational and equality operators support the usual mathematical
relationships between numeric values. For any ordered pair of numeric
values exactly one of relationships the less, greater, equal and is true.
Relational operators may raise the floating-point exception when argument
values are NaNs.
The standard doesn't explicitly state the expectation for equality operators,
but the implication and obvious expectation is that equality operators
should not raise Invalid on a QNaN input, as those predicates are wholly
defined on unordered inputs (to return not equal).
Therefore, add a new operand to ARMISD::FPCMP and FPCMPZ indicating if
QNaN should raise Invalid, and pipe that through to TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294945
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Simon Pilgrim [Mon, 13 Feb 2017 11:52:58 +0000 (11:52 +0000)]
[X86][SSE] Create matchVectorShuffleWithUNPCK helper function.
Currently only used by target shuffle combining - will use it for lowering as well in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294943
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Pierre Gousseau [Mon, 13 Feb 2017 09:57:17 +0000 (09:57 +0000)]
[X86] Improve readability of test/CodeGen/X86/lzcnt-zext-cmp.ll by adding a common check prefix ALL. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294938
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Ayman Musa [Mon, 13 Feb 2017 09:55:48 +0000 (09:55 +0000)]
[X86][AVX512] Fix operand classes for some AVX512 instructions to keep consistency between VEX/EVEX versions of the same instruction.
Differential Revision: https://reviews.llvm.org/D29873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294937
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Andrew V. Tischenko [Mon, 13 Feb 2017 09:43:37 +0000 (09:43 +0000)]
Compile time decreasing in the case we're dealing with Machine Combiner.
Before this patch compile time was about 21s (see below). After this patch
we have less than 2s (see bellow).
Intel(R) Xeon(R) CPU E5-2676 v3 @ 2.40GHz
DAGCombiner - trunk
time ./llc spill_fdiv.ll -o /dev/null -enable-unsafe-fp-math
real 0m1.685s
DAGCombiner + Speed patch
time ./llc spill_fdiv.ll -o /dev/null -enable-unsafe-fp-math
real 0m1.655s
MachineCombiner w/o Speed patch
time ./llc spill_fdiv.ll -o /dev/null -enable-unsafe-fp-math
real 0m21.614s
MachineCombiner + Speed patch
time ./llc spill_fdiv.ll -o /dev/null -enable-unsafe-fp-math
real 0m1.593s
The test spill_fdiv.ll is attached to D29627
D29627 should be closed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294936
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Alexey Bataev [Mon, 13 Feb 2017 08:01:26 +0000 (08:01 +0000)]
[SLP] Fix for PR31690: Allow using of extra values in horizontal
reductions.
Currently, LLVM supports vectorization of horizontal reduction
instructions with initial value set to 0. Patch supports vectorization
of reduction with non-zero initial values. Also, it supports a
vectorization of instructions with some extra arguments, like:
```
float f(float x[], int a, int b) {
float p = a % b;
p += x[0] + 3;
for (int i = 1; i < 32; i++)
p += x[i];
return p;
}
```
Patch allows vectorization of this kind of horizontal reductions.
Differential Revision: https://reviews.llvm.org/D29727
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294934
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Craig Topper [Mon, 13 Feb 2017 04:53:33 +0000 (04:53 +0000)]
[DAGCombiner] Teach DAG combine that inserting an extract_subvector result into the same location of a an undef vector can just use the original input to the extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294932
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Craig Topper [Mon, 13 Feb 2017 04:53:29 +0000 (04:53 +0000)]
[X86] Genericize the handling of INSERT_SUBVECTOR from an EXTRACT_SUBVECTOR to support 512-bit vectors with 128-bit or 256-bit subvectors.
We now detect that both the extract and insert indices are non-zero and convert to a shuffle. This will be lowered as a blend for 256-bit vectors or as a vshuf operations for 512-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294931
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Craig Topper [Sun, 12 Feb 2017 23:49:49 +0000 (23:49 +0000)]
[DAGCombiner] Remove the half vector width check for the combine of EXTRACT_SUBVECTOR from an INSERT_SUBVECTOR.
This gives more parallelism opportunities for AVX-512 when dealing with 128-bit extracts from 512-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294930
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Craig Topper [Sun, 12 Feb 2017 23:49:46 +0000 (23:49 +0000)]
[X86] Don't let LowerEXTRACT_SUBVECTOR call getNode for EXTRACT_SUBVECTOR.
This results in the simplifications inside of getNode running while we're legalizing nodes popped off the worklist during the final DAG combine. This basically makes a DAG combine like operation occur during this legalize step, but we don't handle something quite the same way. I think we don't recursively added the removed nodes to the DAG combiner worklist.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294929
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Daniel Berlin [Sun, 12 Feb 2017 23:28:06 +0000 (23:28 +0000)]
NewGVN: Update a number of xfailed tests to either be correct or note
why they fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294928
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Daniel Berlin [Sun, 12 Feb 2017 23:24:47 +0000 (23:24 +0000)]
NewGVN: We really pass TBAA if we enable DCE and fix the test. Note that GVN eliminates no-use readonly/readnone calls, even if they are not marked nounwind. NewGVN only eliminates them if they are marked nounwind, and thus, trivially dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294927
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Daniel Berlin [Sun, 12 Feb 2017 23:24:45 +0000 (23:24 +0000)]
NewGVN: Reverse order of congruence class elimination to maximize trivial deadness
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294926
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Daniel Berlin [Sun, 12 Feb 2017 23:24:42 +0000 (23:24 +0000)]
NewGVN: Use shouldSwapOperands in one more place
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294925
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Sanjay Patel [Sun, 12 Feb 2017 23:07:52 +0000 (23:07 +0000)]
[TargetLowering] fix SETCC SETLT folding with FP types
The bug was introduced with:
https://reviews.llvm.org/rL294863
...and manifests as a selection failure in x86, but that's actually
another bug. This fix prevents wrong codegen with -0.0, but in the
more common case when we have NSZ and NNAN (-ffast-math), we should
still be able to fold this setcc/compare.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294924
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Daniel Berlin [Sun, 12 Feb 2017 22:40:10 +0000 (22:40 +0000)]
Revert accidental commit titled "testing"
This reverts commit r294919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294923
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Daniel Berlin [Sun, 12 Feb 2017 22:25:20 +0000 (22:25 +0000)]
NewGVN: Apply the fast math flags fix in r267113 to NewGVN as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294922
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Daniel Berlin [Sun, 12 Feb 2017 22:12:20 +0000 (22:12 +0000)]
PredicateInfo: Handle critical edges
Summary:
This adds support for placing predicateinfo such that it affects critical edges.
This fixes the issues mentioned by Nuno on the mailing list.
Depends on D29519
Reviewers: davide, nlopes
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294921
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Daniel Berlin [Sun, 12 Feb 2017 22:02:47 +0000 (22:02 +0000)]
NewGVN: Fix missed call that should be to shouldSwapOperands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294920
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Daniel Berlin [Sun, 12 Feb 2017 22:02:20 +0000 (22:02 +0000)]
testing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294919
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Simon Pilgrim [Sun, 12 Feb 2017 20:53:44 +0000 (20:53 +0000)]
[X86] Fix typo in function name. NFCI.
convertBitVectorToUnsiged - convertBitVectorToUnsigned
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294914
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Saleem Abdulrasool [Sun, 12 Feb 2017 18:55:33 +0000 (18:55 +0000)]
llvm-readobj: process FreeBSD core notes
core files on FreeBSD have additional notes to capture state. Process
those notes when dumping the notes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294909
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Craig Topper [Sun, 12 Feb 2017 18:47:46 +0000 (18:47 +0000)]
[AVX-512] Add various EVEX move instructions to load folding tables using the VEX equivalents as a guide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294908
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Craig Topper [Sun, 12 Feb 2017 18:47:44 +0000 (18:47 +0000)]
[AVX-512] Add VMOV64toSDZrm CodeGenOnly instruction based on the same instruction from AVX/SSE.
I can't prove that we can select this instruction or the AVX/SSE version, but I'm adding it for consistency for now so I can continue matching the load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294907
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Craig Topper [Sun, 12 Feb 2017 18:47:40 +0000 (18:47 +0000)]
[X86] Fix a couple instruction names to use 'mr' instead of 'rm' to indicate they are stores. AVX-512 version was already named with 'mr'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294906
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Craig Topper [Sun, 12 Feb 2017 18:47:37 +0000 (18:47 +0000)]
[AVX-512] Add VPEXTRD/Q to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294905
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Simon Pilgrim [Sun, 12 Feb 2017 16:46:41 +0000 (16:46 +0000)]
[X86][SSE] Update argument names to match function name. NFCI.
The target shuffle match function arguments were using the term 'Ops' but the function names referred to them as 'Inputs' - use 'Inputs' consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294900
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Sanjay Patel [Sun, 12 Feb 2017 16:40:30 +0000 (16:40 +0000)]
[InstCombine] fold icmp sgt/slt (add nsw X, C2), C --> icmp sgt/slt X, (C - C2)
I found one special case of this transform for 'slt 0', so I removed that and added the general transform.
Alive code to check correctness:
Name: slt_no_overflow
Pre: WillNotOverflowSignedSub(C1, C2)
%a = add nsw i8 %x, C2
%b = icmp slt %a, C1
=>
%b = icmp slt %x, C1 - C2
Name: sgt_no_overflow
Pre: WillNotOverflowSignedSub(C1, C2)
%a = add nsw i8 %x, C2
%b = icmp sgt %a, C1
=>
%b = icmp sgt %x, C1 - C2
http://rise4fun.com/Alive/MH
Differential Revision: https://reviews.llvm.org/D29774
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294898
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Sanjay Patel [Sun, 12 Feb 2017 15:35:34 +0000 (15:35 +0000)]
[ValueTracking] use nonnull argument attribute to eliminate null checks
Enhancing value tracking's analysis of null-ness was suggested in D27855, so here's a first attempt at that.
This is part of solving:
https://llvm.org/bugs/show_bug.cgi?id=28430
Differential Revision: https://reviews.llvm.org/D28204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294897
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Simon Pilgrim [Sun, 12 Feb 2017 14:31:23 +0000 (14:31 +0000)]
[X86][AVX2] Add support for combining target shuffles to VPMOVZX
Initial 256-bit vector support - 512-bit support requires extra checks for AVX512BW support (PMOVZXBW) that will be handled in a future patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294896
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NAKAMURA Takumi [Sun, 12 Feb 2017 13:15:31 +0000 (13:15 +0000)]
AMDGPU::expandMemIntrinsicUses(): Fix an uninitialized variable. This function returned true or undef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294895
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Dorit Nuzman [Sun, 12 Feb 2017 09:32:53 +0000 (09:32 +0000)]
[LV/LoopAccess] Check statically if an unknown dependence distance can be
proven larger than the loop-count
This fixes PR31098: Try to resolve statically data-dependences whose
compile-time-unknown distance can be proven larger than the loop-count,
instead of resorting to runtime dependence checking (which are not always
possible).
For vectorization it is sufficient to prove that the dependence distance
is >= VF; But in some cases we can prune unknown dependence distances early,
and even before selecting the VF, and without a runtime test, by comparing
the distance against the loop iteration count. Since the vectorized code
will be executed only if LoopCount >= VF, proving distance >= LoopCount
also guarantees that distance >= VF. This check is also equivalent to the
Strong SIV Test.
Reviewers: mkuper, anemet, sanjoy
Differential Revision: https://reviews.llvm.org/D28044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294892
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Elena Demikhovsky [Sun, 12 Feb 2017 07:56:50 +0000 (07:56 +0000)]
AVX-512: Fixed DWARF register numbers for XMM16-31
The reference is here:
https://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294890
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Davide Italiano [Sun, 12 Feb 2017 05:43:25 +0000 (05:43 +0000)]
[LTO] Remove useless redirection from test. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294889
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Chandler Carruth [Sun, 12 Feb 2017 05:38:04 +0000 (05:38 +0000)]
[PM] Add devirtualization-based iteration utility into the new PM's
default pipeline.
A clang with this patch built with ASan and asserts can build all of the
test-suite as well, so it seems to not uncover any latent problems.
Differential Revision: https://reviews.llvm.org/D29853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294888
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Chandler Carruth [Sun, 12 Feb 2017 05:34:04 +0000 (05:34 +0000)]
[PM] Enable GlobalsAA in the new PM's pipeline by default.
All the invalidation issues and bugs in this seem to be fixed, it has
survived a full build of the test suite plus SPEC with asserts and ASan
enabled on the Clang binary used.
Differential Revision: https://reviews.llvm.org/D29815
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294887
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Davide Italiano [Sun, 12 Feb 2017 05:05:35 +0000 (05:05 +0000)]
[lib/LTO] Add support for hotness optremarks in the new API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294885
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Davide Italiano [Sun, 12 Feb 2017 03:47:54 +0000 (03:47 +0000)]
[LTO] Simplify this test quite a bit, @func2 is unused/unneeded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294884
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Davide Italiano [Sun, 12 Feb 2017 03:42:09 +0000 (03:42 +0000)]
[llvm-lto2] Fix typo in error message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294883
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Davide Italiano [Sun, 12 Feb 2017 03:31:30 +0000 (03:31 +0000)]
[lib/LTO] Initial support for optimization remarks in the new API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294882
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NAKAMURA Takumi [Sun, 12 Feb 2017 01:18:32 +0000 (01:18 +0000)]
Kaleidoscope-Ch7: Add TranformUtils for llvm::createPromoteMemoryToRegisterPass() added in r294870.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294881
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Craig Topper [Sat, 11 Feb 2017 23:23:11 +0000 (23:23 +0000)]
[X86] Update test case I missed in r294876.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294878
91177308-0d34-0410-b5e6-
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Craig Topper [Sat, 11 Feb 2017 22:57:12 +0000 (22:57 +0000)]
[X86] Move code for using blendi for insert_subvector out to an isel pattern. This gives the DAG combiner more opportunity to optimize without needing to dig through the blend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294876
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Craig Topper [Sat, 11 Feb 2017 22:57:09 +0000 (22:57 +0000)]
[DAGCombiner] Make the combine of INSERT_SUBVECTOR into a CONCAT_VECTOR more generic to support larger concats.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294875
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Simon Pilgrim [Sat, 11 Feb 2017 22:47:06 +0000 (22:47 +0000)]
[X86][SSE] Use VSEXT/VZEXT constant folding for SIGN_EXTEND_VECTOR_INREG/ZERO_EXTEND_VECTOR_INREG
Preparatory step for PR31712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294874
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Simon Pilgrim [Sat, 11 Feb 2017 21:55:24 +0000 (21:55 +0000)]
[X86][SSE] Improve VSEXT/VZEXT constant folding.
Generalize VSEXT/VZEXT constant folding to work with any target constant bits source not just BUILD_VECTOR .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294873
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Mehdi Amini [Sat, 11 Feb 2017 21:26:52 +0000 (21:26 +0000)]
Update Kaleidoscope tutorial and improve Windows support
Many quoted code blocks were not in sync with the actual toy.cpp
files. Improve tutorial text slightly in several places.
Added some step descriptions crucial to avoid crashes (like
InitializeNativeTarget* calls).
Solve/workaround problems with Windows (JIT'ed method not found, using
custom and standard library functions from host process).
Patch by: Moritz Kroll <moritz.kroll@gmx.de>
Differential Revision: https://reviews.llvm.org/D29864
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294870
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Amaury Sechet [Sat, 11 Feb 2017 19:34:11 +0000 (19:34 +0000)]
Fix atomic-minmax-i6432.ll .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294867
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Amaury Sechet [Sat, 11 Feb 2017 19:27:15 +0000 (19:27 +0000)]
Regen expected tests result. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294866
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Aaron Ballman [Sat, 11 Feb 2017 18:45:24 +0000 (18:45 +0000)]
Correcting several sphinx errors; should fix the LLVM documentation build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294865
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Simon Pilgrim [Sat, 11 Feb 2017 18:06:24 +0000 (18:06 +0000)]
[X86][SSE] Add early-out when trying to match blend shuffle. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294864
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Sanjay Patel [Sat, 11 Feb 2017 18:01:55 +0000 (18:01 +0000)]
[TargetLowering] check for sign-bit comparisons in SimplifyDemandedBits
I don't know if anything other than x86 vectors is affected by this change, but this may allow
us to remove target-specific intrinsics for blendv* (vector selects). The simplification arises
from the fact that blendv* instructions only use the sign-bit when deciding which vector element
to choose for the destination vector. The mechanism to fold VSELECT into SHRUNKBLEND nodes already
exists in x86 lowering; this demanded bits change just enables the transform to fire more often.
The original motivation starts with a bug for DSE of masked stores that seems completely unrelated,
but I've explained the likely steps in this series here:
https://llvm.org/bugs/show_bug.cgi?id=11210
Differential Revision: https://reviews.llvm.org/D29687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294863
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Amaury Sechet [Sat, 11 Feb 2017 17:48:49 +0000 (17:48 +0000)]
Fix typo in test filename. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294860
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Amaury Sechet [Sat, 11 Feb 2017 17:48:48 +0000 (17:48 +0000)]
Fix indentation in X86ISelLowering. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294859
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Craig Topper [Sat, 11 Feb 2017 17:35:28 +0000 (17:35 +0000)]
[AVX-512] Add VPMINS/MINU/MAXS/MAXU instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294858
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Craig Topper [Sat, 11 Feb 2017 17:35:25 +0000 (17:35 +0000)]
[X86] Improve alphabetizing of load folding tables. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294857
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Simon Pilgrim [Sat, 11 Feb 2017 17:27:21 +0000 (17:27 +0000)]
[X86][SSE] Convert getTargetShuffleMaskIndices to use getTargetConstantBitsFromNode.
Removes duplicate constant extraction code in getTargetShuffleMaskIndices.
getTargetConstantBitsFromNode - adds support for VZEXT_MOVL(SCALAR_TO_VECTOR) and fail if the caller doesn't support undef bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294856
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Simon Pilgrim [Sat, 11 Feb 2017 16:42:07 +0000 (16:42 +0000)]
[X86] Merge repeated getScalarValueSizeInBits calls. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294852
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Daniel Berlin [Sat, 11 Feb 2017 15:20:15 +0000 (15:20 +0000)]
NewGVN: Reverse sense of this test to make it clearer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294851
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Daniel Berlin [Sat, 11 Feb 2017 15:13:49 +0000 (15:13 +0000)]
NewGVN: Add missing initialization of NumFuncArgs lost due to bad merge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294850
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