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Olof Johansson [Mon, 28 Oct 2013 17:11:42 +0000 (10:11 -0700)]
Merge branch 'cleanup/dt-clock' into next/soc
Merging in dt clock cleanup as a pre-req with some of the later SoC branches.
There are a handful of conflicts here -- some of the already merged SoC
branches should have been based on the cleanup but weren't.
In particular, a remove/add of include on highbank and two remove/remove
conflicts on kirkwood were fixed up.
* cleanup/dt-clock: (28 commits)
ARM: vt8500: remove custom .init_time hook
ARM: vexpress: remove custom .init_time hook
ARM: tegra: remove custom .init_time hook
ARM: sunxi: remove custom .init_time hook
ARM: sti: remove custom .init_time hook
ARM: socfpga: remove custom .init_time hook
ARM: rockchip: remove custom .init_time hook
ARM: prima2: remove custom .init_time hook
ARM: nspire: remove custom .init_time hook
ARM: nomadik: remove custom .init_time hook
ARM: mxs: remove custom .init_time hook
ARM: kirkwood: remove custom .init_time hook
ARM: imx: remove custom .init_time hook
ARM: highbank: remove custom .init_time hook
ARM: exynos: remove custom .init_time hook
ARM: dove: remove custom .init_time hook
ARM: bcm2835: remove custom .init_time hook
ARM: bcm: provide common arch init for DT clocks
ARM: call of_clk_init from default time_init handler
ARM: vt8500: prepare for arch-wide .init_time callback
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Kevin Hilman [Fri, 25 Oct 2013 10:46:38 +0000 (03:46 -0700)]
Merge tag 'tegra-for-3.13-soc-v2' of git://git./linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: core SoC support changes for 3.13
This branch includes:
* SoC fuse values are used as device randomness at boot.
* Initial support for the Tegra124 SoC is added. When coupled with an
appropriate clock driver, which should also be merged for 3.13, we are
able to boot to user-space using an initrd.
* The powergate code gains support for Tegra114.
This branch is based on previous pull request tegra-for-3.13-cleanup.
* tag 'tegra-for-3.13-soc-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: Add Tegra114 powergate support
ARM: tegra: Constify list of CPU domains
ARM: tegra: Remove duplicate powergate defines
ARM: tegra: add LP1 support code for Tegra124
ARM: tegra: re-calculate the LP1 data for Tegra30/114
ARM: tegra: enable CPU idle for Tegra124
ARM: tegra: make tegra_resume can work with current and later chips
ARM: tegra: CPU hotplug support for Tegra124
ARM: tegra: add PMC compatible value for Tegra124
ARM: tegra: add Tegra124 SoC support
ARM: tegra: add fuses as device randomness
ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
ARM: tegra: make tegra_init_fuse() __init
ARM: tegra: remove much of iomap.h
ARM: tegra: move resume vector define to irammap.h
ARM: tegra: delete gpio-names.h
ARM: tegra: delete stale header content
ARM: tegra: remove common.c
ARM: tegra: split tegra_pmc_init() in two
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Thierry Reding [Wed, 16 Oct 2013 17:19:02 +0000 (19:19 +0200)]
ARM: tegra: Add Tegra114 powergate support
Extend the list of power gates found on Tegra114. Note that there are
now holes in the list, so perhaps a simple array is no longer the best
data structure to represent it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Wed, 16 Oct 2013 17:19:01 +0000 (19:19 +0200)]
ARM: tegra: Constify list of CPU domains
There's no need to modify these at runtime, it is static data and never
needs to change.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Thierry Reding [Wed, 16 Oct 2013 17:19:00 +0000 (19:19 +0200)]
ARM: tegra: Remove duplicate powergate defines
Instead of duplicating powergate defines, reuse the ones from the
include/linux/tegra-powergate.h header file.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Fri, 11 Oct 2013 09:58:38 +0000 (17:58 +0800)]
ARM: tegra: add LP1 support code for Tegra124
The LP1 suspend procedure is the same with Tegra30 and Tegra114. Just
need to update the difference of the register address, then we can
continue to share the code.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Fri, 11 Oct 2013 09:58:37 +0000 (17:58 +0800)]
ARM: tegra: re-calculate the LP1 data for Tegra30/114
This patch re-calculates the LP1 data of tegra30/114_sdram_pad_address
to base on its label not rely on others. This can make easier to
maintain if some other Tegra chips keep re-using these codes in the
future. And change the name of tegra30_sdram_pad_save to
tegra_sdram_pad_save to make it more common to other chips.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Fri, 11 Oct 2013 09:57:32 +0000 (17:57 +0800)]
ARM: tegra: enable CPU idle for Tegra124
The CPUIdle function of Tegra124 is identical to Tegra114, so we share
the same driver with Tegra114.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Fri, 11 Oct 2013 09:57:31 +0000 (17:57 +0800)]
ARM: tegra: make tegra_resume can work with current and later chips
Because the CPU0 was the first up and the last down core when cluster
power up/down or platform suspend. So only CPU0 needs the rest of the
functions to reset flow controller and re-enable SCU and L2. We also
move the L2 init function for Cortex-A15 to there. The secondery CPU
can just call cpu_resume.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Fri, 11 Oct 2013 09:57:30 +0000 (17:57 +0800)]
ARM: tegra: CPU hotplug support for Tegra124
The procedure of CPU hotplug for Tegra124 is same with Tegra114. We
re-use the same function with it.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Tue, 8 Oct 2013 04:50:04 +0000 (12:50 +0800)]
ARM: tegra: add PMC compatible value for Tegra124
The PMC HW is not identical to the existing Tegra SoC. Hence add to it.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Tue, 8 Oct 2013 04:50:03 +0000 (12:50 +0800)]
ARM: tegra: add Tegra124 SoC support
Add Tegra124 SoC support that base on CortexA15MP Core. And enable the
SMP function that can re-use the same procedure with Tegra114.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Stephen Warren [Thu, 12 Sep 2013 22:51:19 +0000 (16:51 -0600)]
ARM: tegra: add fuses as device randomness
Various fuses on Tegra include information that's unique to an individual
chip, or a subset of chips. Call add_device_randomness() with this data
to perturb the initial state of the random pool.
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Kevin Hilman [Fri, 18 Oct 2013 14:50:11 +0000 (07:50 -0700)]
Merge tag 'omap-for-v3.13/am43xx-hwmod-signed' of git://git./linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
Changes needed for am43xx for the hwmod data.
This will be the last new set of hwmod data for any SoC
as future SoCs will use a driver and device tree based
approach. But before that can be dealt with, we need to
first sort out the pending driver/clk issues.
Queued by Paul Walmsley <paul@pwsan.com>:
Add hwmod and PRCM data for the TI AM43xx family of SoCs.
Under normal circumstances, these patches would not be merged.
The hwmod and PRCM data should be moved out either to DT data or
to drivers/. Also, the current implementation trades off lines
of diff by dynamically rewriting static data at runtime, which is
a bad practice - it causes future maintenance headaches.
However, after speaking with my upstream, it sounds like it's
better to merge these patches in their current state, due to long
term considerations.
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/
20131015213706/
Due to the lack of an AM43xx board and any available public
documentation, it's impossible for me to review or test that
platform in any meaningful way. But at least the tests above
verify that the patches don't affect existing platforms -
particularly AM33xx.
* tag 'omap-for-v3.13/am43xx-hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2: hwmod: Add qspi data for am437x.
ARM: OMAP2+: hwmod: Add USB hwmod data for AM437x.
ARM: OMAP2+: AM43x PRCM init
ARM: OMAP2+: AM43x: PRCM kbuild
ARM: OMAP2+: hwmod: AM43x operations
ARM: OMAP2+: hwmod: AM43x support
ARM: OMAP2+: CM: AM43x clockdomain data
ARM: OMAP2+: PM: AM43x powerdomain data
ARM: OMAP2+: PRCM: AM43x definitions
ARM: OMAP2+: hwmod: AM335x: remove static register offs
ARM: OMAP2+: hwmod: AM335x: runtime register update
ARM: OMAP2+: hwmod: AM335x/AM43x: move common data
ARM: OMAP2+: CM: cm_inst offset s16->u16
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Kevin Hilman [Thu, 17 Oct 2013 22:27:54 +0000 (15:27 -0700)]
Merge tag 'highbank-for-3.13' of git://git./linux/kernel/git/robh/linux into next/soc
From Rob Herring:
Highbank platform updates for 3.13
- convert Calxeda cpuidle driver to a platform driver and to use PSCI
- convert highbank smp_ops and suspend to PSCI
* tag 'highbank-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
dts: calxeda: add ARM PSCI binding
ARM: highbank: adapt to use ARM PSCI calls
ARM: PSCI: remove unnecessary include of arm-gic.h
cpuidle: calxeda: add support to use PSCI calls
ARM: highbank: cpuidle: convert to platform driver
cpuidle: calxeda: add cpu_pm_enter/exit calls
Kevin Hilman [Thu, 17 Oct 2013 22:05:07 +0000 (15:05 -0700)]
Merge tag 'soc-3.13-2' of git://git.infradead.org/linux-mvebu into next/soc
From Jason Cooper:
mvebu soc changes for v3.13 (round 2)
- kirkwood
- remove mbus init, pcie clk init
- retain MAC addr for DT ethernet (work around broken IP)
- docs: clarify Armada SoCs
* tag 'soc-3.13-2' of git://git.infradead.org/linux-mvebu:
Documentation: arm/Marvell: clarify Armada SoCs that match 78xx0 pattern
ARM: kirkwood: retain MAC address for DT ethernet
ARM: kirkwood: Remove unneeded PCIe clock adding
ARM: kirkwood: Remove unneeded MBus initialization
ARM: kirkwood: Add standby support
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Kevin Hilman [Thu, 17 Oct 2013 21:42:33 +0000 (14:42 -0700)]
Merge tag 'integrator-for-v3.13-2' of git://git./linux/kernel/git/linusw/linux-integrator into next/soc
From Linus Walleij:
Integrator patches for the v3.13 kernel cycle:
- Fix up the LED support
- Update the Integrator defconfig
- Remove ATAG boot path
- Move some stuff over to the device tree
* tag 'integrator-for-v3.13-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: integrator: core module registers from compatible strings
ARM: integrator: use devm_ioremap() to remap CM
cpufreq: probe the Integrator cpufreq driver from DT
ARM: integrator: move CM base into device tree
ARM: integrator: decommission the <mach/irqs.h> header
ARM: integrator: delete non-devicetree boot path
ARM: integrator: print the Linux IRQ in LL_DEBUG code
ARM: integrator: get the LM interrupts from DT
ARM: integrator: update defconfig
ARM: integrator: get the CM control register by proxy
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Kevin Hilman [Thu, 17 Oct 2013 21:36:34 +0000 (14:36 -0700)]
Merge branch 'davinci/soc' into next/soc
From Sekhar Nori:
* davinci/soc:
ARM: davinci: convert to clockevents_config_and_register
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Uwe Kleine-König [Sun, 13 Oct 2013 08:36:30 +0000 (10:36 +0200)]
ARM: davinci: convert to clockevents_config_and_register
clockevents_config_and_register is superior compared to setting
shift/mult and {min,max}_delta_ns by hand.
Tested-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
[nsekhar@ti.com: fix an alignment related checkpatch warning]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Tony Lindgren [Thu, 17 Oct 2013 17:37:27 +0000 (10:37 -0700)]
Merge tag 'for-v3.13/am43xx-support' of git://git./linux/kernel/git/pjw/omap-pending into omap-for-v3.13/hwmod
Add hwmod and PRCM data for the TI AM43xx family of SoCs.
Under normal circumstances, these patches would not be merged.
The hwmod and PRCM data should be moved out either to DT data or
to drivers/. Also, the current implementation trades off lines
of diff by dynamically rewriting static data at runtime, which is
a bad practice - it causes future maintenance headaches.
However, after speaking with my upstream, it sounds like it's
better to merge these patches in their current state, due to long
term considerations.
Basic test logs are here:
http://www.pwsan.com/omap/testlogs/am43xx_support_v3.13/
20131015213706/
Due to the lack of an AM43xx board and any available public
documentation, it's impossible for me to review or test that
platform in any meaningful way. But at least the tests above
verify that the patches don't affect existing platforms -
particularly AM33xx.
Linus Walleij [Thu, 10 Oct 2013 16:24:58 +0000 (18:24 +0200)]
ARM: integrator: core module registers from compatible strings
This augments the core machine code for the Integrator platforms
to get their references to the core module device nodes by
using compatible strings instead of predefined node names
and rename the CP syscon node to be simply "syscon".
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Thu, 10 Oct 2013 14:51:28 +0000 (16:51 +0200)]
ARM: integrator: use devm_ioremap() to remap CM
In the PCIv3 driver, use devm_ioremap() instead of just ioremap()
when remapping the system controller in the PCIv3 driver, so
the mapping will be automatically released on probe failure.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Mon, 17 Jun 2013 20:52:32 +0000 (22:52 +0200)]
cpufreq: probe the Integrator cpufreq driver from DT
This makes the Integrator cpufreq driver probe from the core
module device tree node through it's registered platforms
device, getting the memory base from the device tree,
remapping it and removing dependencies to <mach/platform.h>
and <mach/hardware.h> by moving the two affected CM
register offsets into the driver.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Rafael J. Wysocki <rjw@sisk.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sun, 16 Jun 2013 00:44:27 +0000 (02:44 +0200)]
ARM: integrator: move CM base into device tree
This moves the core module (CM) control base into the device
tree. It is a simple memory range of 0x200 bytes. Move the
cm header down into the machine directory and unexport the
cm_control() symbol as no modules are using it.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sat, 15 Jun 2013 21:58:15 +0000 (23:58 +0200)]
ARM: integrator: decommission the <mach/irqs.h> header
This header is no longer needed when we boot from the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sat, 15 Jun 2013 20:01:13 +0000 (22:01 +0200)]
ARM: integrator: delete non-devicetree boot path
The Device Tree boot path now supports everything the ATAG
boot can provide, and the two are equivalent. This deletes
the ATAG boot path from the Integrator/AP and
Integrator/CP platforms to move them on to the future.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sat, 15 Jun 2013 22:05:07 +0000 (00:05 +0200)]
ARM: integrator: print the Linux IRQ in LL_DEBUG code
The static HW irqs have no meaning in the interrupt handler
and does not correlate to the /proc/interrupts IRQ numbers
anymore, print the Linux IRQ number instead.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Sat, 15 Jun 2013 21:56:32 +0000 (23:56 +0200)]
ARM: integrator: get the LM interrupts from DT
The OF/DT boot path needs to get the LM (Logical Module)
IRQs from the device tree for coherency. This augments the
DT syscon node to contain these IRQs and alter the DT LM
code to get them from there.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Thu, 10 Oct 2013 12:00:33 +0000 (14:00 +0200)]
ARM: integrator: update defconfig
This updates the integrator defconfig, apart from the usual
re-shuffling of symbols due to restructuring of the kernel Kconfig
this will also:
- Enable IM-PD1 so all hardware is enabled out-of-the-box
- Enable the LEDs class and heartbeat trigger, so that the
LED driver in plat-versatile/ is compiled.
- Enale some debug code like the CLK debug.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Linus Walleij [Thu, 10 Oct 2013 12:11:18 +0000 (14:11 +0200)]
ARM: integrator: get the CM control register by proxy
The CM_CTRL register was accessed directly from the LED driver,
which does not work now that we get the base for the register
from the device tree. Add an accessor function to do this and
make the LED driver compile again.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Sourav Poddar [Tue, 15 Oct 2013 05:37:27 +0000 (11:07 +0530)]
ARM: OMAP2: hwmod: Add qspi data for am437x.
Add hwmod data for qspi for AM437x.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Kevin Hilman [Mon, 14 Oct 2013 22:42:08 +0000 (15:42 -0700)]
Merge tag 'omap-for-v3.13/soc-take2' of git://git./linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
SoC related changes for omaps to support the realtime
counter on newer omaps, and to fail early for omap5 es1.0
SoCs that don't have any support merged for them in the
mainline tree.
* tag 'omap-for-v3.13/soc-take2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix build error for realtime counter init if not enabled
ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register
ARM: OMAP5: id: Remove ES1.0 support
ARM: OMAP2+: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Kevin Hilman [Mon, 14 Oct 2013 22:38:13 +0000 (15:38 -0700)]
Merge tag 'omap-for-v3.13/hwmod-signed' of git://git./linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
omap hwmod related changes via Paul Walmsley <paul@pwsan.com>:
Some OMAP hwmod changes for 3.13. Significant changes here include:
- support for moving some of the hwmod flags to DT data
- support for the SSI, hardware spinlock, USB host/TLL, and RNG IP
blocks for various OMAPs
- a fix that again decouples hwmod data changes from unrelated DT data
patchsets
Basic test logs are available at:
http://www.pwsan.com/omap/testlogs/prcm_fixes_v3.13/
20131009094936/
* tag 'omap-for-v3.13/hwmod-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP5: hwmod: add missing ocp2scp hwmod data
ARM: AM33xx: hwmod: Add RNG module data
ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DT
ARM: OMAP2+: hwmod: cleanup HWMOD_INIT_NO_RESET usage
ARM: AM33xx: hwmod_data: add the sysc configuration for spinlock
ARM: OMAP5: hwmod data: Add spinlock data
ARM: OMAP5: hwmod data: Add USB Host and TLL modules
ARM: OMAP2+: hwmod data: Add SSI information
ARM: OMAP2+: hwmod: check for module address space during init
Kevin Hilman [Mon, 14 Oct 2013 17:30:11 +0000 (10:30 -0700)]
ARM: keystone: fix PM domain initcall to be keystone only
initcalls need to have platform specific checks so they are not run in
multi-platform builds.
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
George Cherian [Mon, 14 Oct 2013 12:36:24 +0000 (18:06 +0530)]
ARM: OMAP2+: hwmod: Add USB hwmod data for AM437x.
Add hwmod for USBSS and the OCP2SCP for AM437x.
AM437x has got 2 instances of USBSS.
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Ambresh K [Sat, 12 Oct 2013 10:16:37 +0000 (15:46 +0530)]
ARM: OMAP2+: AM43x PRCM init
Initialise AM43x HWMOD, powerdomains and clockdomains.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Afzal Mohammed [Sat, 12 Oct 2013 10:16:28 +0000 (15:46 +0530)]
ARM: OMAP2+: AM43x: PRCM kbuild
Build AM43x power domain, clock domain and hwmod data.
Many of AM43x IP's and interconnects are similar as that in AM335x,
hence AM335x hwmod data is being reused with necessary changes.
Earlier the plan was to reuse AM335x specific PRCM code, but as AM43x
PRCM register layout is much similar to OMAP4/5, AM335x PRCM is
divorced and instead married with OMAP4/5 PRCM for AM43x.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Afzal Mohammed [Sat, 12 Oct 2013 10:16:20 +0000 (15:46 +0530)]
ARM: OMAP2+: hwmod: AM43x operations
Reuse OMAP4 operations on AM43x.
Context related ops are not used on AM43x, as this would not add value
when using DT and AM43x is DT only boot. This additionally helps not to
add context register offset for each hwmod.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Afzal Mohammed [Sat, 12 Oct 2013 10:16:12 +0000 (15:46 +0530)]
ARM: OMAP2+: hwmod: AM43x support
Add hwmod support for IP's that are present in AM43x, but not in AM335x.
AM43x additional ones added here are,
1. synctimer
2. timer8-11
3. ehrpwm3-5
4. spi2-4
5. gpio4-5
AM43x pruss interconnect which is different as compared to AM335x, has
been taken care.
And register offsets for same hwmod's shared with AM335x is different,
AM43x register offsets are updated appropriately.
ocp clock of those in l4_wkup is fed from "sys_clkin_ck" instead of
"dpll_core_m4_div2_ck", so "ocpif" for those in AM43x l4_wkup has been
added seperately.
hwmod's has been added for those that have main clock (wkup_m3, control,
gpio0) and clock domain (l4_hs) different from AM335x. debugss and
adc_tsc that have different clocks and clockdomains repectively has not
been added due to the reasons mentioned below.
AM43x also has IP's like qspi, hdq1w, vpfe, des, rng, usb, dss, debugss,
adc_tsc. These are not handled here due to both/either of following
reasons,
1. To avoid churn; most of them don't have DT bindings, which would
necessitate adding address space in hwmod, which any way would have
to be removed once DT bindings happen with driver support.
2. patches would come in from sources other than the author
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Ambresh K [Sat, 12 Oct 2013 10:16:03 +0000 (15:46 +0530)]
ARM: OMAP2+: CM: AM43x clockdomain data
Add the data file to describe clock domains in AM43x SoC.
OMAP4 clockdomain operations is being reused here.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Ambresh K [Sat, 12 Oct 2013 10:15:54 +0000 (15:45 +0530)]
ARM: OMAP2+: PM: AM43x powerdomain data
Add the data file to describe all power domains in AM43x SoC.
OMAP4 powerdomain operations is being reused here.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Afzal Mohammed [Sat, 12 Oct 2013 10:15:45 +0000 (15:45 +0530)]
ARM: OMAP2+: PRCM: AM43x definitions
Add AM43x CMINST, CDOFFS, RM_RSTST & RM_RSTCTRL definitions - minimal
ones that would be used.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Afzal Mohammed [Sat, 12 Oct 2013 10:15:36 +0000 (15:45 +0530)]
ARM: OMAP2+: hwmod: AM335x: remove static register offs
Hwmod common to AM43x and AM335x has register offsets different. It is
now updated based on SoC detection at run time, hence remove statically
initialized ones.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Afzal Mohammed [Sat, 12 Oct 2013 10:15:26 +0000 (15:45 +0530)]
ARM: OMAP2+: hwmod: AM335x: runtime register update
Most of IP's in AM335x is present on AM43x and so in those cases both
will use same hwmod database (except for a few cases where clock related
details differ), but there is difference w.r.t register offset between
these. Update register offsets at runtime based on the SoC detected to
help in sharing otherwise same hwmod.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Afzal Mohammed [Sat, 12 Oct 2013 10:14:46 +0000 (15:44 +0530)]
ARM: OMAP2+: hwmod: AM335x/AM43x: move common data
AM335x and AM43x have most of the IP's and interconnect's similar.
Instead of adding redundant hwmod data, move interconnects and hwmod
similar between AM335x and AM43x to a common location. This helps in
reuse on AM43x.
AM335x interconnects that has difference and not present in AM43x are
not moved. ocp clock of those in l4_wkup is fed from a different source
for AM43x. Also pruss interconnect is different.
AM335x hwmod's that has difference other than prcm register offsets
(difference is in clocks of wkup_m3, control, gpio0, debugss and clock
domain of l4_hs, adc_tsc as compared to AM43x) and those that are not
present in AM43x are not moved.
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Ankur Kishore [Sat, 12 Oct 2013 10:14:21 +0000 (15:44 +0530)]
ARM: OMAP2+: CM: cm_inst offset s16->u16
Most of the AM43x CM reg address offsets are with MSB bit '1' (on
16-bit value) leading to arithmetic miscalculations while calculating
CLOCK ENABLE register's address because cm_inst field was a type of
"const s16", so make it "const u16".
Also modify relevant functions so as to take care of the above.
[afzal@ti.com: fixup and cleanup]
Signed-off-by: Ankur Kishore <a-kishore@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Acked-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tony Lindgren [Sat, 12 Oct 2013 00:28:04 +0000 (17:28 -0700)]
ARM: OMAP2+: Fix build error for realtime counter init if not enabled
Otherwise we can get an error with some configs:
arch/arm/mach-omap2/timer.c:73: undefined reference to `omap_smc1'
Signed-off-by: Tony Lindgren <tony@atomide.com>
Benoit Cousson [Fri, 11 Oct 2013 22:29:55 +0000 (15:29 -0700)]
ARM: OMAP5: hwmod: add missing ocp2scp hwmod data
Add this hwmod data to allow USB3 to work in OMAP5 boards.
Signed-off-by: Benoit Cousson <bcousson@baylibre.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
[tony@atomide.com: updated to apply against Paul's changes]
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Kevin Hilman [Fri, 11 Oct 2013 22:01:14 +0000 (15:01 -0700)]
Merge tag 'keystone-soc-for-arm-soc' of git://git./linux/kernel/git/ssantosh/linux-keystone into next/soc
From Santosh Shilimkar:
SOC updates for Keystone II devices:
- Clock tree support
- Clock management support using PM core
- Keystone config update for EMDA with ack from Vinod
- Enable SPI and I2C drivers
* tag 'keystone-soc-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: (510 commits)
ARM: keystone: Enable I2C and SPI bus support
ARM: keystone: Select TI_EDMA to be able to enable SPI driver
dma: Allow TI_EDMA selectable for ARCH_KEYSTONE
ARM: dts: keystone: Add the SPI nodes
ARM: dts: keystone: Add i2c device nodes
ARM: keystone: add PM domain support for clock management
ARM: keystone: Enable clock drivers
ARM: dts: keystone: Add clock phandle to UART nodes
ARM: dts: keystone: Add clock tree data to devicetree
+Linux 3.12-rc4
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Tony Lindgren [Fri, 11 Oct 2013 18:07:44 +0000 (11:07 -0700)]
Merge tag 'for-v3.13/hwmod' of git://git./linux/kernel/git/pjw/omap-pending into omap-for-v3.13/hwmod
Some OMAP hwmod changes for 3.13. Significant changes here include:
- support for moving some of the hwmod flags to DT data
- support for the SSI, hardware spinlock, USB host/TLL, and RNG IP
blocks for various OMAPs
- a fix that again decouples hwmod data changes from unrelated DT data
patchsets
Basic test logs are available at:
http://www.pwsan.com/omap/testlogs/prcm_fixes_v3.13/
20131009094936/
The summary reports that the 4460varsomom boots are failing, but this looks
incorrect - it's probably a bug in the validation scripts here.
Santosh Shilimkar [Thu, 26 Sep 2013 22:59:57 +0000 (18:59 -0400)]
ARM: keystone: Enable I2C and SPI bus support
Keystone I2C dnd SPI driver updates are already merged so lets
enable them in config.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Santosh Shilimkar [Mon, 30 Sep 2013 15:08:20 +0000 (11:08 -0400)]
ARM: keystone: Select TI_EDMA to be able to enable SPI driver
Select the TI EDMA to be able to enable SPI driver on Keystone
SOCs. Keystone SOCs share the EDMA IP with other TI SOCs.
Note that EDMA support hasn't been added and tested yet for
Keystone SOC data(device tree), but building it, is harmless since
driver like SPI already takes care of supporting non-dma mode
in the absence of such data.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Santosh Shilimkar [Mon, 30 Sep 2013 15:04:42 +0000 (11:04 -0400)]
dma: Allow TI_EDMA selectable for ARCH_KEYSTONE
Allow the TI_EDMA to be built for ARCH_KEYSTONE which also supports
the EDMA IP.
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Santosh Shilimkar [Wed, 24 Jul 2013 00:25:23 +0000 (20:25 -0400)]
ARM: dts: keystone: Add the SPI nodes
Keystone2 based SOCs supports 3 instances of SPI controllers. Add
the device nodes for them.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Santosh Shilimkar [Wed, 24 Jul 2013 00:07:07 +0000 (20:07 -0400)]
ARM: dts: keystone: Add i2c device nodes
Keystone2 based SOCs supports 3 instances of i2c controllers. Add
the device nodes for them. The i2c0 child device AT24C1024 EEPROM node
is also added. When different board variants are added in future, it
can be moved to the supported boards from common SOC file.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Santosh Shilimkar [Sun, 14 Jul 2013 21:17:39 +0000 (17:17 -0400)]
ARM: keystone: add PM domain support for clock management
Add runtime PM core support to Keystone SOCs by using the pm_clk
infrastructure of the PM core. Patch is based on Kevin's pm_domain
work on DaVinci SOCs.
Keystone SOC doesn't have depedency to enable clocks in early
in the boot and hence the clock and PM domain initialisation is done
at subsys_init() level.
Cc: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Kevin Hilman [Thu, 10 Oct 2013 22:33:39 +0000 (15:33 -0700)]
Merge tag 'renesas-soc2-for-v3.13' of git://git./linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Second Round of Renesas ARM based SoC updates for v3.13
* SMP support for r8a7791 SoC
* r8a7779_init_irq_extpin() for DT for r8a7779 and r8a7778 SoCs
* Add HPB-DMAC to r8a7779 and r8a7778 SoCs
* Add r7s72100 SoC
* Make use of ARCH timer workaround on r8a7791 SoC
* Add IRQC platform device support to r8a7791 SoC
* Add I2C clocks and aliases for the DT mode for r8a7790 SoC
* Add MAC platform device to r8a73a4 SoC
* tag 'renesas-soc2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791 SMP support
ARM: shmobile: r8a7779: split r8a7779_init_irq_extpin() for DT
ARM: shmobile: r8a7778: split r8a7778_init_irq_extpin() for DT
ARM: shmobile: r7s72100 SCIF support
ARM: shmobile: Initial r7s72100 SoC support
ARM: shmobile: r8a7791 Arch timer workaround
ARM: shmobile: r8a7791 IRQC platform device support
ARM: shmobile: Introduce r8a7791_add_standard_devices()
ARM: shmobile: Break out R-Car Gen2 setup code
ARM: shmobile: r8a73a4: add a clock alias for the DMAC in DT mode
ARM: shmobile: r8a7790: add I2C clocks and aliases for the DT mode
ARM: shmobile: r8a7779: add HPB-DMAC support
ARM: shmobile: r8a7778: add HPB-DMAC support
ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it
ARM: shmobile: Remove #gpio-ranges-cells DT property
gpio: rcar: Remove #gpio-range-cells DT property usage
ARM: shmobile: armadillo: fixup ether pinctrl naming
ARM: shmobile: Lager: add Micrel KSZ8041 PHY fixup
ARM: shmobile: update SDHI DT compatibility string to the <unit>-<soc> format
Signed-off-by: Kevin Hilman <khilman@linaro.org>
R Sricharan [Thu, 10 Oct 2013 07:43:48 +0000 (13:13 +0530)]
ARM: OMAP5/DRA7: realtime_counter: Configure CNTFRQ register
The realtime counter called master counter, produces the count
used by the private timer peripherals in the MPU_CLUSTER. The
CNTFRQ per cpu register is used to denote the frequency of the counter.
Currently the frequency value is passed from the
DT file, but this is not scalable when we have other non-DT guest
OS. This register must be set to the right value by the
secure rom code. Setting this register helps in propagating the right
frequency value across OSes.
More discussions and the reason for adding this in a non-DT
way can be seen from below.
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg93832.html
So configuring this secure register for all the cpus here.
Cc: Nishanth Menon <nm@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Lokesh Vutla [Thu, 29 Aug 2013 12:52:10 +0000 (18:22 +0530)]
ARM: AM33xx: hwmod: Add RNG module data
Add RNG hwmod data for AM33xx SoC.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Rajendra Nayak [Wed, 9 Oct 2013 07:26:55 +0000 (01:26 -0600)]
ARM: OMAP2+: hwmod: Extract no-idle and no-reset info from DT
Now that we have DT bindings to specify which devices should not
be reset and idled during init, make hwmod extract the information
(and store them in internal flags) from Device tree.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Rajendra Nayak [Tue, 20 Aug 2013 07:32:44 +0000 (13:02 +0530)]
ARM: OMAP2+: hwmod: cleanup HWMOD_INIT_NO_RESET usage
For modules/IPs/hwmods which do not have
-1- sys->class->reset()
and
-2- hardreset lines
and
-3- No way to do an ocp reset (no sysc control)
the flag 'HWMOD_INIT_NO_RESET' is not much useful.
Cleanup all such instances across various hwmod data files.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Suman Anna [Tue, 17 Sep 2013 19:31:26 +0000 (14:31 -0500)]
ARM: AM33xx: hwmod_data: add the sysc configuration for spinlock
Add the missing sysc configuration to the AM335 spinlock hwmod
data. This ensures that smart-idle is enabled whenever the module
is enabled by the driver.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Suman Anna [Tue, 17 Sep 2013 19:31:03 +0000 (14:31 -0500)]
ARM: OMAP5: hwmod data: Add spinlock data
Add the hwmod data for the spinlock IP in OMAP5 SoC.
This is needed to be able to enable the OMAP spinlock
support for OMAP5.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Roger Quadros [Wed, 9 Oct 2013 05:46:50 +0000 (23:46 -0600)]
ARM: OMAP5: hwmod data: Add USB Host and TLL modules
Add hwmod data for High Speed USB host and TLL modules
CC: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Sebastian Reichel [Wed, 9 Oct 2013 05:46:49 +0000 (23:46 -0600)]
ARM: OMAP2+: hwmod data: Add SSI information
This patch adds Synchronous Serial Interface (SSI) hwmod support for
OMAP34xx SoCs.
Signed-off-by: Sebastian Reichel <sre@debian.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Suman Anna [Wed, 9 Oct 2013 05:46:49 +0000 (23:46 -0600)]
ARM: OMAP2+: hwmod: check for module address space during init
The hwmod init sequence involves initializing and idling all the
hwmods during bootup. If a module class has sysconfig, the init
sequence utilizes the module register base for performing any
sysc configuration.
The module address space is being removed from hwmod database and
retrieved from the <reg> property of the corresponding DT node.
If a hwmod does not have its corresponding DT node defined and the
memory address space is not defined in the corresponding
omap_hwmod_ocp_if, then the module register target address space
would be NULL and any sysc programming would result in a NULL
pointer dereference and a kernel boot hang.
Handle this scenario by checking for a valid module address space
during the _init of each hwmod, and leaving it in the registered
state if no module register address base is defined in either of
the hwmod data or the DT data.
Signed-off-by: Suman Anna <s-anna@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
[paul@pwsan.com: use -ENXIO rather than -ENOMEM to indicate a missing address
space error; fixed checkpatch.pl problem]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Nishanth Menon [Wed, 18 Sep 2013 14:05:42 +0000 (09:05 -0500)]
ARM: OMAP5: id: Remove ES1.0 support
OMAP5 ES1.0 was intended as a test chip and has major register level
differences w.r.t ES2.0 revision of the chip. All register defines,
dts support has been solely added for ES2.0 version of the chip.
Further, all ES1.0 chips and platforms are supposed to have been
removed from circulation. Hence, there is no need to further retain
any resemblence of ES1.0 support in id detection code.
Remove the omap_revision handling and BUG() instead to prevent folks
who mistakenly try an older unsupported chip and report bogus errors.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Sricharan R [Wed, 18 Sep 2013 11:20:11 +0000 (16:50 +0530)]
ARM: OMAP2+: DRA7: realtime_counter: Add ratio registers for 20MHZ sys-clk frequency
The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The timer counts at a rate of 6.144 MHz.
The ratio registers are missing for a sys-clk of 20MHZ which is used
by DRA7 socs. So because of this, the counter was getting wrongly
programmed for a sys-clk of 38.4Mhz(default). So adding the ratio
registers for 20MHZ sys-clk.
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Santosh Shilimkar [Sun, 14 Jul 2013 15:44:53 +0000 (11:44 -0400)]
ARM: keystone: Enable clock drivers
Enable common clock drivers on Keystone 2 based SOCs.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Santosh Shilimkar [Fri, 19 Jul 2013 23:11:39 +0000 (19:11 -0400)]
ARM: dts: keystone: Add clock phandle to UART nodes
Now since the clock tree is added, update UART dt nodes with clock data
and remove the hard coded clock frequency.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Santosh Shilimkar [Tue, 9 Jul 2013 16:51:51 +0000 (12:51 -0400)]
ARM: dts: keystone: Add clock tree data to devicetree
Add clock tree for Keystone 2 based SOCs.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Kevin Hilman [Mon, 7 Oct 2013 14:52:33 +0000 (07:52 -0700)]
Documentation: arm/Marvell: clarify Armada SoCs that match 78xx0 pattern
New users of Marvell SoCs will potentially be confused by the MVEBU
SoCs that match the 78xx0 pattern and thus which defconfig and mach-*
directory to be looking at. Add a bit of clarification to README for
this.
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Sebastian Hesselbarth [Mon, 7 Oct 2013 20:25:11 +0000 (22:25 +0200)]
ARM: kirkwood: retain MAC address for DT ethernet
Ethernet IP on Kirkwood SoCs loose their MAC address register content
if clock gated. To allow modular ethernet driver setups and gated clocks
also on non-DT capable bootloaders, we fixup port device nodes with no
valid MAC address property. This patch copies MAC address register
contents set up by bootloaders early, notably before ethernet clocks
are gated. While at it, also reorder call sequence in _dt_init.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Reviewed-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Ezequiel Garcia [Mon, 30 Sep 2013 21:03:28 +0000 (18:03 -0300)]
ARM: kirkwood: Remove unneeded PCIe clock adding
Since the PCIe devices is properly initialized from the DT, the clocks
are now referenced in the device tree nodes, and it's not needed
to have this hack to add them explicitly.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Tested-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Ezequiel Garcia [Mon, 30 Sep 2013 21:03:27 +0000 (18:03 -0300)]
ARM: kirkwood: Remove unneeded MBus initialization
Since the MBus is initialized from the DT, it's not necessary to
call the legacy initialization.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Ezequiel Garcia [Thu, 22 Aug 2013 15:49:07 +0000 (12:49 -0300)]
ARM: kirkwood: Add standby support
Implements standby support for Kirkwood SoC. When the SoC enters
standby state the memory PM units are disabled, the DDR is set
in self-refresh mode, and the CPU is set in WFI.
At this point there's no clock gating, as that is considered each
driver's task.
Signed-off-by: Simon Guinot <sguinot@lacie.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Magnus Damm [Tue, 1 Oct 2013 08:13:16 +0000 (17:13 +0900)]
ARM: shmobile: r8a7791 SMP support
Tie in the APMU SMP code on r8a7791. When used together
with the secondary CPU device node and smp_ops in the
board specific code then this will allow use of the
two Cortex-A15 cores in the r8a7791 SoC.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Kuninori Morimoto [Wed, 2 Oct 2013 08:38:23 +0000 (01:38 -0700)]
ARM: shmobile: r8a7779: split r8a7779_init_irq_extpin() for DT
r8a7779 INTC needs IRL pin mode settings to determine
behavior of IRQ0 - IRQ3, and r8a7779_init_irq_extpin()
is controlling it via irlm parameter.
But this function registers renesas_intc_irqpin driver
if irlm was set, and this value depends on platform.
This is not good for DT.
This patch splits r8a7779_init_irq_extpin() function
into "mode settings" and "funtion register" parts
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Kuninori Morimoto [Wed, 2 Oct 2013 08:31:40 +0000 (01:31 -0700)]
ARM: shmobile: r8a7778: split r8a7778_init_irq_extpin() for DT
r8a7778 INTC needs IRL pin mode settings to determine
behavior of IRQ0 - IRQ3, and r8a7778_init_irq_extpin()
is controlling it via irlm parameter.
But this function registers renesas_intc_irqpin driver
if irlm was set, and this value depends on platform.
This is not good for DT.
This patch splits r8a7778_init_irq_extpin() function
into "mode settings" and "funtion register" parts.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 18 Sep 2013 20:11:20 +0000 (05:11 +0900)]
ARM: shmobile: r7s72100 SCIF support
Add SCIF serial port support to the r7s72100 SoC by
adding platform devices for SCIF0 -> SCIF7 together with
clock bindings. DT device description is excluded at
this point since such bindings are still under
development.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Wed, 18 Sep 2013 20:11:11 +0000 (05:11 +0900)]
ARM: shmobile: Initial r7s72100 SoC support
Add initial support for the r7272100 SoC including:
- Single Cortex-A9 CPU Core
- GIC
No static virtual mappings are used, all the components
make use of ioremap(). DT_MACHINE_START is still wrapped
in CONFIG_USE_OF to match other mach-shmobile code.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Tue, 1 Oct 2013 08:12:48 +0000 (17:12 +0900)]
ARM: shmobile: r8a7791 Arch timer workaround
Make use of the R-Car Gen2 arch timer workaround on r8a7791.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Tue, 1 Oct 2013 08:12:19 +0000 (17:12 +0900)]
ARM: shmobile: r8a7791 IRQC platform device support
Add a platform device for the r8a7791 IRQC hardware
driving IRQ pins IRQ0 to IRQ9. The Linux interrupt
number is statically assigned to allow board code
written in C to make use of static interrupt numbers.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Tue, 1 Oct 2013 08:11:53 +0000 (17:11 +0900)]
ARM: shmobile: Introduce r8a7791_add_standard_devices()
Introduce the function r8a7791_add_standard_devices() that
follows the same style as other mach-shmobile SoC code and
allows C version of board code to add on-chip devices.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Magnus Damm [Thu, 12 Sep 2013 00:32:49 +0000 (09:32 +0900)]
ARM: shmobile: Break out R-Car Gen2 setup code
Move arch timer workaround code and boot mode pin
handling from setup-r8a7790.c to setup-rcar-gen2.c.
With this in place the same code can be used on
other R-Car Generation 2 devices such as r8a7791.
Signed-off-by: Magnus Damm <damm@opensource.se>
[horms+renesas@verge.net.au trivial rebase of board-lager.c
for introduction of lager_add_standard_devices()]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Guennadi Liakhovetski [Thu, 26 Sep 2013 17:30:02 +0000 (19:30 +0200)]
ARM: shmobile: r8a73a4: add a clock alias for the DMAC in DT mode
Devices, initialised from the Device Tree and from platform code usually
have different names. This patch adds a clock alias for DMAC on r8a73a4
in DT mode.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Guennadi Liakhovetski [Thu, 26 Sep 2013 17:20:57 +0000 (19:20 +0200)]
ARM: shmobile: r8a7790: add I2C clocks and aliases for the DT mode
This patch adds clock definitions for the 4 I2C interfaces on r8a7790 and
clock aliases, suitable for the DT mode.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Max Filippov [Sun, 25 Aug 2013 17:46:23 +0000 (21:46 +0400)]
ARM: shmobile: r8a7779: add HPB-DMAC support
Add HPB-DMAC platform device on R8A7779 SoC along with its slave and channel
configurations (only for SDHI0 so far).
Signed-off-by: Max Filippov <max.filippov@cogentembedded.com>
[Sergei: moved *enum* declaring HPB-DMAC slave IDs from now removed <mach/dma.h>
to <mach/r8a7779.h>, removed #include <mach/dma.h> from setup-r8a7779.c, removed
SSI-related *enum* values and SSI-related data from hpb_dmae_slaves[] and
hpb_dmae_channels[], added ASYNCMDR.ASBTMD{20|24|43} and ASYNCMDR.ASMD{20|24|43}
fields/values, fixed comments to ASYNCMDR.ASBTMD2[123] and ASYNCMDR.ASMD2[123]
fields/values, renamed all the bit/field/value #define's to include 'HBP_DMAE_'
prefix to match the driver, moved comments after the element initializers of
hpb_dmae_channels[].]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Max Filippov [Sat, 24 Aug 2013 21:35:13 +0000 (01:35 +0400)]
ARM: shmobile: r8a7778: add HPB-DMAC support
Add HPB-DMAC platform device on R8A7778 SoC along with its slave and channel
configurations (only for SDHI0 so far).
Signed-off-by: Max Filippov <max.filippov@cogentembedded.com>
[Sergei: moved *enum* declaring HPB-DMAC slave IDs from now removed <mach/dma.h>
to <mach/r8a7778.h>, removed #include <mach/dma.h> from setup-r8a7778.c, removed
SSI-related *enum* values and SSI-related data from hpb_dmae_slaves[] and
hpb_dmae_channels[], moved the comments after the element initializers of
hpb_dmae_channels[].]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Guennadi Liakhovetski [Fri, 2 Aug 2013 14:50:40 +0000 (16:50 +0200)]
ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it
Add a DMAC platform device and clock definitions for it on r8a73a4.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Tue, 8 Oct 2013 00:44:08 +0000 (09:44 +0900)]
Merge tag 'renesas-fixes4-for-v3.12' into soc2-base
Fourth Round of Renesas ARM based SoC fixes for v3.12
* Remove unused #gpio-ranges-cells DT property
* Remove usage of deprecated #gpio-range-cells DT property
from GPIO R-Car
Property was deprecated in v3.11-rc2
* Correct ether pinctl naming for armadillo800eva board
Regression introduced in v3.10-rc5
* Add Micrel KSZ8041 PHY fixup to lager board
This resolves a problem that has been present since 3.11-rc2
* Update SDHI DT compatibility string to the <unit>-<soc> format
This makes compatibility strings consistent across all renesas
hardware which currently supports DT.
The bindings which are being updated where intorodiced on
a per-SoC basis starting in v3.8-rc7. They may have
been internally consistent when originally added.
Simon Horman [Tue, 8 Oct 2013 00:26:53 +0000 (09:26 +0900)]
Merge tag 'renesas-smp-for-v3.13' into soc2-base
Renesas ARM based SoC SMP updates for v3.13
* Add CPU notifier based SCU boot vector code
- Use on emev2, r8a7779 and sh73a0 SoCs
- Remove now unused shmobile_smp_scu_boot_secondary()
* Add shared APMU SMP support code
- Use to add SMP support for r8a7790 SoC
* Introduce shmobile_boot_size
* Expose shmobile_invalidate_start()
* Introduce shmobile_smp_cpu_disable()
- Use on sh73a0 SoC
- Remove now unused shmobile_smp_init_cpus()
Stephen Warren [Mon, 7 Oct 2013 17:11:42 +0000 (11:11 -0600)]
ARM: tegra: fix ARCH_TEGRA_114_SOC select sort order
All the other select statements are alphabetically sorted. Fix the one
remaining escape.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Olof Johansson [Mon, 7 Oct 2013 18:29:02 +0000 (11:29 -0700)]
Merge tag 'renesas-smp-for-v3.13' of git://git./linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Renesas ARM based SoC SMP updates for v3.13
* Add CPU notifier based SCU boot vector code
- Use on emev2, r8a7779 and sh73a0 SoCs
- Remove now unused shmobile_smp_scu_boot_secondary()
* Add shared APMU SMP support code
- Use to add SMP support for r8a7790 SoC
* Introduce shmobile_boot_size
* Expose shmobile_invalidate_start()
* Introduce shmobile_smp_cpu_disable()
- Use on sh73a0 SoC
- Remove now unused shmobile_smp_init_cpus()
* tag 'renesas-smp-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Include CA7 cores in APMU table
ARM: shmobile: Extend APMU code to allow single cluster only
ARM: shmobile: Remove shmobile_smp_scu_boot_secondary()
ARM: shmobile: Let r8a7779 rely on SCU CPU notifier
ARM: shmobile: Let EMEV2 rely on SCU CPU notifier
ARM: shmobile: Let sh73a0 rely on SCU CPU notifier
ARM: shmobile: Add CPU notifier based SCU boot vector code
ARM: shmobile: Add r8a7790 SMP support using APMU code
ARM: shmobile: Shared APMU SMP support code without DT
ARM: shmobile: Introduce shmobile_boot_size
ARM: shmobile: Expose shmobile_invalidate_start()
ARM: shmobile: Remove unused shmobile_smp_init_cpus()
ARM: shmobile: Use shmobile_smp_cpu_disable() on sh73a0
ARM: shmobile: Introduce shmobile_smp_cpu_disable()
ARM: shmobile: r8a7790: Constify platform data and resources
ARM: shmobile: Rename to r8a7790_init_early()
ARM: shmobile: Rename to r8a73a4_init_early()
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Mon, 7 Oct 2013 18:20:13 +0000 (11:20 -0700)]
Merge tag 'renesas-soc-for-v3.13' of git://git./linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Renesas ARM based SoC updates for v3.13
* Add support for r8a7791 SoC
* Rename DU device in clock lookups list of r8a7779 SoC
* USB and SSI/SRU clock support for r8a7778 SoC
* USB phy power control function support for r8a7778 SoC
* tag 'renesas-soc-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7778: add usb phy power control function
ARM: shmobile: r8a7778: add USBHS clock
ARM: shmobile: r8a7791 CMT support
ARM: shmobile: r8a7791 SCIF support
ARM: shmobile: Initial r8a7791 SoC support
ARM: shmobile: r8a7778: add SSI/SRU clock support
ARM: shmobile: r8a7790: Add DU and LVDS clocks
ARM: shmobile: r8a7779: Rename DU device in clock lookups list
Signed-off-by: Olof Johansson <olof@lixom.net>
Michael Opdenacker [Sat, 7 Sep 2013 07:07:13 +0000 (09:07 +0200)]
ARM: davinci: remove deprecated IRQF_DISABLED
This patch proposes to remove the IRQF_DISABLED flag from Davinci code ;)
It's a NOOP since 2.6.35, and will be removed one day
Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Linus Torvalds [Sun, 6 Oct 2013 21:00:20 +0000 (14:00 -0700)]
Linux 3.12-rc4
Eric W. Biederman [Sat, 5 Oct 2013 20:15:30 +0000 (13:15 -0700)]
net: Update the sysctl permissions handler to test effective uid/gid
Modify the code to use current_euid(), and in_egroup_p, as in done
in fs/proc/proc_sysctl.c:test_perm()
Cc: stable@vger.kernel.org
Reviewed-by: Eric Sandeen <sandeen@redhat.com>
Reported-by: Eric Sandeen <sandeen@redhat.com>
Signed-off-by: "Eric W. Biederman" <ebiederm@xmission.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Linus Torvalds [Sun, 6 Oct 2013 20:38:31 +0000 (13:38 -0700)]
Merge git://git./linux/kernel/git/nab/target-pending
Pull SCSI target fixes from Nicholas Bellinger:
"Here are the outstanding target fixes queued up for v3.12-rc4 code.
The highlights include:
- Make vhost/scsi tag percpu_ida_alloc() use GFP_ATOMIC
- Allow sess_cmd_map allocation failure fallback to use vzalloc
- Fix COMPARE_AND_WRITE se_cmd->data_length bug with FILEIO backends
- Fixes for COMPARE_AND_WRITE callback recursive failure OOPs + non
zero scsi_status bug
- Make iscsi-target do acknowledgement tag release from RX context
- Setup iscsi-target with extra (cmdsn_depth / 2) percpu_ida tags
Also included is a iscsi-target patch CC'ed for v3.10+ that avoids
legacy wait_for_task=true release during fast-past StatSN
acknowledgement, and two other SRP target related patches that address
long-standing issues that are CC'ed for v3.3+.
Extra thanks to Thomas Glanzmann for his testing feedback with
COMPARE_AND_WRITE + EXTENDED_COPY VAAI logic"
* git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending:
iscsi-target; Allow an extra tag_num / 2 number of percpu_ida tags
iscsi-target: Perform release of acknowledged tags from RX context
iscsi-target: Only perform wait_for_tasks when performing shutdown
target: Fail on non zero scsi_status in compare_and_write_callback
target: Fix recursive COMPARE_AND_WRITE callback failure
target: Reset data_length for COMPARE_AND_WRITE to NoLB * block_size
ib_srpt: always set response for task management
target: Fall back to vzalloc upon ->sess_cmd_map kzalloc failure
vhost/scsi: Use GFP_ATOMIC with percpu_ida_alloc for obtaining tag
ib_srpt: Destroy cm_id before destroying QP.
target: Fix xop->dbl assignment in target_xcopy_parse_segdesc_02
Linus Torvalds [Sun, 6 Oct 2013 20:35:15 +0000 (13:35 -0700)]
Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dma
Pull slave-dmaengine fixes from Vinod Koul:
"Here is the slave dmanegine fixes. We have the fix for deadlock issue
on imx-dma by Michael and Josh's edma config fix along with author
change"
* 'fixes' of git://git.infradead.org/users/vkoul/slave-dma:
dmaengine: imx-dma: fix callback path in tasklet
dmaengine: imx-dma: fix lockdep issue between irqhandler and tasklet
dmaengine: imx-dma: fix slow path issue in prep_dma_cyclic
dma/Kconfig: Make TI_EDMA select TI_PRIV_EDMA
edma: Update author email address