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Sanjay Patel [Sun, 25 Mar 2018 21:16:33 +0000 (21:16 +0000)]
[PatternMatch] allow undef elements when matching vector FP +0.0
This continues the FP constant pattern matching improvements from:
https://reviews.llvm.org/rL327627
https://reviews.llvm.org/rL327339
https://reviews.llvm.org/rL327307
Several integer constant matchers also have this ability. I'm
separating matching of integer/pointer null from FP positive zero
and renaming/commenting to make the functionality clearer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328461
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Simon Pilgrim [Sun, 25 Mar 2018 20:16:53 +0000 (20:16 +0000)]
[X86] Use WriteResPair for WriteIDiv to cleanup sched defs. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328460
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Simon Pilgrim [Sun, 25 Mar 2018 19:20:08 +0000 (19:20 +0000)]
[SchedModel] Remove instregex entries that don't match any instructions
This patch throws a fatal error if an instregex entry doesn't actually match any instructions. This is part of the work to reduce the compile time impact of increased instregex usage (PR35955), although the x86 models seem to be relatively clean.
All the cases I encountered have now been fixed in trunk and this will ensure they don't get reintroduced.
Differential Revision: https://reviews.llvm.org/D44687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328459
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Simon Pilgrim [Sun, 25 Mar 2018 19:17:17 +0000 (19:17 +0000)]
[X86][SkylakeClient] Fix missing comma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328458
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Simon Pilgrim [Sun, 25 Mar 2018 19:07:17 +0000 (19:07 +0000)]
[ARM] Remove sched model instregex entries that don't match any instructions (D44687)
Reviewed by @javed.absar
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328457
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Simon Pilgrim [Sun, 25 Mar 2018 18:49:48 +0000 (18:49 +0000)]
[X86] Add missing full stop to comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328456
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Sanjay Patel [Sun, 25 Mar 2018 17:48:20 +0000 (17:48 +0000)]
[InstSimplify, InstCombine] add/update tests with FP +0.0 vector with undef; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328455
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Craig Topper [Sun, 25 Mar 2018 17:33:14 +0000 (17:33 +0000)]
[X86][SkylakeClient] Fix a set of regular expressions that were checking for optionally starting with 'Y' instead of 'V'
These bad regexs were introduced by r328435
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328454
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Simon Pilgrim [Sun, 25 Mar 2018 17:28:06 +0000 (17:28 +0000)]
[X86][MMX] MOVQ2DQ/MOVDQ2Q are better described as WriteVecMove than WriteMove
Not that it makes a difference to current cost values, but will when we try to better model GPR-SIMD transfer costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328453
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Simon Pilgrim [Sun, 25 Mar 2018 17:25:37 +0000 (17:25 +0000)]
[X86][SkylakeServer] Merge multiple instregex. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328452
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Craig Topper [Sun, 25 Mar 2018 15:58:12 +0000 (15:58 +0000)]
[X86] Update cost model for Goldmont. Add fsqrt costs for Silvermont
Add fdiv costs for Goldmont using table 16-17 of the Intel Optimization Manual. Also add overrides for FSQRT for Goldmont and Silvermont.
Reviewers: RKSimon
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44644
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328451
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Sanjay Patel [Sun, 25 Mar 2018 14:24:32 +0000 (14:24 +0000)]
[InstCombine] adjust test comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328450
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Sanjay Patel [Sun, 25 Mar 2018 14:19:25 +0000 (14:19 +0000)]
[InstCombine] consolidate casted icmp vector tests
We have thorough coverage of predicates and scalar types,
so we just need a sampling of vector tests to show that
things are working or not with vectors types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328449
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Sanjay Patel [Sun, 25 Mar 2018 14:01:42 +0000 (14:01 +0000)]
[InstCombine] peek through more icmp of FP cast + bitcast
This is an extension of rL328426 as noted in D44367.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328448
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Simon Pilgrim [Sun, 25 Mar 2018 10:21:19 +0000 (10:21 +0000)]
[X86] Add the ability to override memory folding latency to schedules and add 1uop for memory folds for Intel models
The Intel models need an extra 1uop for memory folded instructions, plus a lot of instructions take a non-default memory latency which should allow us to use the multiclass a lot more to tidy things up.
Differential Revision: https://reviews.llvm.org/D44840
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328446
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Craig Topper [Sun, 25 Mar 2018 01:28:43 +0000 (01:28 +0000)]
[X86] Consistently prefix all defs in X86ScheduleSLM.td with 'SLM'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328444
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Martin Storsjo [Sat, 24 Mar 2018 23:00:00 +0000 (23:00 +0000)]
[X86] Update a partially stale comment, since SVN r328386. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328443
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Craig Topper [Sat, 24 Mar 2018 22:58:03 +0000 (22:58 +0000)]
[SchedModel] Remove an unneeded temporary vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328442
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Craig Topper [Sat, 24 Mar 2018 22:58:02 +0000 (22:58 +0000)]
[SchedModel] Use std::move in a couple places to reduce copying
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328441
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Craig Topper [Sat, 24 Mar 2018 22:58:00 +0000 (22:58 +0000)]
[SchedModel] Use std::move to replace a vector instead of vector::swap
We don't really care about the old vector value so we don't care to swap it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328440
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Eric Fiselier [Sat, 24 Mar 2018 22:14:02 +0000 (22:14 +0000)]
Fix module.modulemap after r328395
This patch removes the MachineValueType module since the
header was removed in r328395.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328439
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Craig Topper [Sat, 24 Mar 2018 21:57:35 +0000 (21:57 +0000)]
[SchedModel] Remove std::vectors that were created with 1 element and then passed to an ArrayRef parameter.
ArrayRef can capture a single element. We don't need a vector for that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328438
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Simon Pilgrim [Sat, 24 Mar 2018 21:22:32 +0000 (21:22 +0000)]
[SchedModel] Record::getName() returns StringRef - avoid std::string creation. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328437
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Simon Pilgrim [Sat, 24 Mar 2018 21:04:20 +0000 (21:04 +0000)]
[SchedModel] Avoid std::string creation for instregex patterns that don't contain regex metas. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328436
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Simon Pilgrim [Sat, 24 Mar 2018 20:40:14 +0000 (20:40 +0000)]
[X86][SkylakeClient] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328435
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Simon Pilgrim [Sat, 24 Mar 2018 19:37:28 +0000 (19:37 +0000)]
[X86][Broadwell] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328434
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Mandeep Singh Grang [Sat, 24 Mar 2018 18:37:19 +0000 (18:37 +0000)]
[RISCV] Use init_array instead of ctors for RISCV target, by default
Summary:
LLVM defaults to the newer .init_array/.fini_array scheme for static
constructors rather than the less desirable .ctors/.dtors (the UseCtors
flag defaults to false). This wasn't being respected in the RISC-V
backend because it fails to call TargetLoweringObjectFileELF::InitializeELF with the the appropriate
flag for UseInitArray.
This patch fixes this by implementing RISCVELFTargetObjectFile and overriding its Initialize method to call
InitializeELF(TM.Options.UseInitArray).
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: mgorny, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, llvm-commits
Differential Revision: https://reviews.llvm.org/D44750
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328433
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Simon Pilgrim [Sat, 24 Mar 2018 18:36:01 +0000 (18:36 +0000)]
[X86][Haswell] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328432
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Simon Pilgrim [Sat, 24 Mar 2018 18:12:59 +0000 (18:12 +0000)]
[X86][SandyBridge] Merge xmm/ymm instructions instregex entries to reduce regex matches to reduce compile time
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328431
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Mandeep Singh Grang [Sat, 24 Mar 2018 17:34:37 +0000 (17:34 +0000)]
[Hexagon] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches.
Reviewers: kparzysz
Reviewed By: kparzysz
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44857
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328430
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Mandeep Singh Grang [Sat, 24 Mar 2018 17:15:04 +0000 (17:15 +0000)]
[AMDGPU] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Reviewers: tstellar, RKSimon, arsenm
Reviewed By: arsenm
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44856
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328429
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Andrea Di Biagio [Sat, 24 Mar 2018 16:05:36 +0000 (16:05 +0000)]
[llvm-mca] run clang-format on all files.
This also addresses Simon's review comment in D44839.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328428
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Andrea Di Biagio [Sat, 24 Mar 2018 15:48:25 +0000 (15:48 +0000)]
[llvm-mca] Remove unused field in InstrBuilder. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328427
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Sanjay Patel [Sat, 24 Mar 2018 15:45:02 +0000 (15:45 +0000)]
[InstCombine] peek through FP casts for sign-bit compares (PR36682)
This pattern came up in PR36682:
https://bugs.llvm.org/show_bug.cgi?id=36682
https://godbolt.org/g/LhuD9A
Equality checks are planned as a follow-up enhancement.
Differential Revision: https://reviews.llvm.org/D44367
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328426
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Sanjay Patel [Sat, 24 Mar 2018 15:41:59 +0000 (15:41 +0000)]
[InstCombine] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328425
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Simon Pilgrim [Sat, 24 Mar 2018 15:05:12 +0000 (15:05 +0000)]
[X86][AES] Ensure we're testing both non-VEX/VEX variants of AES instructions on AVX targets
Add skylake server tests as well
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328424
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Simon Pilgrim [Sat, 24 Mar 2018 14:51:52 +0000 (14:51 +0000)]
[X86][SSE] Ensure we're testing both non-VEX/VEX variants of SSE instructions on AVX targets
And ensure we don't use later instruction sets in SSE schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328423
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Sanjay Patel [Sat, 24 Mar 2018 14:45:41 +0000 (14:45 +0000)]
[InstCombine] add multi-use/vector tests for intrinsic shrinking; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328422
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Simon Pilgrim [Sat, 24 Mar 2018 13:47:48 +0000 (13:47 +0000)]
[X86][AVX1] Ensure we don't use later instruction sets in AVX1 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328421
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Simon Pilgrim [Sat, 24 Mar 2018 13:47:01 +0000 (13:47 +0000)]
[X86][AVX2] Ensure we don't use later instruction sets in AVX2 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328420
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Craig Topper [Sat, 24 Mar 2018 07:48:54 +0000 (07:48 +0000)]
[X86] Add a new disassembler opcode map for 3DNow. Stop treating 3DNow as an attribute.
This reduces the size of llvm-mc by at least 150k since we no longer have to multiply the attribute across 7 tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328416
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Craig Topper [Sat, 24 Mar 2018 07:15:47 +0000 (07:15 +0000)]
[X86] Use unique_ptr to simplify memory management. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328413
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Craig Topper [Sat, 24 Mar 2018 07:15:46 +0000 (07:15 +0000)]
[X86] Use X86_INSTR_MRM_MAPPING macro instead of listing all MRM_C0-MRM_FF format encodings. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328412
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Craig Topper [Sat, 24 Mar 2018 07:15:45 +0000 (07:15 +0000)]
[X86] Remove an unnecessary switch around two other switches. NFC
The outer switch only had one valid block so didn't provide any value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328411
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Craig Topper [Sat, 24 Mar 2018 06:04:12 +0000 (06:04 +0000)]
[X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap encoding. NFC
The 3DNow instructions are encoded a little weird, but we can still represent it as an opcode map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328410
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Eric Christopher [Sat, 24 Mar 2018 02:56:58 +0000 (02:56 +0000)]
Add REQUIRES lines for the targets being checked in this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328408
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Craig Topper [Sat, 24 Mar 2018 01:52:01 +0000 (01:52 +0000)]
[X86] Add a DAG combine to simplify PMULDQ/PMULUDQ nodes
These nodes only use the lower 32 bits of their inputs so we can use SimplifyDemandedBits to simplify them.
Differential Revision: https://reviews.llvm.org/D44375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328405
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Eric Christopher [Sat, 24 Mar 2018 00:07:38 +0000 (00:07 +0000)]
Allow FDE references outside the +/-2GB range supported by PC relative
offsets for code models other than small/medium. For JIT application,
memory layout is less controlled and can result in truncations
otherwise.
Patch based on one by Olexa Bilaniuk!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328400
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David Blaikie [Sat, 24 Mar 2018 00:06:14 +0000 (00:06 +0000)]
Remove unused header from EntryExitInstrumenter
Fixes layering, since Transforms/Utils doesn't depend on CodeGen, so
shouldn't include headers from it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328399
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Craig Topper [Sat, 24 Mar 2018 00:02:46 +0000 (00:02 +0000)]
[X86] Correct the value AdSizeX in X86II enum. NFC
Should be NFC since nothing used the enum value. The instruction descriptions are generated from tablegen which had the correct value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328398
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David Blaikie [Fri, 23 Mar 2018 23:58:31 +0000 (23:58 +0000)]
Fix layering by moving ValueTypes.h from CodeGen to IR
ValueTypes.h is implemented in IR already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328397
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David Blaikie [Fri, 23 Mar 2018 23:58:27 +0000 (23:58 +0000)]
Fix layering of CodeGen/TargetOpcodes.def by moving it to Support
It's also used by utils/TableGen so needs to reside somewhere common to
TableGen and CodeGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328396
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David Blaikie [Fri, 23 Mar 2018 23:58:25 +0000 (23:58 +0000)]
Fix layering of MachineValueType.h by moving it from CodeGen to Support
This is used by llvm tblgen as well as by LLVM Targets, so the only
common place is Support for now. (maybe we need another target for these
sorts of things - but for now I'm at least making them correct & we can
make them better if/when people have strong feelings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328395
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David Blaikie [Fri, 23 Mar 2018 23:58:21 +0000 (23:58 +0000)]
Fix layering by moving Support/CodeGenCWrappers.h to Target
This includes llvm-c/TargetMachine.h which is logically part of
libTarget (since libTarget implements llvm-c/TargetMachine.h's
functions).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328394
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David Blaikie [Fri, 23 Mar 2018 23:58:20 +0000 (23:58 +0000)]
Fix layering by moving X86DisassemblerDecoderCommon to Support
This is used from llvm tblgen and the X86Disassembler - the only common
library (apart from TableGen, which probably doesn't make sense to have
as a dependency from a release tool (rather than a use-while-building-llvm
tool) of LLVM)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328393
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David Blaikie [Fri, 23 Mar 2018 23:58:19 +0000 (23:58 +0000)]
Move TargetLoweringObjectFile from CodeGen to Target to fix layering
It's implemented in Target & include from other Target headers, so the
header should be in Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328392
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Philip Reames [Fri, 23 Mar 2018 23:41:47 +0000 (23:41 +0000)]
[GuardWidening] Group code by class [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328387
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Reid Kleckner [Fri, 23 Mar 2018 23:38:53 +0000 (23:38 +0000)]
[X86] Fix Windows `i1 zeroext` conventions to use i8 instead of i32
Both GCC and MSVC only look at the low byte of a boolean when it is
passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328386
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David Blaikie [Fri, 23 Mar 2018 22:11:06 +0000 (22:11 +0000)]
Fix Layering, move instrumentation transform headers into Instrumentation subdirectory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328379
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Fedor Sergeev [Fri, 23 Mar 2018 21:46:16 +0000 (21:46 +0000)]
[PM][FunctionAttrs] add NoUnwind attribute inference to PostOrderFunctionAttrs pass
Summary:
This was motivated by absence of PrunEH functionality in new PM.
It was decided that a proper way to do PruneEH is to add NoUnwind inference
into PostOrderFunctionAttrs and then perform normal SimplifyCFG on top.
This change generalizes attribute handling implemented for (a removal of)
Convergent attribute, by introducing a generic builder-like class
AttributeInferer
It registers all the attribute inference requests, storing per-attribute
predicates into a vector, and then goes through an SCC Node, scanning all
the instructions for not breaking attribute assumptions.
The main idea is that as soon all the instructions from all the functions
of SCC Node conform to attribute assumptions then we are free to infer
the attribute as set for all the functions of SCC Node.
It handles two distinct cases of attributes:
- those that might break due to derefinement of the function code
for these attributes we are allowed to apply inference only if all the
functions are "exact definitions". Example - NoUnwind.
- those that do not care about derefinement
for these attributes we are allowed to apply inference as soon as we see
any function definition. Example - removal of Convergent attribute.
Also in this commit:
* Converted all the FunctionAttrs tests to use FileCheck and added new-PM
invocations to them
* FunctionAttrs/convergent.ll test demonstrates a difference in behavior between
new and old PM implementations. Marked with FIXME.
* PruneEH tests were converted to new-PM as well, using function-attrs+simplify-cfg
combo as intended
* some of "other" tests were updated since function-attrs now infers 'nounwind'
even for old PM pipeline
* -disable-nounwind-inference hidden option added as a possible workaround for a supposedly
rare case when nounwind being inferred by default presents a problem
Reviewers: chandlerc, jlebar
Reviewed By: jlebar
Subscribers: eraman, llvm-commits
Differential Revision: https://reviews.llvm.org/D44415
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328377
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Sanjay Patel [Fri, 23 Mar 2018 21:18:12 +0000 (21:18 +0000)]
[InstCombine] simplify code for FP intrinsic shrinking; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328372
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Sanjay Patel [Fri, 23 Mar 2018 21:13:53 +0000 (21:13 +0000)]
[InstCombine] increase test coverage for intrinsic shrinking; NFC
There were no tests with vector types before this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328371
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Krzysztof Parzyszek [Fri, 23 Mar 2018 20:43:02 +0000 (20:43 +0000)]
[Hexagon] Make findLoopInstr member of HexagonInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328367
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Krzysztof Parzyszek [Fri, 23 Mar 2018 20:41:44 +0000 (20:41 +0000)]
[Hexagon] Correct update of instruction offet in HW loop fixup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328366
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Krzysztof Parzyszek [Fri, 23 Mar 2018 20:11:00 +0000 (20:11 +0000)]
[Hexagon] Boost profit for word-mask immediates, reduce for others
This avoids unnecessary splitting due to uninteresting immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328364
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Zachary Turner [Fri, 23 Mar 2018 19:57:25 +0000 (19:57 +0000)]
[PDB] Resubmit "Support embedding natvis files in PDBs."
This was reverted several times due to what ultimately turned out
to be incompatibilities in our serialized hash table format.
Several changes went in prior to this to fix those issues since
they were more fundamental and independent of supporting injected
sources, so now that those are fixed this change should hopefully
pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328363
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Krzysztof Parzyszek [Fri, 23 Mar 2018 19:47:13 +0000 (19:47 +0000)]
[Hexagon] Assume all extendable branches to be of size 8 in relaxation
The branch relaxation pass collects sizes of all instructions at the
beginning, before any changes have been made. It then performs one pass
over all branches to see which ones need to be extended. It does not
account for the case when a previously valid branch becomes out-of-range
due to relaxing other branches.
This approach fixes this problem by assuming from the beginning that
all extendable branches have been extended. This may cause unneeded
relaxation in some cases, but avoids iteration and recomputing instruction
sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328360
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Andrea Di Biagio [Fri, 23 Mar 2018 19:40:04 +0000 (19:40 +0000)]
[llvm-mca] Split the InstructionInfoView from the SummaryView.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328358
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Krzysztof Parzyszek [Fri, 23 Mar 2018 19:39:37 +0000 (19:39 +0000)]
[Hexagon] Incorrectly removing dead flag and adding kill flag
The HexagonExpandCondsets pass is incorrectly removing the dead
flag on a definition that is really dead, and adding a kill flag
to a use that is tied to a definition. This causes an assert later
during the machine scheduler when querying the live interval
information.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328357
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Benjamin Kramer [Fri, 23 Mar 2018 19:39:16 +0000 (19:39 +0000)]
[Hexagon] Silence unused variable warning in Release builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328356
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Krzysztof Parzyszek [Fri, 23 Mar 2018 19:30:34 +0000 (19:30 +0000)]
[Hexagon] Fold offset in base+immediate loads/stores
Optimize Ry = add(Rx,#n); memw(Ry+#0) = Rz => memw(Rx,#n) = Rz.
Patch by Jyotsna Verma.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328355
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Craig Topper [Fri, 23 Mar 2018 19:15:05 +0000 (19:15 +0000)]
[X86] Add itinerary to RCPSS*_Int and similar instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328353
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Craig Topper [Fri, 23 Mar 2018 19:15:03 +0000 (19:15 +0000)]
[X86] Add itineraries to ADD.*_DB instructions to match their normal counterparts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328352
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Tony Tye [Fri, 23 Mar 2018 18:58:47 +0000 (18:58 +0000)]
[AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU
Add two additional implicit arguments for OpenCL for the AMDGPU target using the AMDHSA runtime to support device enqueue.
Differential Revision: https://reviews.llvm.org/D44697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328351
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Tony Tye [Fri, 23 Mar 2018 18:45:18 +0000 (18:45 +0000)]
[AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
- Remove use of the opencl and amdopencl environment member of the target triple for the AMDGPU target.
- Use function attribute to communicate to the AMDGPU backend to add implicit arguments for OpenCL kernels for the AMDHSA OS.
Differential Revision: https://reviews.llvm.org/D43736
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328349
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Zachary Turner [Fri, 23 Mar 2018 18:43:39 +0000 (18:43 +0000)]
[PDB] Make our PDBs look more like MS PDBs.
When investigating bugs in PDB generation, the first step is
often to do the same link with link.exe and then compare PDBs.
But comparing PDBs is hard because two completely different byte
sequences can both be correct, so it hampers the investigation when
you also have to spend time figuring out not just which bytes are
different, but also if the difference is meaningful.
This patch fixes a couple of cases related to string table emission,
hash table emission, and the order in which we emit strings that
makes more of our bytes the same as the bytes generated by MS PDBs.
Differential Revision: https://reviews.llvm.org/D44810
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328348
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Krzysztof Parzyszek [Fri, 23 Mar 2018 18:43:09 +0000 (18:43 +0000)]
[Hexagon] Always generate mux out of predicated transfers if possible
HexagonGenMux would collapse pairs of predicated transfers if it assumed
that the predicated .new forms cannot be created. Turns out that generating
mux is preferable in almost all cases.
Introduce an option -hexagon-gen-mux-threshold that controls the minimum
distance between the instruction defining the predicate and the later of
the two transfers. If the distance is closer than the threshold, mux will
not be generated. Set the threshold to 0 by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328346
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Jordan Rose [Fri, 23 Mar 2018 18:05:19 +0000 (18:05 +0000)]
Delete the copy constructor for llvm::yaml::Node
The nodes keep a reference back to the original document, but the
document is streamed, not read all into memory at once, and the
position is part of the state. If nodes are ever copied, the document
position can end up being advanced more than once.
This did not reveal any problems in LLVM or Clang but caught a handful
over in Swift!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328345
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Krzysztof Parzyszek [Fri, 23 Mar 2018 18:00:18 +0000 (18:00 +0000)]
[Hexagon] Avoid early if-conversion for one sided branches
Patch by Anand Kodnani.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328344
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Simon Pilgrim [Fri, 23 Mar 2018 17:59:22 +0000 (17:59 +0000)]
[X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX on ymms) function unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328343
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Alex Shlyapnikov [Fri, 23 Mar 2018 17:57:54 +0000 (17:57 +0000)]
[HWASan] Port HWASan to Linux x86-64 (LLVM)
Summary:
Porting HWASan to Linux x86-64, first of the three patches, LLVM part.
The approach is similar to ARM case, trap signal is used to communicate
memory tag check failure. int3 instruction is used to generate a signal,
access parameters are stored in nop [eax + offset] instruction immediately
following the int3 one.
One notable difference is that x86-64 has to untag the pointer before use
due to the lack of feature comparable to ARM's TBI (Top Byte Ignore).
Reviewers: eugenis
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D44699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328342
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Ana Pazos [Fri, 23 Mar 2018 17:53:27 +0000 (17:53 +0000)]
[ARM] Fix "Constant pool entry out of range!" in Thumb1 mode
This patch fixes PR36658, "Constant pool entry out of range!" in Thumb1 mode.
In ARMConstantIslands::optimizeThumb2JumpTables() in Thumb1 mode,
adjustBBOffsetsAfter() is not calculating postOffset correctly by
properly accounting for the padding that is required for the constant pool
that immediately follows the jump table branch instruction.
Reviewers: t.p.northover, eli.friedman
Reviewed By: t.p.northover
Subscribers: chrib, tstellar, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D44709
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328341
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Andrea Di Biagio [Fri, 23 Mar 2018 17:53:02 +0000 (17:53 +0000)]
[llvm-mca] update the ResourcePressureView after r328335. NFC.
This should have been part of r328335. I forgot to svn add these files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328340
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Krzysztof Parzyszek [Fri, 23 Mar 2018 17:46:09 +0000 (17:46 +0000)]
[Hexagon] Two fixes in early if-conversion
- Fix checking for vector predicate registers.
- Avoid speculating llvm.lifetime.end intrinsic.
Patch by Harsha Jagasia and Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328339
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Simon Pilgrim [Fri, 23 Mar 2018 17:38:59 +0000 (17:38 +0000)]
[X86][Btver2] Cleanup MOVMSK instructions to use JFPA function unit
Add missing non-VEX and (V)PMOVMSKB instructions to the pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328338
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Andrew Kaylor [Fri, 23 Mar 2018 17:36:18 +0000 (17:36 +0000)]
Fix a block copying problem in LICM
Differential Revision: https://reviews.llvm.org/D44817
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328336
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Andrea Di Biagio [Fri, 23 Mar 2018 17:36:07 +0000 (17:36 +0000)]
[llvm-mca] Make the resource cost a double.
This is done in preparation for the fix for PR36874.
The number of cycles consumed for each pipe is now a double quantity. This
allows reuse of the resource pressure view to print out instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328335
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Fangrui Song [Fri, 23 Mar 2018 17:26:12 +0000 (17:26 +0000)]
[ADT] Simplify getMemory. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328334
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Krzysztof Parzyszek [Fri, 23 Mar 2018 17:22:55 +0000 (17:22 +0000)]
[Hexagon] Copy subregisters in HexagonStoreWiden
When converting an instruction to the wider version, copy any
subregisters if the original operand has a subregister.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328333
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Simon Pilgrim [Fri, 23 Mar 2018 16:17:56 +0000 (16:17 +0000)]
[X86][Btver2] Vector permutes use a JFPU01 scheduler pipe and JFPX/JVALU function unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328331
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Sanjay Patel [Fri, 23 Mar 2018 15:39:03 +0000 (15:39 +0000)]
[InstCombine] auto-generate checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328329
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Simon Pilgrim [Fri, 23 Mar 2018 15:35:13 +0000 (15:35 +0000)]
[X86][Btver2] Vector store instructions use a JFPU1 scheduler pipe and JSAGU/JSTC function units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328328
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Sanjay Patel [Fri, 23 Mar 2018 15:31:31 +0000 (15:31 +0000)]
[InstSimplify] regenerate checks, move tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328327
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Zaara Syeda [Fri, 23 Mar 2018 15:28:15 +0000 (15:28 +0000)]
Re-commit: [MachineLICM] Add functions to MachineLICM to hoist invariant stores
This patch adds functions to allow MachineLICM to hoist invariant stores.
Currently, MachineLICM does not hoist any store instructions, however
when storing the same value to a constant spot on the stack, the store
instruction should be considered invariant and be hoisted. The function
isInvariantStore iterates each operand of the store instruction and checks
that each register operand satisfies isCallerPreservedPhysReg. The store
may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore.
This patch also adds the PowerPC changes needed to consider the stack
register as caller preserved.
Differential Revision: https://reviews.llvm.org/D40196
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328326
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Sanjay Patel [Fri, 23 Mar 2018 15:19:35 +0000 (15:19 +0000)]
[InstCombine] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328325
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Simon Pilgrim [Fri, 23 Mar 2018 15:17:50 +0000 (15:17 +0000)]
[X86][Btver2] Cleanup DPPS/DPPD instructions to use JFPA/JFPM function units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328324
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Sanjay Patel [Fri, 23 Mar 2018 15:07:35 +0000 (15:07 +0000)]
[InstCombine] reduce code duplication; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328323
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Sanjay Patel [Fri, 23 Mar 2018 14:48:31 +0000 (14:48 +0000)]
[InstCombine] improve variable name; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328322
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John Brawn [Fri, 23 Mar 2018 14:47:07 +0000 (14:47 +0000)]
[AArch64] Don't reduce the width of loads if it prevents combining a shift
Loads and stores can only shift the offset register by the size of the value
being loaded, but currently the DAGCombiner will reduce the width of the load
if it's followed by a trunc making it impossible to later combine the shift.
Solve this by implementing shouldReduceLoadWidth for the AArch64 backend and
make it prevent the width reduction if this is what would happen, though do
allow it if reducing the load width will let us eliminate a later sign or zero
extend.
Differential Revision: https://reviews.llvm.org/D44794
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328321
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Simon Pilgrim [Fri, 23 Mar 2018 14:45:03 +0000 (14:45 +0000)]
[X86][Btver2] Fix MicroOps counts for DPPS/YMM memory folded instructions
This was due to a misunderstanding over what llvm calls a micro-op (retirement unit) is actually called a macro-op on the AMD/Jaguar target. Folded loads don't affect num macro ops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328320
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