OSDN Git Service
Kevin Enderby [Thu, 18 Dec 2014 00:53:40 +0000 (00:53 +0000)]
Add printing the LC_LINKER_OPTION load command with llvm-objdump’s -private-headers.
Also corrected the name of the load command to not end in an ’S’ as well as corrected
the name of the MachO::linker_option_command struct and other places that had the
word option as plural which did not match the Mac OS X headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224485
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Thu, 18 Dec 2014 00:46:16 +0000 (00:46 +0000)]
IR: Handle self-referencing DICompositeTypes in DIBuilder
Add API to DIBuilder to handle self-referencing `DICompositeType`s.
Self-references aren't expected in the debug info graph, and we take
advantage of that by only calling `resolveCycles()` on nodes that were
once forward declarations (otherwise, DIBuilder needs an expensive
tracking reference to every unresolved node it creates, which in cyclic
graphs is *all of them*).
However, clang seems to create self-referencing `DICompositeType`s. Add
API to manage this safely. The paired commit to clang will include the
regression test.
I'll make the `DICompositeType` API `private` in a follow-up to prevent
misuse (I've separated that to prevent build failures from missing the
clang commit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224482
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Samsonov [Thu, 18 Dec 2014 00:45:32 +0000 (00:45 +0000)]
[dsymutil] Fix missing member initializer.
This bug was found by the MSan bootstrap bot:
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/5330/steps/check-llvm%20msan/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224481
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Wed, 17 Dec 2014 22:05:42 +0000 (22:05 +0000)]
LTO: Lazy-load LTOModule in local contexts
Start lazy-loading `LTOModule`s that own their contexts. These can only
really be used for parsing symbols, so its unnecessary to ever
materialize their functions.
I looked into using `IRObjectFile::create()` and optionally calling
`materializAllPermanently()` afterwards, but this turned out to be
awkward.
- The default target triple and data layout logic needs to happen
*before* the call to `IRObjectFile::IRObjectFile()`, but after
`Module` was created.
- I tried passing a lambda in to do the module initialization, but
this seemed to require threading the error message from
`TargetRegistry::lookupTarget()` through `std::error_code`.
- I also looked at setting `errMsg` directly from within the lambda,
but this didn't look any better.
(I guess there's a reason we weren't already using that function.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224466
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Wed, 17 Dec 2014 21:50:04 +0000 (21:50 +0000)]
[sanitizer] allow -fsanitize-coverage=N w/ -fsanitize=leak, llvm part
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224463
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Wed, 17 Dec 2014 21:25:20 +0000 (21:25 +0000)]
RegisterCoalescer: Fix stripCopies() picking up main range instead of subregister range
This fixes a problem where stripCopies() would switch to values in the
main liverange when it crossed a copy instruction. However when joining
subranges we need to stay in the respective subregister ranges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224461
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Wed, 17 Dec 2014 21:04:08 +0000 (21:04 +0000)]
R600/SI: Fix f64 inline immediates
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224458
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Wed, 17 Dec 2014 20:35:11 +0000 (20:35 +0000)]
[Hexagon] Reconfiguring register alternate names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224455
91177308-0d34-0410-b5e6-
96231b3b80d8
Will Schmidt [Wed, 17 Dec 2014 19:56:29 +0000 (19:56 +0000)]
Enable the P8Model entry
This was missed last time around, for the P8 Instruction Scheduling
changes (223257). This will hook the P8Model entry in so those
changes will actually be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224452
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Wed, 17 Dec 2014 19:13:47 +0000 (19:13 +0000)]
ExecutionDepsFix: Correctly handle wide registers.
The ExecutionDepsFix previously mapped each register to 1 or zero
registers of the register class it was called with and therefore
simulating liveness for. This was problematic for cases involving wider
registers like Q0 on ARM where ExecutionDepsFix gets invoked for the Dxx
registers. In these cases the wide register would get mapped to the last
matching D register, while it should have been all matching D registers.
This commit changes the AliasMap to use a SmallVector to map registers
to potentially multiple destination regclass registers. This is required
to avoid regressions with subregister liveness tracking enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224447
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Wed, 17 Dec 2014 18:12:10 +0000 (18:12 +0000)]
Random Number Generator Refactoring (removing from Module)
This patch removes the RNG from Module. Passes should instead create a new RNG for their use as needed.
Patch by Stephen Crane @rinon.
Differential revision: http://reviews.llvm.org/D4377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224444
91177308-0d34-0410-b5e6-
96231b3b80d8
Jingyue Wu [Wed, 17 Dec 2014 17:59:04 +0000 (17:59 +0000)]
[NVPTX] Fix bugs related to isSingleValueType
Summary:
With isSingleValueType starting to treat vector types as single-value types,
code that uses this interface needs to be updated.
Test Plan:
vector-global.ll
nvcl-param-align.ll
Reviewers: jholewinski
Reviewed By: jholewinski
Subscribers: llvm-commits, meheff, eliben, jholewinski
Differential Revision: http://reviews.llvm.org/D6573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224440
91177308-0d34-0410-b5e6-
96231b3b80d8
Timur Iskhodzhanov [Wed, 17 Dec 2014 17:52:12 +0000 (17:52 +0000)]
Fix CR/LF line endings in test case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224437
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Wed, 17 Dec 2014 16:17:44 +0000 (16:17 +0000)]
ARM: correct an off-by-one in an assert
The assert was off-by-one, resulting in failures for valid input.
Thanks to Asiri Rathnayake for pointing out the failure!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224432
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Kuperstein [Wed, 17 Dec 2014 12:32:17 +0000 (12:32 +0000)]
[DAGCombine] Slightly improve lowering of BUILD_VECTOR into a shuffle.
This handles the case of a BUILD_VECTOR being constructed out of elements extracted from a vector twice the size of the result vector. Previously this was always scalarized. Now, we try to construct a shuffle node that feeds on extract_subvectors.
This fixes PR15872 and provides a partial fix for PR21711.
Differential Revision: http://reviews.llvm.org/D6678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224429
91177308-0d34-0410-b5e6-
96231b3b80d8
Vladimir Medic [Wed, 17 Dec 2014 11:49:56 +0000 (11:49 +0000)]
MipsABIInfo class is used in different libraries. Moving the files to MCTargetDesc folder(LLVMMipsDesc library) prevents linkage errors. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224427
91177308-0d34-0410-b5e6-
96231b3b80d8
Toma Tabacu [Wed, 17 Dec 2014 10:56:16 +0000 (10:56 +0000)]
[mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.
Summary:
When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives,
while GCC uses the default options if an assembly-level function contains inline assembly code.
This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example).
This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6637
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224425
91177308-0d34-0410-b5e6-
96231b3b80d8
Suyog Sarda [Wed, 17 Dec 2014 10:34:27 +0000 (10:34 +0000)]
Revert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders them for bundling into vector of loads,
and vectorizes it."
This was re-ordering floating point data types resulting in mismatch in output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224424
91177308-0d34-0410-b5e6-
96231b3b80d8
Yaron Keren [Wed, 17 Dec 2014 09:55:15 +0000 (09:55 +0000)]
Teach lit.cfg to recognize -windows-gnu in addition to -mingw32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224421
91177308-0d34-0410-b5e6-
96231b3b80d8
Elena Demikhovsky [Wed, 17 Dec 2014 08:12:59 +0000 (08:12 +0000)]
Added 5 more tests related to sink store revision 224247
- by Ella Bolshinsky
http://reviews.llvm.org/D6420
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224418
91177308-0d34-0410-b5e6-
96231b3b80d8
Erik Eckstein [Wed, 17 Dec 2014 07:29:19 +0000 (07:29 +0000)]
Strength reduce intrinsics with overflow into regular arithmetic operations if possible.
Some intrinsics, like s/uadd.with.overflow and umul.with.overflow, are already strength reduced.
This change adds other arithmetic intrinsics: s/usub.with.overflow, smul.with.overflow.
It completes the work on PR20194.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224417
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Wed, 17 Dec 2014 07:27:31 +0000 (07:27 +0000)]
Revert "Linker: Drop superseded subprograms"
This reverts commit r224389. Based on feedback from the bots, the
assertion seems to be going off *more* often, not less (previously I was
just seeing it in an internal bootstrap, now it's happening in public
builds too).
http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_build/936/
http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/5325
Reverting in order to investigate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224416
91177308-0d34-0410-b5e6-
96231b3b80d8
Justin Hibbits [Wed, 17 Dec 2014 06:23:35 +0000 (06:23 +0000)]
Add parsing of 'foo@local".
Summary:
Currently, it supports generating, but not parsing, this expression.
Test added as well.
Test Plan: New test added, no regressions due to this.
Reviewers: hfinkel
Reviewed By: hfinkel
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6672
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224415
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 17 Dec 2014 03:38:04 +0000 (03:38 +0000)]
Remove a debugging assert.
Sorry for the noise, I have no idea how it survived to the final version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224414
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 17 Dec 2014 03:07:20 +0000 (03:07 +0000)]
Remove unused includes and out of date comment. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224413
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 17 Dec 2014 02:42:20 +0000 (02:42 +0000)]
Fix the windows build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224412
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Wed, 17 Dec 2014 02:32:44 +0000 (02:32 +0000)]
Refactor and simplify the code reading /proc/cpuinfo. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224410
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Wed, 17 Dec 2014 02:18:13 +0000 (02:18 +0000)]
RegisterCoalescer: Sprinkle some const modifiers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224409
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Wed, 17 Dec 2014 02:00:38 +0000 (02:00 +0000)]
llvm-lto: Add testing coverage for local contexts
Add coverage in `llvm-lto` for the API exposed by libLTO to create
modules in local contexts.
The goal here isn't to test the symbol-related API extensively, just to
confirm that these modules work at all. (I'll be shifting code around
soon that should be NFC and I realized there was no test coverage.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224408
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Wed, 17 Dec 2014 01:56:51 +0000 (01:56 +0000)]
Delete debugging cruft that crept in with r223802.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224407
91177308-0d34-0410-b5e6-
96231b3b80d8
David Majnemer [Wed, 17 Dec 2014 01:54:33 +0000 (01:54 +0000)]
InstSimplify: shl nsw/nuw undef, %V -> undef
We can always choose an value for undef which might cause %V to shift
out an important bit except for one case, when %V is zero.
However, shl behaves like an identity function when the right hand side
is zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224405
91177308-0d34-0410-b5e6-
96231b3b80d8
Nick Lewycky [Wed, 17 Dec 2014 01:52:08 +0000 (01:52 +0000)]
Make ValueEnumerator::print use OS for metadata too. Noticed by inspection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224404
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Wed, 17 Dec 2014 01:36:17 +0000 (01:36 +0000)]
[CodeGenPrepare] Reapply r224351 with a fix for the assertion failure:
The type promotion helper does not support vector type, so when make
such it does not kick in in such cases.
Original commit message:
[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.
This patch extends the optimization in CodeGenPrepare that moves a sign/zero
extension near a load when the target can combine them. The optimization may
promote any operations between the extension and the load to make that possible.
Although this optimization may be beneficial for all targets, in particular
AArch64, this is enabled for X86 only as I have not benchmarked it for other
targets yet.
** Context **
Most targets feature extended loads, i.e., loads that perform a zero or sign
extension for free. In that context it is interesting to expose such pattern in
CodeGenPrepare so that the instruction selection pass can form such loads.
Sometimes, this pattern is blocked because of instructions between the load and
the extension. When those instructions are promotable to the extended type, we
can expose this pattern.
** Motivating Example **
Let us consider an example:
define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
%ld = load i8* %addr1
%zextld = zext i8 %ld to i32
%ld2 = load i32* %addr2
%add = add nsw i32 %ld2, %zextld
%sextadd = sext i32 %add to i64
%zexta = zext i8 %a to i32
%addza = add nsw i32 %zexta, %zextld
%sextaddza = sext i32 %addza to i64
%addb = add nsw i32 %b, %zextld
%sextaddb = sext i32 %addb to i64
call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
ret void
}
As it is, this IR generates the following assembly on x86_64:
[...]
movzbl (%rdi), %eax # zero-extended load
movl (%rsi), %es # plain load
addl %eax, %esi # 32-bit add
movslq %esi, %rdi # sign extend the result of add
movzbl %dl, %edx # zero extend the first argument
addl %eax, %edx # 32-bit add
movslq %edx, %rsi # sign extend the result of add
addl %eax, %ecx # 32-bit add
movslq %ecx, %rdx # sign extend the result of add
[...]
The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.
Now, by promoting the additions to form more extended loads we would generate:
[...]
movzbl (%rdi), %eax # zero-extended load
movslq (%rsi), %rdi # sign-extended load
addq %rax, %rdi # 64-bit add
movzbl %dl, %esi # zero extend the first argument
addq %rax, %rsi # 64-bit add
movslq %ecx, %rdx # sign extend the second argument
addq %rax, %rdx # 64-bit add
[...]
The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.
This kind of sequences happen a lot on code using 32-bit indexes on 64-bit
architectures.
Note: The throughput numbers are similar on Sandy Bridge and Haswell.
** Proposed Solution **
To avoid the penalty of all these sign/zero extensions, we merge them in the
loads at the beginning of the chain of computation by promoting all the chain of
computation on the extended type. The promotion is done if and only if we do not
introduce new extensions, i.e., if we do not degrade the code quality.
To achieve this, we extend the existing “move ext to load” optimization with the
promotion mechanism introduced to match larger patterns for addressing mode
(r200947).
The idea of this extension is to perform the following transformation:
ext(promotableInst1(...(promotableInstN(load))))
=>
promotedInst1(...(promotedInstN(ext(load))))
The promotion mechanism in that optimization is enabled by a new TargetLowering
switch, which is off by default. In other words, by default, the optimization
performs the “move ext to load” optimization as it was before this patch.
** Performance **
Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.
Tested Optimization Levels: O3/Os
Tests: llvm-testsuite + externals.
Results:
- No regression beside noise.
- Improvements:
CINT2006/473.astar: ~2%
Benchmarks/PAQ8p: ~2%
Misc/perlin: ~3%
The results are consistent for both O3 and Os.
<rdar://problem/
18310086>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224402
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Wed, 17 Dec 2014 01:01:30 +0000 (01:01 +0000)]
Add printing the LC_ENCRYPTION_INFO_64 load command with llvm-objdump’s -private-headers
and add tests for the two AArch64 binaries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224400
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Wed, 17 Dec 2014 00:43:22 +0000 (00:43 +0000)]
PR21875: codegen for non-type template parameters of nullptr_t type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224399
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Wed, 17 Dec 2014 00:29:23 +0000 (00:29 +0000)]
Revert "[CodeGenPrepare] Move sign/zero extensions near loads using type promotion."
This reverts commit r224351. It causes assertion failures when building
ICU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224397
91177308-0d34-0410-b5e6-
96231b3b80d8
Hans Wennborg [Tue, 16 Dec 2014 23:41:59 +0000 (23:41 +0000)]
SelectionDAG switch lowering: use 'unsigned' to count destination popularity
SwitchInst::getNumCases() returns unsinged, so using uint64_t to count cases
seems unnecessary.
Also fix a missing CHECK in the test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224393
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 23:36:15 +0000 (23:36 +0000)]
[Hexagon] Updating doubleword shift usages to new versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224391
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Tue, 16 Dec 2014 23:25:52 +0000 (23:25 +0000)]
Add printing the LC_ENCRYPTION_INFO load command with llvm-objdump’s -private-headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224390
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 23:23:41 +0000 (23:23 +0000)]
Linker: Drop superseded subprograms
When a function gets replaced by `ModuleLinker`, drop superseded
subprograms. This ensures that the "first" subprogram pointing at a
function is the same one that `!dbg` references point at.
This is a stop-gap fix for PR21910. Notably, this fixes Release+Asserts
bootstraps that are currently asserting out in
`LexicalScopes::initialize()` due to the explicit instantiations in
`lib/IR/Dominators.cpp` eventually getting replaced by -argpromotion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224389
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 16 Dec 2014 22:48:42 +0000 (22:48 +0000)]
fix typo, add spaces; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224384
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Tue, 16 Dec 2014 22:30:10 +0000 (22:30 +0000)]
[X86][SSE] Vector double -> float conversion memory folding (cvtpd2ps)
Added a missing memory folding relationship for the (V)CVTPD2PS instruction - we can safely fold these for stack reloads.
Differential Revision: http://reviews.llvm.org/D6663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224383
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Tue, 16 Dec 2014 22:29:43 +0000 (22:29 +0000)]
Make the assert a bit stronger.
We should get no declarations in here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224382
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 22:17:09 +0000 (22:17 +0000)]
[Hexagon] Removing old XTYPE/BIT instructions and replacing usages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224381
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 16 Dec 2014 21:57:18 +0000 (21:57 +0000)]
merge consecutive loads that are offset from a base address
SelectionDAG::isConsecutiveLoad() was not detecting consecutive loads
when the first load was offset from a base address.
This patch recognizes that pattern and subtracts the offset before comparing
the second load to see if it is consecutive.
The codegen change in the new test case improves from:
vmovsd 32(%rdi), %xmm0
vmovsd 48(%rdi), %xmm1
vmovhpd 56(%rdi), %xmm1, %xmm1
vmovhpd 40(%rdi), %xmm0, %xmm0
vinsertf128 $1, %xmm1, %ymm0, %ymm0
To:
vmovups 32(%rdi), %ymm0
An existing test case is also improved from:
vmovsd (%rdi), %xmm0
vmovsd 16(%rdi), %xmm1
vmovsd 24(%rdi), %xmm2
vunpcklpd %xmm2, %xmm0, %xmm0 ## xmm0 = xmm0[0],xmm2[0]
vmovhpd 8(%rdi), %xmm1, %xmm3
To:
vmovsd (%rdi), %xmm0
vmovsd 16(%rdi), %xmm1
vmovhpd 24(%rdi), %xmm0, %xmm0
vmovhpd 8(%rdi), %xmm1, %xmm1
This patch fixes PR21771 ( http://llvm.org/bugs/show_bug.cgi?id=21771 ).
Differential Revision: http://reviews.llvm.org/D6642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224379
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Tue, 16 Dec 2014 21:48:27 +0000 (21:48 +0000)]
Fix a bug in llvm-objdump’s -private-headers for the LC_VERSION_MIN_IPHONEOS
load command not getting printed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224376
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 21:28:58 +0000 (21:28 +0000)]
[Hexagon] Adding tstbit/bitclr/bitset instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374
91177308-0d34-0410-b5e6-
96231b3b80d8
Kostya Serebryany [Tue, 16 Dec 2014 21:24:15 +0000 (21:24 +0000)]
[sanitizer] prevent function call merging for sanitizer-coverage callbacks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224372
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Tue, 16 Dec 2014 21:00:25 +0000 (21:00 +0000)]
Fix another use of PRIx32 that should have been PRIx64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224368
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 20:57:56 +0000 (20:57 +0000)]
[Hexagon] Adding bit count and twiddling instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224367
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 20:40:23 +0000 (20:40 +0000)]
[Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224365
91177308-0d34-0410-b5e6-
96231b3b80d8
Frederic Riss [Tue, 16 Dec 2014 20:22:11 +0000 (20:22 +0000)]
[dsymutil] Pass the verbosity flag down to the processing. NFC for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224361
91177308-0d34-0410-b5e6-
96231b3b80d8
Frederic Riss [Tue, 16 Dec 2014 20:21:34 +0000 (20:21 +0000)]
[dsymutil] Avoid calling getStringTableData() for each symbol. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224360
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Tue, 16 Dec 2014 20:15:45 +0000 (20:15 +0000)]
x86-32: PUSHF/POPF use/def EFLAGS
Summary: As a side-quest for D6629 jvoung pointed out that I should use -verify-machineinstrs and this found a bug in x86-32's handling of EFLAGS for PUSHF/POPF. This patch fixes the use/def, and adds -verify-machineinstrs to all x86 tests which contain 'EFLAGS'. One exception: this patch leaves inline-asm-fpstack.ll as-is because it fails -verify-machineinstrs in a way unrelated to EFLAGS. This patch also modifies cmpxchg-clobber-flags.ll along the lines of what D6629 already does by also testing i386.
Test Plan: ninja check
Reviewers: t.p.northover, jvoung
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D6687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224359
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Tue, 16 Dec 2014 19:29:29 +0000 (19:29 +0000)]
Use CastInst::castIsValid to simplify the verifier.
Also delete a dead member variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224356
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 16 Dec 2014 19:16:17 +0000 (19:16 +0000)]
NVPTX: Remove duplicate of AsmPrinter::lowerConstant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224355
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Tue, 16 Dec 2014 19:16:14 +0000 (19:16 +0000)]
Move lowerConstant to AsmPrinter
This was a static function before, and NVPTX duplicated it
because it wasn't exposed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224354
91177308-0d34-0410-b5e6-
96231b3b80d8
Quentin Colombet [Tue, 16 Dec 2014 19:09:03 +0000 (19:09 +0000)]
[CodeGenPrepare] Move sign/zero extensions near loads using type promotion.
This patch extends the optimization in CodeGenPrepare that moves a sign/zero
extension near a load when the target can combine them. The optimization may
promote any operations between the extension and the load to make that possible.
Although this optimization may be beneficial for all targets, in particular
AArch64, this is enabled for X86 only as I have not benchmarked it for other
targets yet.
** Context **
Most targets feature extended loads, i.e., loads that perform a zero or sign
extension for free. In that context it is interesting to expose such pattern in
CodeGenPrepare so that the instruction selection pass can form such loads.
Sometimes, this pattern is blocked because of instructions between the load and
the extension. When those instructions are promotable to the extended type, we
can expose this pattern.
** Motivating Example **
Let us consider an example:
define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) {
%ld = load i8* %addr1
%zextld = zext i8 %ld to i32
%ld2 = load i32* %addr2
%add = add nsw i32 %ld2, %zextld
%sextadd = sext i32 %add to i64
%zexta = zext i8 %a to i32
%addza = add nsw i32 %zexta, %zextld
%sextaddza = sext i32 %addza to i64
%addb = add nsw i32 %b, %zextld
%sextaddb = sext i32 %addb to i64
call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb)
ret void
}
As it is, this IR generates the following assembly on x86_64:
[...]
movzbl (%rdi), %eax # zero-extended load
movl (%rsi), %es # plain load
addl %eax, %esi # 32-bit add
movslq %esi, %rdi # sign extend the result of add
movzbl %dl, %edx # zero extend the first argument
addl %eax, %edx # 32-bit add
movslq %edx, %rsi # sign extend the result of add
addl %eax, %ecx # 32-bit add
movslq %ecx, %rdx # sign extend the result of add
[...]
The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA.
Now, by promoting the additions to form more extended loads we would generate:
[...]
movzbl (%rdi), %eax # zero-extended load
movslq (%rsi), %rdi # sign-extended load
addq %rax, %rdi # 64-bit add
movzbl %dl, %esi # zero extend the first argument
addq %rax, %rsi # 64-bit add
movslq %ecx, %rdx # sign extend the second argument
addq %rax, %rdx # 64-bit add
[...]
The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA.
This kind of sequences happen a lot on code using 32-bit indexes on 64-bit
architectures.
Note: The throughput numbers are similar on Sandy Bridge and Haswell.
** Proposed Solution **
To avoid the penalty of all these sign/zero extensions, we merge them in the
loads at the beginning of the chain of computation by promoting all the chain of
computation on the extended type. The promotion is done if and only if we do not
introduce new extensions, i.e., if we do not degrade the code quality.
To achieve this, we extend the existing “move ext to load” optimization with the
promotion mechanism introduced to match larger patterns for addressing mode
(r200947).
The idea of this extension is to perform the following transformation:
ext(promotableInst1(...(promotableInstN(load))))
=>
promotedInst1(...(promotedInstN(ext(load))))
The promotion mechanism in that optimization is enabled by a new TargetLowering
switch, which is off by default. In other words, by default, the optimization
performs the “move ext to load” optimization as it was before this patch.
** Performance **
Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10.
Tested Optimization Levels: O3/Os
Tests: llvm-testsuite + externals.
Results:
- No regression beside noise.
- Improvements:
CINT2006/473.astar: ~2%
Benchmarks/PAQ8p: ~2%
Misc/perlin: ~3%
The results are consistent for both O3 and Os.
<rdar://problem/
18310086>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224351
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Tue, 16 Dec 2014 18:58:11 +0000 (18:58 +0000)]
Fix the arm build bots for a test that was added. A printing routine was incorrectly using PRIx32
when it should have been using PRIx64 for the value that was passed as uint64_t .
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224350
91177308-0d34-0410-b5e6-
96231b3b80d8
Robert Khasanov [Tue, 16 Dec 2014 18:24:07 +0000 (18:24 +0000)]
[AVX512] Enable integer arithmetic lowering for AVX512BW/VL subsets.
Added lowering tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224349
91177308-0d34-0410-b5e6-
96231b3b80d8
Evgeny Astigeevich [Tue, 16 Dec 2014 18:16:17 +0000 (18:16 +0000)]
On behalf of Matthew Wahab:
An instruction alias defined with InstAlias and an optional operand in the
middle of the AsmString field, "..${a} <operands>", would get the final
"}" printed in the instruction disassembly. This wouldn't happen if the optional
operand appeared as the last item in the AsmString which is how the current
backends avoided the problem.
There don't appear to be any tests for this part of Tablegen but it passes the
pre-commit tests. Manually tested the change by enabling the generic alias
printer in the ARM backend and checking the output.
Differential Revision: http://reviews.llvm.org/D6529
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224348
91177308-0d34-0410-b5e6-
96231b3b80d8
Ahmed Bougacha [Tue, 16 Dec 2014 18:05:28 +0000 (18:05 +0000)]
[MC] Reset the MCInst in the matcher function before adding opcode/operands.
On X86, the Intel asm parser tries to match all memory operand sizes when
none is explicitly specified. For LEA, which doesn't really have a memory
operand (just a pointer one), this results in multiple successful matches,
one for each memory size. There's no error because it's same opcode, so
really, it's just one match. However, the tablegen'd matcher function
adds opcode/operands to the passed MCInst, and this results in multiple
duplicated operands.
This commit clears the MCInst in the tablegen'd matcher function.
We sometimes clear it when the match failed, so there's no expectation of
keeping the previous content anyway.
Differential Revision: http://reviews.llvm.org/D6670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224347
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 17:44:49 +0000 (17:44 +0000)]
[Hexagon] Adding absolute value, and negate with saturation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224346
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjay Patel [Tue, 16 Dec 2014 16:30:01 +0000 (16:30 +0000)]
combine consecutive subvector 16-byte loads into one 32-byte load
This is a fix for PR21709 ( http://llvm.org/bugs/show_bug.cgi?id=21709 ).
When we have 2 consecutive 16-byte loads that are merged into one 32-byte vector,
we can use a single 32-byte load instead.
But we don't do this for SandyBridge / IvyBridge because they have slower 32-byte memops.
We also don't bother using 32-byte *integer* loads on a machine that only has AVX1 (btver2)
because those operands would have to be split in half anyway since there is no support for
32-byte integer math ops.
Differential Revision: http://reviews.llvm.org/D6492
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224344
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 16:27:17 +0000 (16:27 +0000)]
[Hexagon] Adding saturate and swizzle instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224343
91177308-0d34-0410-b5e6-
96231b3b80d8
Robert Khasanov [Tue, 16 Dec 2014 16:12:11 +0000 (16:12 +0000)]
[AVX512] Add a comment for avx512_broadcast_pat multiclass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224341
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 16:10:01 +0000 (16:10 +0000)]
[Hexagon] Removing old multiply defs and updating references to new versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224340
91177308-0d34-0410-b5e6-
96231b3b80d8
Vladimir Medic [Tue, 16 Dec 2014 15:29:12 +0000 (15:29 +0000)]
The single check for N64 inside MipsDisassemblerBase's subclasses is actually wrong. It should be testing for FeatureGP64bit.There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224339
91177308-0d34-0410-b5e6-
96231b3b80d8
Zoran Jovanovic [Tue, 16 Dec 2014 14:59:10 +0000 (14:59 +0000)]
[mips][microMIPS] Implement SWP and LWP instructions
Differential Revision: http://reviews.llvm.org/D5667
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Ballman [Tue, 16 Dec 2014 14:04:11 +0000 (14:04 +0000)]
Fixing -Wsign-compare warnings; NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224337
91177308-0d34-0410-b5e6-
96231b3b80d8
Vladimir Medic [Tue, 16 Dec 2014 13:02:25 +0000 (13:02 +0000)]
Add disassembler tests for mips4 platform. There are no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224335
91177308-0d34-0410-b5e6-
96231b3b80d8
Elena Demikhovsky [Tue, 16 Dec 2014 11:50:42 +0000 (11:50 +0000)]
Masked Load and Store Intrinsics in loop vectorizer.
The loop vectorizer optimizes loops containing conditional memory
accesses by generating masked load and store intrinsics.
This decision is target dependent.
http://reviews.llvm.org/D6527
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224334
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Tue, 16 Dec 2014 11:21:58 +0000 (11:21 +0000)]
[mips] Fix arguments-struct.ll for Windows and OSX hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224333
91177308-0d34-0410-b5e6-
96231b3b80d8
Bradley Smith [Tue, 16 Dec 2014 10:59:27 +0000 (10:59 +0000)]
[ARM] Prevent PerformVCVTCombine from combining a vmul/vcvt with 8 lanes
This would result in a crash since the vcvt used does not support v8i32 types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224332
91177308-0d34-0410-b5e6-
96231b3b80d8
Elena Demikhovsky [Tue, 16 Dec 2014 09:10:08 +0000 (09:10 +0000)]
X86: Added FeatureVectorUAMem for all AVX architectures.
According to AVX specification:
"Most arithmetic and data processing instructions encoded using the VEX prefix and
performing memory accesses have more flexible memory alignment requirements
than instructions that are encoded without the VEX prefix. Specifically,
With the exception of explicitly aligned 16 or 32 byte SIMD load/store instructions,
most VEX-encoded, arithmetic and data processing instructions operate in
a flexible environment regarding memory address alignment, i.e. VEX-encoded
instruction with 32-byte or 16-byte load semantics will support unaligned load
operation by default. Memory arguments for most instructions with VEX prefix
operate normally without causing #GP(0) on any byte-granularity alignment
(unlike Legacy SSE instructions)."
The same for AVX-512.
This change does not affect anything right now, because only the "memop pattern fragment"
depends on FeatureVectorUAMem and it is not used in AVX patterns.
All AVX patterns are based on the "unaligned load" anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224330
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 07:45:05 +0000 (07:45 +0000)]
Remove 'metadata' from comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224328
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 07:40:31 +0000 (07:40 +0000)]
IR: Stop printing 'metadata' in Metadata::print()
Stop printing `metadata` in `Metadata::print()` and
`Metadata::printAsOperand()`.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224327
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 07:09:37 +0000 (07:09 +0000)]
IR: Make MDNode::dump() useful by adding addresses
It's horrible to inspect `MDNode`s in a debugger. All of their operands
that are `MDNode`s get dumped as `<badref>`, since we can't assign
metadata slots in the context of a `Metadata::dump()`. (Why not? Why
not assign numbers lazily? Because then each time you called `dump()`,
a given `MDNode` could have a different lazily assigned number.)
Fortunately, the C memory model gives us perfectly good identifiers for
`MDNode`. Add pointer addresses to the dumps, transforming this:
(lldb) e N->dump()
!{i32 662302, i32 26, <badref>, null}
(lldb) e ((MDNode*)N->getOperand(2))->dump()
!{i32 4, !"foo"}
into:
(lldb) e N->dump()
!{i32 662302, i32 26, <0x100706ee0>, null}
(lldb) e ((MDNode*)0x100706ee0)->dump()
!{i32 4, !"foo"}
and this:
(lldb) e N->dump()
0x101200248 = !{<badref>, <badref>, <badref>, <badref>, <badref>}
(lldb) e N->getOperand(0)
(const llvm::MDOperand) $0 = {
MD = 0x00000001012004e0
}
(lldb) e N->getOperand(1)
(const llvm::MDOperand) $1 = {
MD = 0x00000001012004e0
}
(lldb) e N->getOperand(2)
(const llvm::MDOperand) $2 = {
MD = 0x0000000101200058
}
(lldb) e N->getOperand(3)
(const llvm::MDOperand) $3 = {
MD = 0x00000001012004e0
}
(lldb) e N->getOperand(4)
(const llvm::MDOperand) $4 = {
MD = 0x0000000101200058
}
(lldb) e ((MDNode*)0x00000001012004e0)->dump()
!{}
(lldb) e ((MDNode*)0x0000000101200058)->dump()
!{null}
into:
(lldb) e N->dump()
!{<0x1012004e0>, <0x1012004e0>, <0x101200058>, <0x1012004e0>, <0x101200058>}
(lldb) e ((MDNode*)0x1012004e0)->dump()
!{}
(lldb) e ((MDNode*)0x101200058)->dump()
!{null}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224325
91177308-0d34-0410-b5e6-
96231b3b80d8
Duncan P. N. Exon Smith [Tue, 16 Dec 2014 07:08:19 +0000 (07:08 +0000)]
DebugInfo: Update testcase to actually check something
This test was missing a `Debug Info Version` so it's `not grep` was
passing vacuously. Update it to CHECK for something useful at the same
time so it doesn't bitrot quite so easily in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224324
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Tue, 16 Dec 2014 05:53:25 +0000 (05:53 +0000)]
ARM: diagnose deprecated syntax
The use of SP and PC in the register list for stores is deprecated on ARM
(ARM ARM A.8.8.199):
ARM deprecates the use of ARM instructions that include the SP or the PC in
the list.
Provide a deprecation warning from the assembler in the case that the syntax is
ever seen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224319
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Tue, 16 Dec 2014 05:51:41 +0000 (05:51 +0000)]
[PowerPC] Improve instruction selection bit-permuting operations (32-bit)
The PowerPC backend, somewhat embarrassingly, did not generate an
optimal-length sequence of instructions for a 32-bit bswap. While adding a
pattern for the bswap intrinsic to fix this would not have been terribly
difficult, doing so would not have addressed the real problem: we had been
generating poor code for many bit-permuting operations (by which I mean things
like byte-swap that permute the bits of one or more inputs around in various
ways). Here are some initial steps toward solving this deficiency.
Bit-permuting operations are represented, at the SDAG level, using ISD::ROTL,
SHL, SRL, AND and OR (mostly with constant second operands). Looking back
through these operations, we can build up a description of the bits in the
resulting value in terms of bits of one or more input values (and constant
zeros). For each bit, we compute the rotation amount from the original value,
and then group consecutive (value, rotation factor) bits into groups. Groups
sharing these attributes are then collected and sorted, and we can then
instruction select the entire permutation using a combination of masked
rotations (rlwinm), imm ands (andi/andis), and masked rotation inserts
(rlwimi).
The result is that instead of lowering an i32 bswap as:
rlwinm 5, 3, 24, 16, 23
rlwinm 4, 3, 24, 0, 7
rlwimi 4, 3, 8, 8, 15
rlwimi 5, 3, 8, 24, 31
rlwimi 4, 5, 0, 16, 31
we now produce:
rlwinm 4, 3, 8, 0, 31
rlwimi 4, 3, 24, 16, 23
rlwimi 4, 3, 24, 0, 7
and for the 'test6' example in the PowerPC/README.txt file:
unsigned test6(unsigned x) {
return ((x & 0x00FF0000) >> 16) | ((x & 0x000000FF) << 16);
}
we used to produce:
lis 4, 255
rlwinm 3, 3, 16, 0, 31
ori 4, 4, 255
and 3, 3, 4
and now we produce:
rlwinm 4, 3, 16, 24, 31
rlwimi 4, 3, 16, 8, 15
and, as a nice bonus, this fixes the FIXME in
test/CodeGen/PowerPC/rlwimi-and.ll.
This commit does not include instruction-selection for i64 operations, those
will come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224318
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Tue, 16 Dec 2014 04:10:10 +0000 (04:10 +0000)]
ARM: 80-column
clang-format a function with an overly long string constant. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224314
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Tue, 16 Dec 2014 04:03:38 +0000 (04:03 +0000)]
LiveRangeCalc: Rewrite subrange calculation
This changes subrange calculation to calculate subranges sequentially
instead of in parallel. The code is easier to understand that way and
addresses the code review issues raised about LiveOutData being
hard to understand/needing more comments by removing them :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224313
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Tue, 16 Dec 2014 03:10:29 +0000 (03:10 +0000)]
Remove the last unnecessary member variable of mapped_file_region. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224312
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Tue, 16 Dec 2014 02:53:35 +0000 (02:53 +0000)]
Convert a member variable to a local variable. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224311
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Tue, 16 Dec 2014 02:19:26 +0000 (02:19 +0000)]
Remove unused member and simplify. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224309
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Tue, 16 Dec 2014 01:43:41 +0000 (01:43 +0000)]
Start adding thin archive support.
This is just sufficient for 'ar t' to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224307
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Tue, 16 Dec 2014 01:14:45 +0000 (01:14 +0000)]
Fix a bug in llvm-objdump’s -private-headers for 32-bit Mach-O files
printing the section header. And add some tests for this for 32-bit files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224302
91177308-0d34-0410-b5e6-
96231b3b80d8
Adrian Prantl [Tue, 16 Dec 2014 00:20:49 +0000 (00:20 +0000)]
ARM/AArch64: Attach the FrameSetup MIFlag to CFI instructions.
Debug info marks the first instruction without the FrameSetup flag
as being the end of the function prologue. Any CFI instructions in the
middle of the function prologue would cause debug info to end the prologue
too early and worse, attach the line number of the CFI instruction, which
incidentally is often 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224294
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Tue, 16 Dec 2014 00:07:24 +0000 (00:07 +0000)]
[Hexagon] Adding doubleword multiplies with and without accumulation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224293
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Ilseman [Mon, 15 Dec 2014 23:41:21 +0000 (23:41 +0000)]
Sink the isa into the assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224291
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Mon, 15 Dec 2014 23:29:37 +0000 (23:29 +0000)]
[Hexagon] Adding halfword to doubleword multiplies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224289
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Mon, 15 Dec 2014 23:19:07 +0000 (23:19 +0000)]
[Hexagon] Adding logical-logical accumulation instructions and tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224288
91177308-0d34-0410-b5e6-
96231b3b80d8
Sanjoy Das [Mon, 15 Dec 2014 22:50:15 +0000 (22:50 +0000)]
Teach ScalarEvolution to exploit min and max expressions when proving
isKnownPredicate.
The motivation for this change is to optimize away checks in loops
like this:
limit = min(t, len)
for (i = 0 to limit)
if (i >= len || i < 0) throw_array_of_of_bounds();
a[i] = ...
Differential Revision: http://reviews.llvm.org/D6635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224285
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Pilgrim [Mon, 15 Dec 2014 22:45:48 +0000 (22:45 +0000)]
Added missing tests for X86vzmovl folding. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224284
91177308-0d34-0410-b5e6-
96231b3b80d8
JF Bastien [Mon, 15 Dec 2014 22:34:58 +0000 (22:34 +0000)]
x86: Emit LOCK prefix after DATA16
Summary: x86 allows either ordering for the LOCK and DATA16 prefixes, but using GCC+GAS leads to different code generation than using LLVM. This change matches the order that GAS emits the x86 prefixes when a semicolon isn't used in inline assembly (see tc-i386.c comment before define LOCK_PREFIX), and helps simplify tooling that operates on the instruction's byte sequence (such as NaCl's validator). This change shouldn't have any performance impact.
Test Plan: ninja check
Reviewers: craig.topper, jvoung
Subscribers: jfb, llvm-commits
Differential Revision: http://reviews.llvm.org/D6630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224283
91177308-0d34-0410-b5e6-
96231b3b80d8
Colin LeMahieu [Mon, 15 Dec 2014 22:10:37 +0000 (22:10 +0000)]
[Hexagon] Adding a number of additional multiply forms with tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224282
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Ilseman [Mon, 15 Dec 2014 21:47:09 +0000 (21:47 +0000)]
Clean up warning about unused variable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224281
91177308-0d34-0410-b5e6-
96231b3b80d8
Matthias Braun [Mon, 15 Dec 2014 21:36:35 +0000 (21:36 +0000)]
Revert "LiveRangeCalc: Rewrite subrange calculation"
Revert until I find out why non-subreg enabled targets break.
This reverts commit
6097277eefb9c5fb35a7f493c783ee1fd1b9d6a7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224278
91177308-0d34-0410-b5e6-
96231b3b80d8
Michael Ilseman [Mon, 15 Dec 2014 21:36:29 +0000 (21:36 +0000)]
Revert of r223763, in spirit.
r223763 was made to work around a temporary issue where a user of the
JIT was passing down a declaration (incorrectly). This shouldn't
occur, so assert rather than silently continue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224277
91177308-0d34-0410-b5e6-
96231b3b80d8