OSDN Git Service
Vedant Kumar [Fri, 8 Sep 2017 20:24:23 +0000 (20:24 +0000)]
[llvm-cov] Use portable output redirection in a test
A follow-up to a test fix (r312825).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312826
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Vedant Kumar [Fri, 8 Sep 2017 20:18:17 +0000 (20:18 +0000)]
[llvm-cov] Try to appease a Windows bot
On a Windows bot, I see a FileCheck error where the source being matched
over no longer exists, i.e it seems like it's FileCheck'ing some stale
output:
http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/4747
You can see "// CHECK: [[@LINE]]|{{ +}Marker at 19:3 = 1" in the
FileCheck stderr, but that CHECK line doesn't exist.
Remove the input file to FileCheck before running the test, to try and
appease the bot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312825
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Matt Arsenault [Fri, 8 Sep 2017 19:09:13 +0000 (19:09 +0000)]
AMDGPU: Start using !con operator
We have a lot of operand definition work essentially producing
every valid permutation of operands to workaround builiding
operand lists based on the instruction features. Apparently tablegen
already has a mostly undocumented operator to concat dags which
simplies this.
Convert one simple place to use this. The BUF instruction definitions
have much more complicated logic that can be totally rewritten now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312822
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Vedant Kumar [Fri, 8 Sep 2017 19:08:39 +0000 (19:08 +0000)]
[llvm-cov] Disable name-compression in a test binary
This should fix the lld bot:
The Buildbot has detected a new failure on builder llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast while building cfe.
Full details are available at:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/16993
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312821
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Matt Arsenault [Fri, 8 Sep 2017 18:51:26 +0000 (18:51 +0000)]
AMDGPU: Recompute scc liveness
The various scalar bit operations set SCC,
so one is erased or moved it needs to be recomputed.
Not sure why the existing tests don't fail on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312819
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Vedant Kumar [Fri, 8 Sep 2017 18:44:50 +0000 (18:44 +0000)]
[Coverage] Build sorted and unique segments
A coverage segment contains a starting line and column, an execution
count, and some other metadata. Clients of the coverage library use
segments to prepare line-oriented reports.
Users of the coverage library depend on segments being unique and sorted
in source order. Currently this is not guaranteed (this is why the clang
change which introduced deferred regions was reverted).
This commit documents the "unique and sorted" condition and asserts that
it holds. It also fixes the SegmentBuilder so that it produces correct
output in some edge cases.
Testing: I've added unit tests for some edge cases. I've also checked
that the new SegmentBuilder implementation is fully covered. Apart from
running check-profile and the llvm-cov tests, I've successfully used a
stage1 llvm-cov to prepare a coverage report for an instrumented clang
binary.
Differential Revision: https://reviews.llvm.org/D36813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312817
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Vedant Kumar [Fri, 8 Sep 2017 18:44:49 +0000 (18:44 +0000)]
[llvm-cov] Fix a lifetime issue
This fixes an issue where a std::string was moved to a constructor
which accepted a StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312816
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Vedant Kumar [Fri, 8 Sep 2017 18:44:48 +0000 (18:44 +0000)]
[Coverage] Define LineColPair for convenience. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312815
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Vedant Kumar [Fri, 8 Sep 2017 18:44:47 +0000 (18:44 +0000)]
[Coverage] Report errors when reading malformed source regions
Each source region has a start and end location. Report an error when
the end location does not precede the begin location.
The old lineExecutionCounts.covmapping test actually had a buggy source
region in it. This commit introduces a regenerated copy of the coverage
and moves the old copy to malformedRegions.covmapping, for a test.
Differential Revision: https://reviews.llvm.org/D37387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312814
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Vedant Kumar [Fri, 8 Sep 2017 18:44:46 +0000 (18:44 +0000)]
[llvm-cov] Unify region marker placement between text/html modes
Make sure that the text and html emitters always emit the same set of
region markers, and avoid emitting redundant markers for line segments
which don't end on the line they start on.
This is related to D35925, and depends on D36014
Differential Revision: https://reviews.llvm.org/D36020
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312813
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Chandler Carruth [Fri, 8 Sep 2017 18:23:42 +0000 (18:23 +0000)]
[x86] Fix GCC pedantic warnings about default arguments for lambdas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312809
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Craig Topper [Fri, 8 Sep 2017 17:33:54 +0000 (17:33 +0000)]
[X86] Simplify the slow-incdec test and add test cases with optsize.
I think we want to consider using inc/dec with optsize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312804
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Dinar Temirbulatov [Fri, 8 Sep 2017 17:08:17 +0000 (17:08 +0000)]
[SLPVectorizer] Add struct InstructionsState that holds information about analysis of vector to be vectorized.
Reviewers: spatel, mzolotukhin, mkuper, hfinkel, RKSimon, filcab, ABataev, davide
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D37212
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312802
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Wei Mi [Fri, 8 Sep 2017 16:44:52 +0000 (16:44 +0000)]
Fix a bug for rL312641.
rL312641 Allowed llvm.memcpy/memset/memmove to be tail calls when parent
function return the intrinsics's first argument. However on arm-none-eabi
platform, llvm.memcpy will be expanded to __aeabi_memcpy which doesn't
have return value. The fix is to check the libcall name after expansion
to match "memcpy/memset/memmove" before allowing those intrinsic to be
tail calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312799
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Krzysztof Parzyszek [Fri, 8 Sep 2017 16:29:50 +0000 (16:29 +0000)]
Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnits
Differential Revision: https://reviews.llvm.org/D37600
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312797
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Alexey Bataev [Fri, 8 Sep 2017 14:32:20 +0000 (14:32 +0000)]
[SLP] Fix the warning about paths not returning the value, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312793
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Alexey Bataev [Fri, 8 Sep 2017 13:49:36 +0000 (13:49 +0000)]
[SLP] Support for horizontal min/max reduction.
SLP vectorizer supports horizontal reductions for Add/FAdd binary
operations. Patch adds support for horizontal min/max reductions.
Function getReductionCost() is split to getArithmeticReductionCost() for
binary operation reductions and getMinMaxReductionCost() for min/max
reductions.
Patch fixes PR26956.
Differential revision: https://reviews.llvm.org/D27846
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312791
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Simon Pilgrim [Fri, 8 Sep 2017 10:49:11 +0000 (10:49 +0000)]
[X86] Added PR31045 test case
Reduced version of 'addr-calc-crash.ll' that was included in D27044, that had been fixed already by D31286/rL298633
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312786
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Max Kazantsev [Fri, 8 Sep 2017 10:15:05 +0000 (10:15 +0000)]
Re-enable "[IRCE] Identify loops with latch comparison against current IV value"
Re-applying after the found bug was fixed.
Differential Revision: https://reviews.llvm.org/D36215
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312783
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Jonas Devlieghere [Fri, 8 Sep 2017 09:48:51 +0000 (09:48 +0000)]
[dwarfdump] Verify line table prologue
This patch adds prologue verification, which is already present in
Apple's dwarfdump. It checks for invalid directory indices and warns
about duplicate file paths.
Differential revision: https://reviews.llvm.org/D37511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312782
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Jatin Bhateja [Fri, 8 Sep 2017 09:15:36 +0000 (09:15 +0000)]
[X86] Adding a test point for PR34149 'Suboptimal codegen for "fast" minnum and maxnum'
Differential Revision: https://reviews.llvm.org/D37614
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312778
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Martin Storsjo [Fri, 8 Sep 2017 06:49:46 +0000 (06:49 +0000)]
[llvm-dlltool] Mention arm64 in the lists of architecture alternatives
This was missed in SVN r310223 when arm64 support was added.
Differential Revision: https://reviews.llvm.org/D37588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312776
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Max Kazantsev [Fri, 8 Sep 2017 04:26:41 +0000 (04:26 +0000)]
diff --git a/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp b/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
index
f72a808..
9fa49fd 100644
--- a/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
+++ b/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp
@@ -450,20 +450,10 @@ struct LoopStructure {
// equivalent to:
//
// intN_ty inc = IndVarIncreasing ? 1 : -1;
- // pred_ty predicate = IndVarIncreasing
- // ? IsSignedPredicate ? ICMP_SLT : ICMP_ULT
- // : IsSignedPredicate ? ICMP_SGT : ICMP_UGT;
+ // pred_ty predicate = IndVarIncreasing ? ICMP_SLT : ICMP_SGT;
//
- //
- // for (intN_ty iv = IndVarStart; predicate(IndVarBase, LoopExitAt);
- // iv = IndVarNext)
+ // for (intN_ty iv = IndVarStart; predicate(iv, LoopExitAt); iv = IndVarBase)
// ... body ...
- //
- // Here IndVarBase is either current or next value of the induction variable.
- // in the former case, IsIndVarNext = false and IndVarBase points to the
- // Phi node of the induction variable. Otherwise, IsIndVarNext = true and
- // IndVarBase points to IV increment instruction.
- //
Value *IndVarBase;
Value *IndVarStart;
@@ -471,13 +461,12 @@ struct LoopStructure {
Value *LoopExitAt;
bool IndVarIncreasing;
bool IsSignedPredicate;
- bool IsIndVarNext;
LoopStructure()
: Tag(""), Header(nullptr), Latch(nullptr), LatchBr(nullptr),
LatchExit(nullptr), LatchBrExitIdx(-1), IndVarBase(nullptr),
IndVarStart(nullptr), IndVarStep(nullptr), LoopExitAt(nullptr),
- IndVarIncreasing(false), IsSignedPredicate(true), IsIndVarNext(false) {}
+ IndVarIncreasing(false), IsSignedPredicate(true) {}
template <typename M> LoopStructure map(M Map) const {
LoopStructure Result;
@@ -493,7 +482,6 @@ struct LoopStructure {
Result.LoopExitAt = Map(LoopExitAt);
Result.IndVarIncreasing = IndVarIncreasing;
Result.IsSignedPredicate = IsSignedPredicate;
- Result.IsIndVarNext = IsIndVarNext;
return Result;
}
@@ -841,42 +829,21 @@ LoopStructure::parseLoopStructure(ScalarEvolution &SE,
return false;
};
- // `ICI` can either be a comparison against IV or a comparison of IV.next.
- // Depending on the interpretation, we calculate the start value differently.
+ // `ICI` is interpreted as taking the backedge if the *next* value of the
+ // induction variable satisfies some constraint.
- // Pair {IndVarBase; IsIndVarNext} semantically designates whether the latch
- // comparisons happens against the IV before or after its value is
- // incremented. Two valid combinations for them are:
- //
- // 1) { phi [ iv.start, preheader ], [ iv.next, latch ]; false },
- // 2) { iv.next; true }.
- //
- // The latch comparison happens against IndVarBase which can be either current
- // or next value of the induction variable.
const SCEVAddRecExpr *IndVarBase = cast<SCEVAddRecExpr>(LeftSCEV);
bool IsIncreasing = false;
bool IsSignedPredicate = true;
- bool IsIndVarNext = false;
ConstantInt *StepCI;
if (!IsInductionVar(IndVarBase, IsIncreasing, StepCI)) {
FailureReason = "LHS in icmp not induction variable";
return None;
}
- const SCEV *IndVarStart = nullptr;
- // TODO: Currently we only handle comparison against IV, but we can extend
- // this analysis to be able to deal with comparison against sext(iv) and such.
- if (isa<PHINode>(LeftValue) &&
- cast<PHINode>(LeftValue)->getParent() == Header)
- // The comparison is made against current IV value.
- IndVarStart = IndVarBase->getStart();
- else {
- // Assume that the comparison is made against next IV value.
- const SCEV *StartNext = IndVarBase->getStart();
- const SCEV *Addend = SE.getNegativeSCEV(IndVarBase->getStepRecurrence(SE));
- IndVarStart = SE.getAddExpr(StartNext, Addend);
- IsIndVarNext = true;
- }
+ const SCEV *StartNext = IndVarBase->getStart();
+ const SCEV *Addend = SE.getNegativeSCEV(IndVarBase->getStepRecurrence(SE));
+ const SCEV *IndVarStart = SE.getAddExpr(StartNext, Addend);
const SCEV *Step = SE.getSCEV(StepCI);
ConstantInt *One = ConstantInt::get(IndVarTy, 1);
@@ -1060,7 +1027,6 @@ LoopStructure::parseLoopStructure(ScalarEvolution &SE,
Result.IndVarIncreasing = IsIncreasing;
Result.LoopExitAt = RightValue;
Result.IsSignedPredicate = IsSignedPredicate;
- Result.IsIndVarNext = IsIndVarNext;
FailureReason = nullptr;
@@ -1350,9 +1316,8 @@ LoopConstrainer::RewrittenRangeInfo LoopConstrainer::changeIterationSpaceEnd(
BranchToContinuation);
NewPHI->addIncoming(PN->getIncomingValueForBlock(Preheader), Preheader);
- auto *FixupValue =
- LS.IsIndVarNext ? PN->getIncomingValueForBlock(LS.Latch) : PN;
- NewPHI->addIncoming(FixupValue, RRI.ExitSelector);
+ NewPHI->addIncoming(PN->getIncomingValueForBlock(LS.Latch),
+ RRI.ExitSelector);
RRI.PHIValuesAtPseudoExit.push_back(NewPHI);
}
@@ -1735,10 +1700,7 @@ bool InductiveRangeCheckElimination::runOnLoop(Loop *L, LPPassManager &LPM) {
}
LoopStructure LS = MaybeLoopStructure.getValue();
const SCEVAddRecExpr *IndVar =
- cast<SCEVAddRecExpr>(SE.getSCEV(LS.IndVarBase));
- if (LS.IsIndVarNext)
- IndVar = cast<SCEVAddRecExpr>(SE.getMinusSCEV(IndVar,
- SE.getSCEV(LS.IndVarStep)));
+ cast<SCEVAddRecExpr>(SE.getMinusSCEV(SE.getSCEV(LS.IndVarBase), SE.getSCEV(LS.IndVarStep)));
Optional<InductiveRangeCheck::Range> SafeIterRange;
Instruction *ExprInsertPt = Preheader->getTerminator();
diff --git a/test/Transforms/IRCE/latch-comparison-against-current-value.ll b/test/Transforms/IRCE/latch-comparison-against-current-value.ll
deleted file mode 100644
index
afea0e6..
0000000
--- a/test/Transforms/IRCE/latch-comparison-against-current-value.ll
+++ /dev/null
@@ -1,182 +0,0 @@
-; RUN: opt -verify-loop-info -irce-print-changed-loops -irce -S < %s 2>&1 | FileCheck %s
-
-; Check that IRCE is able to deal with loops where the latch comparison is
-; done against current value of the IV, not the IV.next.
-
-; CHECK: irce: in function test_01: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
-; CHECK: irce: in function test_02: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
-; CHECK-NOT: irce: in function test_03: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
-; CHECK-NOT: irce: in function test_04: constrained Loop at depth 1 containing: %loop<header><exiting>,%in.bounds<latch><exiting>
-
-; SLT condition for increasing loop from 0 to 100.
-define void @test_01(i32* %arr, i32* %a_len_ptr) #0 {
-
-; CHECK: test_01
-; CHECK: entry:
-; CHECK-NEXT: %exit.mainloop.at = load i32, i32* %a_len_ptr, !range !0
-; CHECK-NEXT: [[COND2:%[^ ]+]] = icmp slt i32 0, %exit.mainloop.at
-; CHECK-NEXT: br i1 [[COND2]], label %loop.preheader, label %main.pseudo.exit
-; CHECK: loop:
-; CHECK-NEXT: %idx = phi i32 [ %idx.next, %in.bounds ], [ 0, %loop.preheader ]
-; CHECK-NEXT: %idx.next = add nuw nsw i32 %idx, 1
-; CHECK-NEXT: %abc = icmp slt i32 %idx, %exit.mainloop.at
-; CHECK-NEXT: br i1 true, label %in.bounds, label %out.of.bounds.loopexit1
-; CHECK: in.bounds:
-; CHECK-NEXT: %addr = getelementptr i32, i32* %arr, i32 %idx
-; CHECK-NEXT: store i32 0, i32* %addr
-; CHECK-NEXT: %next = icmp slt i32 %idx, 100
-; CHECK-NEXT: [[COND3:%[^ ]+]] = icmp slt i32 %idx, %exit.mainloop.at
-; CHECK-NEXT: br i1 [[COND3]], label %loop, label %main.exit.selector
-; CHECK: main.exit.selector:
-; CHECK-NEXT: %idx.lcssa = phi i32 [ %idx, %in.bounds ]
-; CHECK-NEXT: [[COND4:%[^ ]+]] = icmp slt i32 %idx.lcssa, 100
-; CHECK-NEXT: br i1 [[COND4]], label %main.pseudo.exit, label %exit
-; CHECK-NOT: loop.preloop:
-; CHECK: loop.postloop:
-; CHECK-NEXT: %idx.postloop = phi i32 [ %idx.copy, %postloop ], [ %idx.next.postloop, %in.bounds.postloop ]
-; CHECK-NEXT: %idx.next.postloop = add nuw nsw i32 %idx.postloop, 1
-; CHECK-NEXT: %abc.postloop = icmp slt i32 %idx.postloop, %exit.mainloop.at
-; CHECK-NEXT: br i1 %abc.postloop, label %in.bounds.postloop, label %out.of.bounds.loopexit
-
-entry:
- %len = load i32, i32* %a_len_ptr, !range !0
- br label %loop
-
-loop:
- %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
- %idx.next = add nsw nuw i32 %idx, 1
- %abc = icmp slt i32 %idx, %len
- br i1 %abc, label %in.bounds, label %out.of.bounds
-
-in.bounds:
- %addr = getelementptr i32, i32* %arr, i32 %idx
- store i32 0, i32* %addr
- %next = icmp slt i32 %idx, 100
- br i1 %next, label %loop, label %exit
-
-out.of.bounds:
- ret void
-
-exit:
- ret void
-}
-
-; ULT condition for increasing loop from 0 to 100.
-define void @test_02(i32* %arr, i32* %a_len_ptr) #0 {
-
-; CHECK: test_02
-; CHECK: entry:
-; CHECK-NEXT: %exit.mainloop.at = load i32, i32* %a_len_ptr, !range !0
-; CHECK-NEXT: [[COND2:%[^ ]+]] = icmp ult i32 0, %exit.mainloop.at
-; CHECK-NEXT: br i1 [[COND2]], label %loop.preheader, label %main.pseudo.exit
-; CHECK: loop:
-; CHECK-NEXT: %idx = phi i32 [ %idx.next, %in.bounds ], [ 0, %loop.preheader ]
-; CHECK-NEXT: %idx.next = add nuw nsw i32 %idx, 1
-; CHECK-NEXT: %abc = icmp ult i32 %idx, %exit.mainloop.at
-; CHECK-NEXT: br i1 true, label %in.bounds, label %out.of.bounds.loopexit1
-; CHECK: in.bounds:
-; CHECK-NEXT: %addr = getelementptr i32, i32* %arr, i32 %idx
-; CHECK-NEXT: store i32 0, i32* %addr
-; CHECK-NEXT: %next = icmp ult i32 %idx, 100
-; CHECK-NEXT: [[COND3:%[^ ]+]] = icmp ult i32 %idx, %exit.mainloop.at
-; CHECK-NEXT: br i1 [[COND3]], label %loop, label %main.exit.selector
-; CHECK: main.exit.selector:
-; CHECK-NEXT: %idx.lcssa = phi i32 [ %idx, %in.bounds ]
-; CHECK-NEXT: [[COND4:%[^ ]+]] = icmp ult i32 %idx.lcssa, 100
-; CHECK-NEXT: br i1 [[COND4]], label %main.pseudo.exit, label %exit
-; CHECK-NOT: loop.preloop:
-; CHECK: loop.postloop:
-; CHECK-NEXT: %idx.postloop = phi i32 [ %idx.copy, %postloop ], [ %idx.next.postloop, %in.bounds.postloop ]
-; CHECK-NEXT: %idx.next.postloop = add nuw nsw i32 %idx.postloop, 1
-; CHECK-NEXT: %abc.postloop = icmp ult i32 %idx.postloop, %exit.mainloop.at
-; CHECK-NEXT: br i1 %abc.postloop, label %in.bounds.postloop, label %out.of.bounds.loopexit
-
-entry:
- %len = load i32, i32* %a_len_ptr, !range !0
- br label %loop
-
-loop:
- %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
- %idx.next = add nsw nuw i32 %idx, 1
- %abc = icmp ult i32 %idx, %len
- br i1 %abc, label %in.bounds, label %out.of.bounds
-
-in.bounds:
- %addr = getelementptr i32, i32* %arr, i32 %idx
- store i32 0, i32* %addr
- %next = icmp ult i32 %idx, 100
- br i1 %next, label %loop, label %exit
-
-out.of.bounds:
- ret void
-
-exit:
- ret void
-}
-
-; Same as test_01, but comparison happens against IV extended to a wider type.
-; This test ensures that IRCE rejects it and does not falsely assume that it was
-; a comparison against iv.next.
-; TODO: We can actually extend the recognition to cover this case.
-define void @test_03(i32* %arr, i64* %a_len_ptr) #0 {
-
-; CHECK: test_03
-
-entry:
- %len = load i64, i64* %a_len_ptr, !range !1
- br label %loop
-
-loop:
- %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
- %idx.next = add nsw nuw i32 %idx, 1
- %idx.ext = sext i32 %idx to i64
- %abc = icmp slt i64 %idx.ext, %len
- br i1 %abc, label %in.bounds, label %out.of.bounds
-
-in.bounds:
- %addr = getelementptr i32, i32* %arr, i32 %idx
- store i32 0, i32* %addr
- %next = icmp slt i32 %idx, 100
- br i1 %next, label %loop, label %exit
-
-out.of.bounds:
- ret void
-
-exit:
- ret void
-}
-
-; Same as test_02, but comparison happens against IV extended to a wider type.
-; This test ensures that IRCE rejects it and does not falsely assume that it was
-; a comparison against iv.next.
-; TODO: We can actually extend the recognition to cover this case.
-define void @test_04(i32* %arr, i64* %a_len_ptr) #0 {
-
-; CHECK: test_04
-
-entry:
- %len = load i64, i64* %a_len_ptr, !range !1
- br label %loop
-
-loop:
- %idx = phi i32 [ 0, %entry ], [ %idx.next, %in.bounds ]
- %idx.next = add nsw nuw i32 %idx, 1
- %idx.ext = sext i32 %idx to i64
- %abc = icmp ult i64 %idx.ext, %len
- br i1 %abc, label %in.bounds, label %out.of.bounds
-
-in.bounds:
- %addr = getelementptr i32, i32* %arr, i32 %idx
- store i32 0, i32* %addr
- %next = icmp ult i32 %idx, 100
- br i1 %next, label %loop, label %exit
-
-out.of.bounds:
- ret void
-
-exit:
- ret void
-}
-
-!0 = !{i32 0, i32 50}
-!1 = !{i64 0, i64 50}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312775
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Adrian Prantl [Fri, 8 Sep 2017 02:31:37 +0000 (02:31 +0000)]
Fix a crash when emitting debug info for multi-reg function arguments
by reusing more of the existing machinery
This is a follow-up to r312169.
Thanks to Björn Pettersson for the testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312773
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Dean Michael Berris [Fri, 8 Sep 2017 01:47:56 +0000 (01:47 +0000)]
[XRay][CodeGen][PowerPC] Fix tail exit codegen for XRay in PPC
Summary:
This fixes code-gen for XRay in PPC. The regression wasn't caught by
codegen tests which we add in this change.
What happened was the following:
- For tail exits, we used to unconditionally prepend the returns/exits
with a pseudo-instruction that gets lowered to the instrumentation
sled (and leave the actual return/exit instruction as-is).
- Changes to the XRay instrumentation pass caused the tail exits to
suddenly also emit the tail exit pseudo-instruction, since the check
for whether a return instruction was also a call instruction meant it
was a tail exit instruction.
- None of the tests caught the regression either due to non-existent
tests, or the tests being disabled/removed for continuous breakage.
This change re-introduces some of the basic tests and verifies that
we're back to a state that allows the back-end to generate appropriate
XRay instrumented binaries for PPC in the presence of tail exits.
Reviewers: echristo, timshen
Subscribers: nemanjai, kbarton, llvm-commits
Differential Revision: https://reviews.llvm.org/D37570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312772
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Chandler Carruth [Fri, 8 Sep 2017 00:17:12 +0000 (00:17 +0000)]
[x86] Flesh out the custom ISel for RMW aritmetic ops with used flags to
cover the bitwise operators.
Nothing really exciting here, this just stamps out the rest of the core
operations that can RMW memory and set flags.
Still not implemented here: ADC, SBB. Those will require more
interesting logic to channel the flags *in*, and I'm not currently
planning to try to tackle that. It might be interesting for someone who
wants to improve our code generation for bignum implementations.
Differential Revision: https://reviews.llvm.org/D37141
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312768
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Peter Collingbourne [Fri, 8 Sep 2017 00:10:53 +0000 (00:10 +0000)]
WholeProgramDevirt: When promoting for single-impl devirt, also rename the comdat.
This is required when targeting COFF, as the comdat name must match
one of the names of the symbols in the comdat.
Differential Revision: https://reviews.llvm.org/D37550
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312767
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Chandler Carruth [Thu, 7 Sep 2017 23:54:24 +0000 (23:54 +0000)]
[x86] Extend the manual ISel of `add` and `sub` with both RMW memory
operands and used flags to support matching immediate operands.
This is a bit trickier than register operands, and we still want to fall
back on a register operands even for things that appear to be
"immediates" when they won't actually select into the operation's
immediate operand. This also requires us to handle things like selecting
`sub` vs. `add` to minimize the number of bits needed to represent the
immediate, and picking the shortest immediate encoding. In order to
that, we in turn need to scan to make sure that CF isn't used as it will
get inverted.
The end result seems very nice though, and we're now generating
optimal instruction sequences for these patterns IMO.
A follow-up patch will further expand this to other operations with RMW
memory operands. But handing `add` and `sub` are useful starting points
to flesh out the machinery and make sure interesting and complex cases
can be handled.
Thanks to Craig Topper who provided a few fixes and improvements to this
patch in addition to the review!
Differential Revision: https://reviews.llvm.org/D37139
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312764
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Rafael Espindola [Thu, 7 Sep 2017 23:30:48 +0000 (23:30 +0000)]
Don't call exit from cl::PrintHelpMessage.
Most callers were not expecting the exit(0) and trying to exit with a
different value.
This also adds back the call to cl::PrintHelpMessage in llvm-ar.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312761
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Eugene Zelenko [Thu, 7 Sep 2017 23:28:24 +0000 (23:28 +0000)]
[Bitcode] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312760
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Reid Kleckner [Thu, 7 Sep 2017 23:27:44 +0000 (23:27 +0000)]
Sink some IntrinsicInst.h and Intrinsics.h out of llvm/include
Many of these uses can get by with forward declarations. Hopefully this
speeds up compilation after adding a single intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312759
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Richard Trieu [Thu, 7 Sep 2017 23:20:35 +0000 (23:20 +0000)]
Revert r312318, r312325, r312424, r312489
r312318 - Debug info for variables whose type is shrinked to bool
r312325, r312424, r312489 - Test case for r312318
Revision 312318 introduced a null dereference bug.
Details in https://bugs.llvm.org/show_bug.cgi?id=34490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312758
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Petr Hosek [Thu, 7 Sep 2017 23:02:50 +0000 (23:02 +0000)]
[llvm-objcopy] Add support for special section indexes in symbol table greater than SHN_LORESERVE
As is indexes above SHN_LORESERVE will not be handled correctly because
they'll be treated as indexes of sections rather than special values
that should just be copied. This change adds support to copy them
though.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D37393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312756
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Reid Kleckner [Thu, 7 Sep 2017 22:46:24 +0000 (22:46 +0000)]
Move duplicate helpers from DbgValueInst / DbgDeclareInst to DbgInfoIntrinsic
NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312754
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Rafael Espindola [Thu, 7 Sep 2017 22:20:38 +0000 (22:20 +0000)]
llvm-ar: exit with 1 if there is an error.
This is pr34396.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312752
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Paul Robinson [Thu, 7 Sep 2017 22:15:44 +0000 (22:15 +0000)]
[DWARF] Line 0 should not have a discriminator.
It's meaningless and takes up extra space in the line table.
Differential Revision: https://reviews.llvm.org/D37364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312751
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Reid Kleckner [Thu, 7 Sep 2017 21:28:09 +0000 (21:28 +0000)]
Fix llvm-xray tests to avoid subshells
We already uses pipefail to detect failure of a redirected command, so
the "|| echo failure" construct was unnecessary.
These tests run and pass on Windows now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312747
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Lang Hames [Thu, 7 Sep 2017 21:04:00 +0000 (21:04 +0000)]
[ORC] Add ErrorSuccess and void specializations to AsyncHandlerTraits.
This will allow async handlers to be added that return void or Error::success().
Such handlers are expected to be common, since one of the primary uses of
addAsyncHandler is to run the body of the handler in a detached thread, in which
case the main handler returns immediately and does not need to provide an Error
value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312746
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Petr Hosek [Thu, 7 Sep 2017 20:44:16 +0000 (20:44 +0000)]
[yaml2obj][ELF] Add support for symbol indexes greater than SHN_LORESERVE
Right now Symbols must be either undefined or defined in a specific
section. Some symbols have section indexes like SHN_ABS however. This
change adds support for outputting symbols that have such section
indexes.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D37391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312745
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Peter Collingbourne [Thu, 7 Sep 2017 20:39:46 +0000 (20:39 +0000)]
COFF: PDB: Allow multiple modules with the same name.
It is possible for two modules to have the same name if they are
archive members with the same name, or if we are doing LTO (in which
case all modules will have the name "lto.tmp").
Differential Revision: https://reviews.llvm.org/D37589
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312744
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Peter Collingbourne [Thu, 7 Sep 2017 19:17:30 +0000 (19:17 +0000)]
Remove dead code. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312740
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Keith Wyss [Thu, 7 Sep 2017 19:10:34 +0000 (19:10 +0000)]
[XRay][tools] Disable windows for tests that use an unsupported shell redirect.
The tests are filechecking against stderr and use some magic to make stdout go
away and pipe stderr to FileCheck. This broke bots on windows.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312739
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Artem Belevich [Thu, 7 Sep 2017 18:14:32 +0000 (18:14 +0000)]
[CUDA] Added rudimentary support for CUDA-9 and sm_70.
For now CUDA-9 is not included in the list of CUDA versions clang
searches for, so the path to CUDA-9 must be explicitly passed
via --cuda-path=.
On LLVM side NVPTX added sm_70 GPU type which bumps required
PTX version to 6.0, but otherwise is equivalent to sm_62 at the moment.
Differential Revision: https://reviews.llvm.org/D37576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312734
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Keith Wyss [Thu, 7 Sep 2017 18:07:48 +0000 (18:07 +0000)]
[XRay][tools] Function call stack based analysis tooling for XRay traces
Second try after fixing a code san problem with iterator reference types.
This change introduces a subcommand to the llvm-xray tool called
"stacks" which allows for analysing XRay traces provided as inputs and
accounting time to stacks instead of just individual functions. This
gives us a more precise view of where in a program the latency is
actually attributed.
The tool uses a trie data structure to keep track of the caller-callee
relationships as we process the XRay traces. In particular, we keep
track of the function call stack as we enter functions. While we're
doing this we're adding nodes in a trie and indicating a "calls"
relatinship between the caller (current top of the stack) and the callee
(the new top of the stack). When we push function ids onto the stack, we
keep track of the timestamp (TSC) for the enter event.
When exiting functions, we are able to account the duration by getting
the difference between the timestamp of the exit event and the
corresponding entry event in the stack. This works even if we somehow
miss the exit events for intermediary functions (i.e. if the exit event
is not cleanly associated with the enter event at the top of the stack).
The output of the tool currently provides just the top N leaf functions
that contribute the most latency, and the top N stacks that have the
most frequency. In the future we can provide more sophisticated query
mechanisms and potentially an export to database feature to make offline
analysis of the stack traces possible with existing tools.
Differential revision: D34863
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312733
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Matt Arsenault [Thu, 7 Sep 2017 18:05:07 +0000 (18:05 +0000)]
AMDGPU: Start selecting v_mad_mix_f32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312732
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Matt Arsenault [Thu, 7 Sep 2017 17:24:43 +0000 (17:24 +0000)]
DAG: Allow creating extract_vector_elt post-legalize
Fixes some combine issues for AMDGPU where we weren't
getting the many extract_vector_elt combines expected
in a future patch.
This should really be checking isOperationLegalOrCustom on
the extract. That improves a number of x86 lit tests, but
a few get stuck in an infinite loop from one place
where a similar looking extract is created. I have a
different workaround in the backend for that which
keeps many of those improvements, but also adds a few
regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312730
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Konstantin Zhuravlyov [Thu, 7 Sep 2017 17:14:54 +0000 (17:14 +0000)]
AMDGPU: Handle non-temporal loads and stores
Differential Revision: https://reviews.llvm.org/D36862
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312729
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Konstantin Zhuravlyov [Thu, 7 Sep 2017 16:14:21 +0000 (16:14 +0000)]
AMDGPU: Handle more than one memory operand in SIMemoryLegalizer
Differential Revision: https://reviews.llvm.org/D37397
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312725
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Benjamin Kramer [Thu, 7 Sep 2017 14:52:26 +0000 (14:52 +0000)]
[ARM] Remove redundant vcvt patterns.
These don't add any value as they're just compositions of existing
patterns. However, they can confuse the cost logic in ISel, leading to
duplicated vcvt instructions like in PR33199.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312724
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Michael Zuckerman [Thu, 7 Sep 2017 14:02:13 +0000 (14:02 +0000)]
[X86][LLVM]Expanding Supports lowerInterleavedLoad() in X86InterleavedAccess (VF{8|16|32} stride 3).
This patch expands the support of lowerInterleavedload to {8|16|32}x8i stride 3.
LLVM creates suboptimal shuffle code-gen for AVX2. In overall, this patch is a specific fix for the pattern (Strid=3 VF={8|16|32}) and we plan to include the store (deinterleved side).
The patch goal is to optimize the following sequence:
a0 b0 c0 a1 b1 c1 a2 b2
c2 a3 b3 c3 a4 b4 c4 a5
b5 c5 a6 b6 c6 a7 b7 c7
into
a0 a1 a2 a3 a4 a5 a6 a7
b0 b1 b2 b3 b4 b5 b6 b7
c0 c1 c2 c3 c4 c5 c6 c7
Reviewers
1. zvi
2. igor
3. guyblank
4. dorit
5. Ayal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312722
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Simon Atanasyan [Thu, 7 Sep 2017 12:54:26 +0000 (12:54 +0000)]
[mips] Use RegisterMCAsmBackend to register all MIPS asm backends. NFC
This change converts the `MipsAsmBackend` constructor to the "standard"
form. It makes possible to use `RegisterMCAsmBackend` for the backends
registrations. Now we pass `Triple` instance to the `MipsAsmBackend`
ctor and deduce all required options like endianness and bitness from
the triple. We still need to implement explicit ABI checking for
providing correct options to backends.
Differential revision: https://reviews.llvm.org/D37519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312720
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Florian Hahn [Thu, 7 Sep 2017 12:49:39 +0000 (12:49 +0000)]
[MachineCombiner] Update instruction depths incrementally for large BBs.
Summary:
For large basic blocks with lots of combinable instructions, the
MachineTraceMetrics computations in MachineCombiner can dominate the compile
time, as computing the trace information is quadratic in the number of
instructions in a BB and it's relevant successors/predecessors.
In most cases, knowing the instruction depth should be enough to make
combination decisions. As we already iterate over all instructions in a basic
block, the instruction depth can be computed incrementally. This reduces the
cost of machine-combine drastically in cases where lots of instructions
are combined. The major drawback is that AFAIK, computing the critical path
length cannot be done incrementally. Therefore we only compute
instruction depths incrementally, for basic blocks with more
instructions than inc_threshold. The -machine-combiner-inc-threshold
option can be used to set the threshold and allows for easier
experimenting and checking if using incremental updates for all basic
blocks has any impact on the performance.
Reviewers: sanjoy, Gerolf, MatzeB, efriedma, fhahn
Reviewed By: fhahn
Subscribers: kiranchandramohan, javed.absar, efriedma, llvm-commits
Differential Revision: https://reviews.llvm.org/D36619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312719
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Florian Hahn [Thu, 7 Sep 2017 11:51:30 +0000 (11:51 +0000)]
[MachineTraceMetrics] Add computeDepth function (NFCI).
Summary:
This function is used in D36619 to update the instruction depths
incrementally.
Reviewers: efriedma, Gerolf, MatzeB, fhahn
Reviewed By: fhahn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D36696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312714
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Alex Bradbury [Thu, 7 Sep 2017 11:30:55 +0000 (11:30 +0000)]
[Sparc][NFC] Clean up SelectCC lowering
The ARM, BPF, MSP430, Sparc and Mips backends all use a similar code sequence
for lowering SelectCC. As pointed out by @reames in D29937, this code isn't
particularly clear and in most of these backends doesn't actually match the
comments. This patch makes the code sequence clearer for the Sparc backend
through better variable naming and more accurate comments (e.g. we are
inserting triangle control flow, _not_ diamond). There is no functional
change.
Differential Revision: https://reviews.llvm.org/D37194
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312713
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Benjamin Kramer [Thu, 7 Sep 2017 09:54:03 +0000 (09:54 +0000)]
Fixing incorrectly capitalised regexps.
Patch by Sam Allen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312709
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Jonas Paulsson [Thu, 7 Sep 2017 09:13:17 +0000 (09:13 +0000)]
Revert "[RegAlloc] Make sure live-ranges reflect the state of the IR when removing them"
This temporarily reverts commit
463fa38 (r311401).
See https://bugs.llvm.org/show_bug.cgi?id=34502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312708
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Alexander Ivchenko [Thu, 7 Sep 2017 08:59:05 +0000 (08:59 +0000)]
[x86] Update to cmov promotion tests for D36711; NFC
Adding i8 -> [i16, i32, i64] and i32 -> i64 cases.
This way we can see what the current codegen looks like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312707
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Zvi Rackover [Thu, 7 Sep 2017 07:40:34 +0000 (07:40 +0000)]
X86: Improve AVX512 fptoui lowering
Summary:
Add patterns for
fptoui <16 x float> to <16 x i8>
fptoui <16 x float> to <16 x i16>
Reviewers: igorb, delena, craig.topper
Reviewed By: craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312704
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Craig Topper [Thu, 7 Sep 2017 06:11:10 +0000 (06:11 +0000)]
[X86] Force shuffle lowering to only create X86ISD::VPERM2X128 with 64-bit element types so we can remove some patterns from isel.
Intrinsic handling is still creating these nodes with 32-bit elements as well. But at least this gets rid of 8 and 16.
Ideally, someday we'll convert the intrinsics to generic vector shuffles and remove the intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312702
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Matt Arsenault [Thu, 7 Sep 2017 05:37:34 +0000 (05:37 +0000)]
AMDGPU: Don't legalize i16 extloads to i32 with legal i16
Keeping non-i16 extloads makes it easier to match some new
gfx9 load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312699
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Peter Collingbourne [Thu, 7 Sep 2017 05:35:35 +0000 (05:35 +0000)]
ModuleSummaryAnalysis: Correctly handle all function operand references.
The current code that handles personality functions when creating a
module summary does not correctly handle the case where a function's
personality function operand refers to the function indirectly
(e.g. via a bitcast). This patch handles such cases by treating
personality function references like any other reference, i.e. by
adding them to the function's reference list. This has the minor side
benefit of allowing personality functions to participate in early
dead stripping.
We do this by calling findRefEdges on the function itself. This way
we also end up handling other function operands (specifically prefix
data and prologue data) for free.
Differential Revision: https://reviews.llvm.org/D37553
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312698
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Craig Topper [Thu, 7 Sep 2017 05:08:16 +0000 (05:08 +0000)]
[X86] Remove patterns for selecting a v8f32 X86ISD::MOVSS or v4f64 X86ISD::MOVSD.
I don't think we ever generate these. If we did, I would expect we would also be able to generate v16f32 and v8f64, but we don't have those patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312694
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Saleem Abdulrasool [Thu, 7 Sep 2017 04:00:13 +0000 (04:00 +0000)]
ARM: track globals promoted to coalesced const pool entries
Globals that are promoted to an ARM constant pool may alias with another
existing constant pool entry. We need to keep a reference to all globals
that were promoted to each constant pool value so that we can emit a
distinct label for each promoted global. These labels are necessary so
that debug info can refer to the promoted global without an undefined
reference during linking.
Patch by Stephen Crane!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312692
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Peter Collingbourne [Thu, 7 Sep 2017 01:33:52 +0000 (01:33 +0000)]
Object: Downgrade invalid weak externals from an assert fail to an llvm::Error when creating an irsymtab.
This fixes bitcode emission for modules containing invalid weak externals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312686
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Matt Arsenault [Thu, 7 Sep 2017 01:21:43 +0000 (01:21 +0000)]
InstSimplify: canonicalize is idempotent
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312685
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Peter Collingbourne [Thu, 7 Sep 2017 00:55:00 +0000 (00:55 +0000)]
LTO: Remove unnecessary Windows support code.
I empirically verified that open files can in fact be renamed on
Windows with sys::fs::rename, so remove the incorrect code and comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312683
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Petr Hosek [Wed, 6 Sep 2017 23:41:02 +0000 (23:41 +0000)]
Reland "[llvm-objcopy] Add support for relocations"
This change adds support for SHT_REL and SHT_RELA sections in
llvm-objcopy.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D36554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312680
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Eugene Zelenko [Wed, 6 Sep 2017 23:05:38 +0000 (23:05 +0000)]
[Pass] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312679
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Zvi Rackover [Wed, 6 Sep 2017 23:04:28 +0000 (23:04 +0000)]
Util: Improve update_llc_test_checks to scrub macosx-style assembly annotations
Summary:
In D37523 Sanjay pointed out that the tool does not scrub macosx-style 'End of Function' annotations,
where the comments begin with a double-#.
I tested this patch by verifying all existing occurences of 'End function' are scrubbed:
find ./test/CodeGen/X86 -name '*.ll' | xargs grep -l "End function" | xargs utils/update_llc_test_checks.py --llc-binary build/bin/llc
Reviewers: spatel, chandlerc, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37532
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312678
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Stanislav Mekhanoshin [Wed, 6 Sep 2017 22:27:29 +0000 (22:27 +0000)]
[AMDGPU] Use v_pk_max_f16 for fcanonicalize
Differential Revision: https://reviews.llvm.org/D37325
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312676
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Sam Clegg [Wed, 6 Sep 2017 22:05:41 +0000 (22:05 +0000)]
[WebAssembly] Only treat imports/exports as symbols when reading relocatable object files
This change only treats imported and exports functions and globals
as symbol table entries the object has a "linking" section (i.e. it is
relocatable object file).
In this case all globals must be of type I32 and initialized with
i32.const. This was previously being assumed but not checked for and
was causing a failure on big endian machines due to using the wrong
value of then union.
See: https://bugs.llvm.org/show_bug.cgi?id=34487
Differential Revision: https://reviews.llvm.org/D37497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312674
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Rui Ueyama [Wed, 6 Sep 2017 22:05:32 +0000 (22:05 +0000)]
Removes redundant `llvm::`, add comments and simplify a return type of a function.
No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312673
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Matthias Braun [Wed, 6 Sep 2017 20:45:24 +0000 (20:45 +0000)]
Insert IMPLICIT_DEFS for undef uses in tail merging
Tail merging can convert an undef use into a normal one when creating a
common tail. Doing so can make the register live out from a block which
previously contained the undef use. To keep the liveness up-to-date,
insert IMPLICIT_DEFs in such blocks when necessary.
To enable this patch the computeLiveIns() function which used to
compute live-ins for a block and set them immediately is split into new
functions:
- computeLiveIns() just computes the live-ins in a LivePhysRegs set.
- addLiveIns() applies the live-ins to a block live-in list.
- computeAndAddLiveIns() is a convenience function combining the other
two functions and behaving like computeLiveIns() before this patch.
Based on a patch by Krzysztof Parzyszek <kparzysz@codeaurora.org>
Differential Revision: https://reviews.llvm.org/D37034
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312668
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Mandeep Singh Grang [Wed, 6 Sep 2017 20:19:10 +0000 (20:19 +0000)]
[docs] Add a note on iteration of unordered containers to coding standards
Summary: Beware of non-determinism due to ordering of pointers
Reviewers: dblaikie, dexonsmith
Reviewed By: dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312667
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Krzysztof Parzyszek [Wed, 6 Sep 2017 19:36:58 +0000 (19:36 +0000)]
Disable jump threading into loop headers
Consider this type of a loop:
for (...) {
...
if (...) continue;
...
}
Normally, the "continue" would branch to the loop control code that
checks whether the loop should continue iterating and which contains
the (often) unique loop latch branch. In certain cases jump threading
can "thread" the inner branch directly to the loop header, creating
a second loop latch. Loop canonicalization would then transform this
loop into a loop nest. The problem with this is that in such a loop
nest neither loop is countable even if the original loop was. This
may inhibit subsequent loop optimizations and be detrimental to
performance.
Differential Revision: https://reviews.llvm.org/D36404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312664
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Sanjay Patel [Wed, 6 Sep 2017 19:05:20 +0000 (19:05 +0000)]
[x86] fix triple and regenerate checks for psubus; NFC
Patch by Yulia Koval!
Differential Revision: https://reviews.llvm.org/D37523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312662
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Craig Topper [Wed, 6 Sep 2017 19:03:55 +0000 (19:03 +0000)]
[X86] Move more isel patterns to X86InstrVecCompiler.td. NFC
This moves more of our subvector insert/extract tricks to X86InstrVecCompiler.td and refactors them into multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312661
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Stanislav Mekhanoshin [Wed, 6 Sep 2017 18:29:51 +0000 (18:29 +0000)]
[AMDGPU] Fixed encoding of v_pk_mul_f16 in fcanonicalize
Differential Revision: https://reviews.llvm.org/D37522
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312660
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Krzysztof Parzyszek [Wed, 6 Sep 2017 17:57:13 +0000 (17:57 +0000)]
[IfConversion] Remove kill flags from common instructions as well
When if-converting a diamond, two separate blocks will be placed back
to back to form a straight line code. To ensure correctness of the
liveness information, any registers that are live in the second block
should not be killed in the first block, even if they were in the
original code.
Additionally, when the two blocks share common instructions at the
beginning, these instructions will not be duplicated, but only placed
once, before both of the blocks. Since the function "isIdenticalTo"
(as used here) ignores kill flags, the common initial code in one
block may have a kill flag for a register that is live in the other
block.
Because the code that removes kill flags only runs for the non-common
parts of the predicated blocks, a kill flag mismatch in the common
code could still lead to a live register being killed prematurely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312654
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Craig Topper [Wed, 6 Sep 2017 17:06:40 +0000 (17:06 +0000)]
[X86] Actually add the new file that was supposed to go with r312649.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312650
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Craig Topper [Wed, 6 Sep 2017 16:56:52 +0000 (16:56 +0000)]
[X86] Introduce a new td file to hold patterns some of the non instruction patterns from SSE and AVX512
This patch moves some of similar non-instruction patterns from X86InstrSSE.td and X86InstrAVX512.td to a common file.
This is intended as a starting point. There are many other optimization patterns that exist in both files that we could move here.
Differential Revision: https://reviews.llvm.org/D37455
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312649
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Nuno Lopes [Wed, 6 Sep 2017 16:55:31 +0000 (16:55 +0000)]
Fix PR33878: BasicAA incorrectly assumes different address spaces don't alias
Remove code that assumed that a nullptr of address space != 0 couldnt alias with a non-null pointer. This is incorrect, since nothing can be concluded about a null pointer in an address space != 0.
This code was written before address spaces were introduced
Differential Revision: https://reviews.llvm.org/D37518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312648
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Alexander Kornienko [Wed, 6 Sep 2017 16:28:33 +0000 (16:28 +0000)]
Minor style fixes in lib/Support/**/Program.(inc|cpp).
No functional changes intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312646
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Petr Hosek [Wed, 6 Sep 2017 16:23:15 +0000 (16:23 +0000)]
Revert "[llvm-objcopy] Add support for relocations"
This reverts r312643 because it's failing on llvm-i686-linux-RA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312645
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Krzysztof Parzyszek [Wed, 6 Sep 2017 16:22:55 +0000 (16:22 +0000)]
[Hexagon] Add option to generate calls to "abort" for "unreachable"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312644
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Petr Hosek [Wed, 6 Sep 2017 16:19:48 +0000 (16:19 +0000)]
[llvm-objcopy] Add support for relocations
This change adds support for SHT_REL and SHT_RELA sections in
llvm-objcopy.
Patch by Jake Ehrlich
Differential Revision: https://reviews.llvm.org/D36554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312643
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Wei Mi [Wed, 6 Sep 2017 16:05:17 +0000 (16:05 +0000)]
[TailCall] Allow llvm.memcpy/memset/memmove to be tail calls when parent
function return the intrinsics's first argument.
llvm.memcpy/memset/memmove return void but they will return the first
argument after they are expanded as libcalls. Now if the parent function
has any return value, llvm.memcpy cannot be turned into tail call after
expansion.
The patch is to handle that case in SelectionDAGBuilder so when caller
function return the same value as the first argument of llvm.memcpy,
tail call is allowed.
Differential Revision: https://reviews.llvm.org/D37406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312641
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Stanislav Mekhanoshin [Wed, 6 Sep 2017 15:31:30 +0000 (15:31 +0000)]
[AMDGPU] Fix shouldClusterMemOps to process flat loads
Flat loads do not have vdata operand but have vdst instead.
Differential Revision: https://reviews.llvm.org/D37502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312640
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Nicolai Haehnle [Wed, 6 Sep 2017 13:50:13 +0000 (13:50 +0000)]
AMDGPU: Make worst-case assumption about the wait states in inline assembly
Summary:
Mesa still uses a hack where empty inline assembly is used as a kind of
optimization barrier. This exposed a problem where not enough wait states
were inserted, because the hazard recognizer implicitly assumed that each
inline assembly "instruction" has at least one wait state.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D37205
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312635
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Simon Pilgrim [Wed, 6 Sep 2017 10:23:12 +0000 (10:23 +0000)]
[X86][X87] Ensure x87 instructions are tagged as altering the FPSW reg
As noted in PR34080, a lot of x87 instructions alter the FPSW status register (or leave it in an undefined state) but aren't tagged as such in the tablegen.
This patch tags the control word, stack, wait and math instructions as altering FPSW, which matches what the AMD APMs suggests happens.
Differential Revision: https://reviews.llvm.org/D36414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312629
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Alex Bradbury [Wed, 6 Sep 2017 09:21:21 +0000 (09:21 +0000)]
[RISCV][NFC] Fix sorting of includes in lib/Target/RISCV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312624
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Craig Topper [Wed, 6 Sep 2017 06:50:03 +0000 (06:50 +0000)]
[DAGCombiner] When combining EXTRACT_SUBVECTOR of a BUILD_VECTOR, make sure we don't create a BUILD_VECTOR with an illegal type after type legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312621
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Chandler Carruth [Wed, 6 Sep 2017 06:28:08 +0000 (06:28 +0000)]
[x86] Fix PR34377 by disabling cmov conversion when we relied on it
performing a zext of a register.
On the PR there is discussion of how to more effectively handle this,
but this patch prevents us from miscompiling code.
Differential Revision: https://reviews.llvm.org/D37504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312620
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Zvi Rackover [Wed, 6 Sep 2017 05:33:04 +0000 (05:33 +0000)]
X86 Tests: Tidy up AVX512 conversion tests. NFC.
Rename functions to a consistent format to make it easier to track coverage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312619
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Jatin Bhateja [Wed, 6 Sep 2017 03:58:14 +0000 (03:58 +0000)]
Updating a test reference for rL312608.
Differential Revision: https://reviews.llvm.org/D37501
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312614
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Craig Topper [Wed, 6 Sep 2017 03:35:58 +0000 (03:35 +0000)]
[X86] Add more FMA3 patterns to cover a load in all 3 possible positions.
This matches what we already do for AVX512. The peephole pass makes up for this in most if not all cases. But this makes isel behavior for these consistent with every other instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312613
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Hal Finkel [Wed, 6 Sep 2017 03:08:26 +0000 (03:08 +0000)]
[PowerPC] Don't use xscvdpspn on the P7
xscvdpspn was not introduced until the P8, so don't use it on the P7. Fixes a
regression introduced in r288152.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312612
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Jatin Bhateja [Wed, 6 Sep 2017 02:58:47 +0000 (02:58 +0000)]
[X86] Allow cross-lane permutations for sub targets supporting AVX2.
Summary:
Most instructions in AVX work “in-lane”, that is, each source element is applied only to other
elements of the same lane, thus a cross lane permutation is costly and needs more than one instrution.
AVX2 includes instructions to perform any-to-any permutation of words over a 256-bit register
and vectorized table lookup.
This should also Fix PR34369
Differential Revision: https://reviews.llvm.org/D37388
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312608
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Lang Hames [Wed, 6 Sep 2017 02:53:37 +0000 (02:53 +0000)]
[ORC] Fix some comments in JITSymbol.
Patch by Breckin Loggins. Thanks Breckin!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312607
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Eric Beckmann [Wed, 6 Sep 2017 01:50:36 +0000 (01:50 +0000)]
Fix crbug 759265 by suppressing llvm mt warnings.
Summary:
Previous would throw warning whenever libxml2 is not installed. Now
only give this warning if merging manifest fails.
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D37240
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312604
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