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Oren Ben Simhon [Sat, 17 Mar 2018 13:29:46 +0000 (13:29 +0000)]
[X86] Added support for nocf_check attribute for indirect Branch Tracking
X86 Supports Indirect Branch Tracking (IBT) as part of Control-Flow Enforcement Technology (CET).
IBT instruments ENDBR instructions used to specify valid targets of indirect call / jmp.
The `nocf_check` attribute has two roles in the context of X86 IBT technology:
1. Appertains to a function - do not add ENDBR instruction at the beginning of the function.
2. Appertains to a function pointer - do not track the target function of this pointer by adding nocf_check prefix to the indirect-call instruction.
This patch implements `nocf_check` context for Indirect Branch Tracking.
It also auto generates `nocf_check` prefixes before indirect branchs to jump tables that are guarded by range checks.
Differential Revision: https://reviews.llvm.org/D41879
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327767
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Jonas Paulsson [Sat, 17 Mar 2018 09:15:13 +0000 (09:15 +0000)]
[SystemZ] Add 'REQUIRES: asserts' to test case using debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327766
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Jonas Paulsson [Sat, 17 Mar 2018 08:32:12 +0000 (08:32 +0000)]
[SystemZ] computeKnownBitsForTargetNode() / ComputeNumSignBitsForTargetNode()
Improve/implement these methods to improve DAG combining. This mainly
concerns intrinsics.
Some constant operands to SystemZISD nodes have been marked Opaque to avoid
transforming back and forth between generic and target nodes infinitely.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327765
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Jonas Paulsson [Sat, 17 Mar 2018 08:04:00 +0000 (08:04 +0000)]
[SelectionDAG] Handle big endian target BITCAST in computeKnownBits()
The BITCAST handling in computeKnownBits() previously only worked for little
endian.
This patch reverses the iteration over elements for a big endian target which
allows this to work in this case also.
SystemZ test case.
Review: Eli Friedman
https://reviews.llvm.org/D44249
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327764
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Chandler Carruth [Fri, 16 Mar 2018 23:51:33 +0000 (23:51 +0000)]
[GlobalsAA] Fix a pretty terrible bug that has been in GlobalsAA for
a long time.
The key thing is that we need to create value handles for every function
that we create a `FunctionInfo` object around. Without this, when that
function is deleted we can end up creating a new function that collides
with its address and look up a stale AA result. With that AA result we
can in turn miscompile code in ways that break.
This is seriously one of the most absurd miscompiles I've seen. It only
reproduced for us recently and only when building a very large server
with both ThinLTO and PGO.
A *HUGE* shout out to Wei Mi who tracked all of this down and came up
with this patch. I'm just landing it because I happened to still by at
a computer.
He or I can work on crafting a test case to hit this (now that we know
what to target) but it'll take a while, and we've been chasing this for
a long time and need it fix Right Now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327761
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Jessica Paquette [Fri, 16 Mar 2018 22:53:34 +0000 (22:53 +0000)]
[MachineOutliner] Make KILLs invisible
At the point the outliner runs, KILLs don't impact anything, but they're still
considered unique instructions. This commit makes them invisible like
DebugValues so that they can still be outlined without impacting outlining
decisions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327760
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Andrea Di Biagio [Fri, 16 Mar 2018 22:21:52 +0000 (22:21 +0000)]
[llvm-mca] Remove method getSchedModel() from the Backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327756
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Andrea Di Biagio [Fri, 16 Mar 2018 22:02:47 +0000 (22:02 +0000)]
[llvm-mca] Remove unused methods from Backend. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327749
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David L Kreitzer [Fri, 16 Mar 2018 21:21:23 +0000 (21:21 +0000)]
Quiet unused variable warnings. NFC.
Differential revision: https://reviews.llvm.org/D44583
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327745
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Craig Topper [Fri, 16 Mar 2018 21:10:07 +0000 (21:10 +0000)]
[X86] Pass SelectionDAG into X86ISelAddressMode::dump and on to SDNode::dump.
This prevents a crash in SelectionDAGDumper with -debug when trying to print mem operands if one of the registers in the addressing mode comes from a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327744
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Sanjay Patel [Fri, 16 Mar 2018 20:55:55 +0000 (20:55 +0000)]
[InstSimplify] add NaN constant diversity; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327743
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Krzysztof Parzyszek [Fri, 16 Mar 2018 20:55:49 +0000 (20:55 +0000)]
[Hexagon] Avoid bank conflicts in post-RA scheduler
Avoid scheduling two loads in such a way that they would end up in the
same packet. If there is a load in a packet, try to schedule a non-load
next.
Patch by Brendon Cahoon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327742
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Krzysztof Parzyszek [Fri, 16 Mar 2018 20:21:43 +0000 (20:21 +0000)]
[Hexagon] Add lit testcases for atomic intrinsics
Patch by Ben Craig.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327737
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Reid Kleckner [Fri, 16 Mar 2018 20:13:32 +0000 (20:13 +0000)]
[IR] Avoid the need to prefix MS C++ symbols with '\01'
Now the Windows mangling modes ('w' and 'x') do not do any mangling for
symbols starting with '?'. This means that clang can stop adding the
hideous '\01' leading escape. This means LLVM debug logs are less likely
to contain ASCII escape characters and it will be easier to copy and
paste MS symbol names from IR.
Finally.
For non-Windows platforms, names starting with '?' still get IR
mangling, so once clang stops escaping MS C++ names, we will get extra
'_' prefixing on MachO. That's fine, since it is currently impossible to
construct a triple that uses the MS C++ ABI in clang and emits macho
object files.
Differential Revision: https://reviews.llvm.org/D7775
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327734
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Reid Kleckner [Fri, 16 Mar 2018 20:11:55 +0000 (20:11 +0000)]
Revert r327721 "This patch fixes the invalid usage of OptSize in Machine Combiner."
It causes asserts when compiling Chromium on Win32 with optimizations.
We compile many things with -Os.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327733
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Craig Topper [Fri, 16 Mar 2018 18:25:59 +0000 (18:25 +0000)]
[X86] Merge ADDSUB/SUBADD detection into single methods that can detect either and indicate what they found.
Previously, we called the same functions twice with a bool flag determining whether we should look for ADDSUB or SUBADD. It would be more efficient to run the code once and detect either pattern with a flag to tell which type it found.
Differential Revision: https://reviews.llvm.org/D44540
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327730
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Craig Topper [Fri, 16 Mar 2018 18:18:47 +0000 (18:18 +0000)]
[CorrelatedValuePropagation] Use SelectInst::getCondition/getTrueValue/getFalseValue instead of getOperand for readability. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327728
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Farhana Aleen [Fri, 16 Mar 2018 18:12:00 +0000 (18:12 +0000)]
[AMDGPU] Supported ds_write_b128 generation.
Summary: This is a follow-on patch of https://reviews.llvm.org/D44210
Author: FarhanaAleen
Reviewed By: msearles
Subscribers: llvm-commits, AMDGPU
Differential Revision: https://reviews.llvm.org/D44319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327726
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Craig Topper [Fri, 16 Mar 2018 17:13:42 +0000 (17:13 +0000)]
[X86] Post process the DAG after isel to remove vector moves that were added to zero upper bits.
We previously avoided inserting these moves during isel in a few cases which is implemented using a whitelist of opcodes. But it's too difficult to generate a perfect list of opcodes to whitelist. Especially with AVX512F without AVX512VL using 512 bit vectors to implement some 128/256 bit operations. Since isel is done bottoms up, we'd have to check the VT and opcode and subtarget in order to determine whether an EXTRACT_SUBREG would be generated for some operations.
So instead of doing that, this patch adds a post processing step that detects when the moves are unnecesssary after isel. At that point any EXTRACT_SUBREGs would have already been created and appear in the DAG. So then we just need to ensure the input to the move isn't one.
Differential Revision: https://reviews.llvm.org/D44289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327724
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Dmitry Preobrazhensky [Fri, 16 Mar 2018 16:38:04 +0000 (16:38 +0000)]
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
See bug 36751: https://bugs.llvm.org/show_bug.cgi?id=36751
Differential Revision: https://reviews.llvm.org/D44529
Reviewers: artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327723
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Philip Reames [Fri, 16 Mar 2018 16:33:49 +0000 (16:33 +0000)]
[LICM/mustexec] Extend first iteration must execute logic to fcmps
This builds on the work from https://reviews.llvm.org/D44287. It turned out supporting fcmp was much easier than I realized, so let's do that now.
As an aside, our -O3 handling of a floating point IVs leaves a lot to be desired. We do convert the float IV to an integer IV, but do so late enough that many other optimizations are missed (e.g. we don't vectorize).
Differential Revision: https://reviews.llvm.org/D44542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327722
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Andrew V. Tischenko [Fri, 16 Mar 2018 16:06:24 +0000 (16:06 +0000)]
This patch fixes the invalid usage of OptSize in Machine Combiner.
Differential Revision: https://reviews.llvm.org/D43813
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327721
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Dmitry Preobrazhensky [Fri, 16 Mar 2018 15:40:27 +0000 (15:40 +0000)]
[AMDGPU][MC] Corrected default values for unused SDWA operands
See bug 36355: https://bugs.llvm.org/show_bug.cgi?id=36355
Differential Revision: https://reviews.llvm.org/D44481
Reviewers: artem.tamazov, arsenm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327720
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Sanjay Patel [Fri, 16 Mar 2018 15:27:39 +0000 (15:27 +0000)]
[InstCombine] add nnan requirement to potential fabs folds tests; NFC
As noted in D44550, we can't guarantee preserving the sign-bit of NaN
if we convert these to fabs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327718
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Jonas Paulsson [Fri, 16 Mar 2018 15:21:26 +0000 (15:21 +0000)]
[SystemZ] Make AnyRegBitRegClass unallocatable.
AnyReg is just for the assembler and it is better to have it as not
allocatable in order to simplify (make more intuitive) the RegPressureSets.
Review: Ulrich Weigand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327715
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Aditya Nandakumar [Fri, 16 Mar 2018 15:14:18 +0000 (15:14 +0000)]
[GISel]: Remove unused header include in MachineIRBuilder.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327714
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Brian M. Rzycki [Fri, 16 Mar 2018 15:13:47 +0000 (15:13 +0000)]
[JumpThreading] Track unreachable BBs to avoid processing
JumpThreading iterates over F until the IR quiesces. Transforming
unreachable BBs increases compile time and it is also possible to
never stabilize causing JumpThreading to hang. An older attempt at
fixing this problem was D3991 where removeUnreachableBlocks(F)
was called before JumpThreading began. This has a few drawbacks:
* expensive - the routine attempts to fix up the IR to identify
additional BBs that can be removed along with unreachable BBs.
* aggressive - does not identify and preserve the shape of the IR.
At a minimum it does not preserve loop hierarchies.
* invasive - altering reachable blocks it may disrupt IR shapes
that could have otherwise been JumpThreaded.
This patch avoids removeUnreachableBlocks(F) and instead tracks
unreachable BBs in a SmallPtrSet using DominatorTree to validate the
initial state of all BBs. We then rely on subsequent passes to identify
and remove these unreachable blocks from F.
Reviewers: dberlin, sebpop, kuhar, dinesh.d
Reviewed by: sebpop, kuhar
Subscribers: hiraditya, uabelho, llvm-commits
Differential Revision: https://reviews.llvm.org/D44177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327713
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Krzysztof Parzyszek [Fri, 16 Mar 2018 15:03:37 +0000 (15:03 +0000)]
[Hexagon] Fix zero-extending non-HVX bool vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327712
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Mikhail Maltsev [Fri, 16 Mar 2018 14:10:56 +0000 (14:10 +0000)]
[ARM] Convert more invalid NEON immediate loads
Summary:
Currently the LLVM MC assembler is able to convert e.g.
vmov.i32 d0, #0xabababab
(which is technically invalid) into a valid instruction
vmov.i8 d0, #0xab
this patch adds support for vmov.i64 and for cases with the resulting
load types other than i8, e.g.:
vmov.i32 d0, #0xab00ab00 ->
vmov.i16 d0, #0xab00
Reviewers: olista01, rengolin
Reviewed By: rengolin
Subscribers: rengolin, javed.absar, kristof.beyls, rogfer01, llvm-commits
Differential Revision: https://reviews.llvm.org/D44467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327709
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Simon Pilgrim [Fri, 16 Mar 2018 14:01:01 +0000 (14:01 +0000)]
[X86][Btver2] Add correct mul/imul schedule costs
Integer multiply is performed on the JMul function unit and i64 requires double pumping
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327707
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Simon Pilgrim [Fri, 16 Mar 2018 13:43:55 +0000 (13:43 +0000)]
[X86][Btver2] Add correct lzcnt/tzcnt/popcnt schedule costs
Don't use WriteIMul defaults
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327706
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Mikhail Maltsev [Fri, 16 Mar 2018 12:46:49 +0000 (12:46 +0000)]
[ARM] Fix a check in vmov/vmvn immediate parsing
Summary:
Currently the check is incorrect and the following invalid
instruction is accepted and incorrectly assembled:
vmov.i32 d2, #0x00a500a6
This patch fixes the issue.
Reviewers: olista01, rengolin
Reviewed By: rengolin
Subscribers: SjoerdMeijer, javed.absar, rogfer01, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D44460
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327704
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Matthew Simpson [Fri, 16 Mar 2018 11:34:15 +0000 (11:34 +0000)]
[AArch64] Implement getArithmeticReductionCost
This patch provides an implementation of getArithmeticReductionCost for
AArch64. We can specialize the cost of add reductions since they are computed
using the 'addv' instruction.
Differential Revision: https://reviews.llvm.org/D44490
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327702
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Pavel Labath [Fri, 16 Mar 2018 10:30:26 +0000 (10:30 +0000)]
HashTableTest: squelch some "comparison of integers of different signs" warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327701
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Pavel Labath [Fri, 16 Mar 2018 10:02:16 +0000 (10:02 +0000)]
DWARFVerifier: Enhance validation of .debug_names hash tables
Summary:
This patch adds more checks to the .debug_names validator. Specifically,
they check for:
- buckets claiming to be non-empty but pointing to mismatched hashes
(most consumers would interpret this as an empty bucket, but it
questionable whether the generator meant that)
- hashes that are not reachable from any bucket
- names with incorrect hashes
Together, these checks ensure that any name in the index can be reached
through the hash table using the regular lookup algorithm. We also warn
if we encounter a name index without a hash table.
Reviewers: JDevlieghere, aprantl, dblaikie
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327699
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Matthew Simpson [Fri, 16 Mar 2018 10:00:30 +0000 (10:00 +0000)]
[TTI, AArch64] Allow the cost model analysis to test vector reduce intrinsics
This patch considers the experimental vector reduce intrinsics in the default
implementation of getIntrinsicInstrCost. The cost of these intrinsics is
computed with getArithmeticReductionCost and getMinMaxReductionCost. This patch
also adds a test case for AArch64 that indicates the costs we currently compute
for vector reduce intrinsics. These costs are inaccurate and will be updated in
a follow-on patch.
Differential Revision: https://reviews.llvm.org/D44489
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327698
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Sjoerd Meijer [Fri, 16 Mar 2018 08:06:25 +0000 (08:06 +0000)]
[ARM] FP16 codegen support for VSEL
This implements lowering of SELECT_CC for f16s, which enables
codegen of VSEL with f16 types.
Differential Revision: https://reviews.llvm.org/D44518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327695
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Max Kazantsev [Fri, 16 Mar 2018 05:02:24 +0000 (05:02 +0000)]
[NFC] Void variables used for asserts only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327693
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Sanjay Patel [Fri, 16 Mar 2018 01:06:33 +0000 (01:06 +0000)]
[InstCombine] add more tests for fcmp+select -> fabs; NFC
This should correspond to the patterns in D44091 and might
make handling these in the DAG unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327689
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Simon Pilgrim [Thu, 15 Mar 2018 23:46:12 +0000 (23:46 +0000)]
[X86][Btver2] Add support for multiple pipelines stages for x86 scalar schedules. NFCI.
This allows us to use JWriteResIntPair for complex schedule classes (like WriteIDiv) as well as single pipe instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327686
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Simon Pilgrim [Thu, 15 Mar 2018 23:15:11 +0000 (23:15 +0000)]
[X86][Btver2] Tweak pipes test to remove register dependencies
It gives us a better view of pipe usage in the timeline which is what the test is trying to show.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327685
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Craig Topper [Thu, 15 Mar 2018 23:04:11 +0000 (23:04 +0000)]
[SelectionDAG][ARM][X86] Teach PromoteIntRes_SETCC to do a better job picking the result type for the setcc.
Previously if getSetccResultType returned an illegal type we just fell back to using the default promoted type. This appears to have been to handle the case where for vectors getSetccResultType returns the input type, but the input type itself isn't legal and will need to be promoted. Without the legality check we would never reach a legal type.
But just picking the promoted type to be the setcc type can create strange setccs where the result type is 128 bits and the operand type is 256 bits. If for example the result type was promoted to v8i16 from v8i1, but the input type was promoted from v8i23 to v8i32. We currently handle this with custom lowering code in X86.
This legality check also caused us reject the getSetccResultType when the input type needed to be widened or split. Even though that result wouldn't have caused legalization to get stuck.
This patch tries to fix this by detecting the getSetccResultType needs to be promoted. If its input type also needs to be promoted we'll try a ask for a new setcc result type based on its eventual promoted value. Otherwise we fall back to default type to promote to.
For any other illegal values we might get back from the initial call to getSetccResultType we just keep and allow it to be re-legalized later via splitting or widening or scalarizing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327683
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Simon Pilgrim [Thu, 15 Mar 2018 23:00:47 +0000 (23:00 +0000)]
[X86][Btver2] Fix ymm div/sqrt to use fmul unit
YMM FDiv/FSqrt are dispatched on pipe JFPU1 but should be performed on the JFPM unit - that is where most of the cycles are spent.
This matches the pipes for WriteFSqrt/WriteFDiv definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327682
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Sean Silva [Thu, 15 Mar 2018 22:51:55 +0000 (22:51 +0000)]
Use standard `print(dbgs())` pattern to implement DebugLoc::dump
The open-coded implementation had a bug. It didn't print filenames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327681
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Sanjay Patel [Thu, 15 Mar 2018 22:48:23 +0000 (22:48 +0000)]
[InstCombine] add tests for fcmp+select -> fabs; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327680
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Zachary Turner [Thu, 15 Mar 2018 22:47:04 +0000 (22:47 +0000)]
Fix PDB injected sources test.
This test was originally disabled because it was failing on a bot.
It turns out I had run dos2unix on the file, and that removed a
necessary byte from the file. I'm just recomitting the proper
file and updating the test to test a little bit more now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327679
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Simon Pilgrim [Thu, 15 Mar 2018 22:34:24 +0000 (22:34 +0000)]
[X86][Btver2] Add test to show timeline of fpu instructions on different pipes/units
Try to demonstrate the scheduling from fpu0/fpu1 pipes to the valu0/vimul/fpa or valu1/stc/fpm functional units
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327676
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Zachary Turner [Thu, 15 Mar 2018 22:31:00 +0000 (22:31 +0000)]
[PDB] Fix a bug where we were serializing hash tables incorrectly.
There was some code that tried to calculate the number of 4-byte
words required to hold N bits, but it was instead computing the
number of bytes required to hold N bits. This was leading to
extraneous data being output into the hash table, which would
cause certain operations in DIA (the Microsoft PDB reader) to
fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327675
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Derek Schuff [Thu, 15 Mar 2018 22:06:51 +0000 (22:06 +0000)]
[WebAssembly] Add DebugLoc information to WebAssembly block and loop.
Patch by Yury Delendik
Differential Revision: https://reviews.llvm.org/D44448
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327673
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Artem Belevich [Thu, 15 Mar 2018 21:40:56 +0000 (21:40 +0000)]
[NVPTX] TblGen-ized lowering of WMMA intrinsics.
NFC.
Differential Revision: https://reviews.llvm.org/D43151
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327672
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Florian Hahn [Thu, 15 Mar 2018 21:34:43 +0000 (21:34 +0000)]
[LoopUnroll] Peel off iterations if it makes conditions true/false.
If the loop body contains conditions of the form IndVar < #constant, we
can remove the checks by peeling off #constant iterations.
This improves codegen for PR34364.
Reviewers: mkuper, mkazantsev, efriedma
Reviewed By: mkazantsev
Differential Revision: https://reviews.llvm.org/D43876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327671
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Reid Kleckner [Thu, 15 Mar 2018 21:24:04 +0000 (21:24 +0000)]
Re-land r327620 "[CodeView] Initial support for emitting S_BLOCK32 symbols for lexical scopes"
This is safe to land now that we don't copy FunctionInfo when rehashing
the DenseMap.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327670
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Reid Kleckner [Thu, 15 Mar 2018 21:18:42 +0000 (21:18 +0000)]
[codeview] Fix sense of the assertion about hashtable insertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327669
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Zachary Turner [Thu, 15 Mar 2018 21:12:51 +0000 (21:12 +0000)]
Fix structure alignment issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327666
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Reid Kleckner [Thu, 15 Mar 2018 21:12:21 +0000 (21:12 +0000)]
[codeview] Delete FunctionInfo copy ctor and move out of DenseMap
We were unnecessarily copying a bunch of these FunctionInfo objects
around when rehashing the DenseMap.
Furthermore, r327620 introduced pointers referring to objects owned by
FunctionInfo, and the default copy ctor did the wrong thing in this
case, leading to use-after-free when the DenseMap gets rehashed.
I will rebase r327620 on this next and recommit it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327665
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Philip Reames [Thu, 15 Mar 2018 21:04:28 +0000 (21:04 +0000)]
[LICM] Ignore exits provably not taken on first iteration when computing must execute
It is common to have conditional exits within a loop which are known not to be taken on some iterations, but not necessarily all. This patches extends our reasoning around guaranteed to execute (used when establishing whether it's safe to dereference a location from the preheader) to handle the case where an exit is known not to be taken on the first iteration and the instruction of interest *is* known to be taken on the first iteration.
This case comes up in two major ways:
* If we have a range check which we've been unable to eliminate, we frequently know that it doesn't fail on the first iteration.
* Pass ordering. We may have a check which will be eliminated through some sequence of other passes, but depending on the exact pass sequence we might never actually do so or we might miss other optimizations from passes run before the check is finally eliminated.
The initial version (here) is implemented via InstSimplify. At the moment, it catches a few cases, but misses a lot too. I added test cases for missing cases in InstSimplify which I'll follow up on separately. Longer term, we should probably wire SCEV through to here to get much smarter loop aware simplification of the first iteration predicate.
Differential Revision: https://reviews.llvm.org/D44287
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327664
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Evandro Menezes [Thu, 15 Mar 2018 20:37:32 +0000 (20:37 +0000)]
[AArch64] Adjust the cost model for Exynos M3
Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327663
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Evandro Menezes [Thu, 15 Mar 2018 20:31:25 +0000 (20:31 +0000)]
[AArch64] Adjust the cost model for Exynos M3
Add special case for rotate right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327662
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Evandro Menezes [Thu, 15 Mar 2018 20:31:13 +0000 (20:31 +0000)]
[AArch64] Adjust the cost model for Exynos M3
Increase the number of cheap as move cases of register reset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327661
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Craig Topper [Thu, 15 Mar 2018 20:30:54 +0000 (20:30 +0000)]
[X86] Make sure we use FSUB instruction as the reference for operand order in isAddSubOrSubAdd when recognizing subadd
The FADD part of the addsub/subadd pattern can have its operands commuted, but when checking for fsubadd we were using the fadd as reference and commuting the fsub node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327660
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Craig Topper [Thu, 15 Mar 2018 20:30:51 +0000 (20:30 +0000)]
[X86] Add test case showing bad fmsubadd creation due to bad commuting.
The code that creates fmsubadd from shuffle vector has some code to allow commuting the operands of the fadd node. This code was originally created when we only recognized fmaddsub. When fmsubadd support was added this code was not updated and is now commuting the fsub operands instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327659
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David Blaikie [Thu, 15 Mar 2018 20:29:14 +0000 (20:29 +0000)]
Remove empty file
I should've deleted this in r320768 but accidentally just deleted its
contents instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327658
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Reid Kleckner [Thu, 15 Mar 2018 20:12:16 +0000 (20:12 +0000)]
Revert r327620 "[CodeView] Initial support for emitting S_BLOCK32 symbols for lexical scopes"
It is causing crashes when compiling Chrome in debug mode.
I'll try to debug it in a second.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327657
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Diego Caballero [Thu, 15 Mar 2018 19:34:27 +0000 (19:34 +0000)]
[LV] Test commit. Removing white space.
This is just to check that I have commit access privilege.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327656
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Philip Reames [Thu, 15 Mar 2018 18:12:27 +0000 (18:12 +0000)]
[EarlyCSE] Don't hide earler invariant.scopes
If we've already established an invariant scope with an earlier generation, we don't want to hide it in the scoped hash table with one with a later generation. I noticed this when working on the invariant-load handling, but it also applies to the invariant.start case as well.
Without this change, my previous patch for invariant-load regresses some cases, so I'm pushing this without waiting for review. This is why you don't make last minute tweaks to patches to catch "obvious cases" after it's already been reviewed. Bad Philip!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327655
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Zachary Turner [Thu, 15 Mar 2018 17:56:44 +0000 (17:56 +0000)]
Move some function declarations higher so they can be found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327653
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Zachary Turner [Thu, 15 Mar 2018 17:51:10 +0000 (17:51 +0000)]
Add missing #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327652
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Guozhi Wei [Thu, 15 Mar 2018 17:49:12 +0000 (17:49 +0000)]
[PPC] Avoid non-simple MVT in STBRX optimization
PR35402 triggered this case. It bswap and stores a 48bit value, current STBRX optimization transforms it into STBRX. Unfortunately 48bit is not a simple MVT, there is no PPC instruction to support it, and it can't be automatically expanded by llvm, so caused a crash.
This patch detects the non-simple MVT and returns early.
Differential Revision: https://reviews.llvm.org/D44500
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327651
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Simon Pilgrim [Thu, 15 Mar 2018 17:45:10 +0000 (17:45 +0000)]
[X86][Btver2] Attach AES/CLMUL instructions to a scheduler pipe
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327650
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Craig Topper [Thu, 15 Mar 2018 17:38:59 +0000 (17:38 +0000)]
[X86] Simplify the type legality checking for (FM)ADDSUB/SUBADD matching. NFCI
Rather than enumerating all specific types, for the DAG combine we can just use TLI::isTypeLegal and an SSE3 check. For the BUILD_VECTOR version we already know the type is legal so we just need to check SSE3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327649
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Craig Topper [Thu, 15 Mar 2018 17:38:55 +0000 (17:38 +0000)]
[X86] Fix 80 column violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327648
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Zachary Turner [Thu, 15 Mar 2018 17:38:26 +0000 (17:38 +0000)]
Refactor the PDB HashTable class.
It previously only worked when the key and value types were
both 4 byte integers. We now have a use case for a non trivial
value type, so we need to extend it to support arbitrary value
types, which means templatizing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327647
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Philip Reames [Thu, 15 Mar 2018 17:29:32 +0000 (17:29 +0000)]
[EarlyCSE] Reuse invariant scopes for invariant load
This is a follow up to https://reviews.llvm.org/D43716 which rewrites the invariant load handling using the new infrastructure. It's slightly more powerful, but only in somewhat minor ways for the moment. It's not clear that DSE of stores to invariant locations is actually interesting since why would your IR have such a construct to start with?
Note: The submitted version is slightly different than the reviewed one. I realized the scope could start for an invariant load which was proven redundant and removed. Added a test case to illustrate that as well.
Differential Revision: https://reviews.llvm.org/D44497
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327646
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Roman Lebedev [Thu, 15 Mar 2018 16:17:46 +0000 (16:17 +0000)]
[InstSimplify] peek through unsigned FP casts for sign-bit compares (PR36682)
This pattern came up in PR36682 / D44390
https://bugs.llvm.org/show_bug.cgi?id=36682
https://reviews.llvm.org/D44390
https://godbolt.org/g/oKvT5H
See also D44421, D44424
Reviewers: spatel, majnemer, efriedma, arsenm
Reviewed By: spatel
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D44425
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327642
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Roman Lebedev [Thu, 15 Mar 2018 16:17:40 +0000 (16:17 +0000)]
[InstSimplify][NFC] simplifyICmpWithConstant(): refactor GetCompareTy() calls
Preparation for D44425.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327641
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Andrea Di Biagio [Thu, 15 Mar 2018 16:13:12 +0000 (16:13 +0000)]
[llvm-mca] Simplify code. NFC.
Now both method DispatchUnit::checkRAT() and DispatchUnit::canDispatch take as
input an Instruction refrence instead of an instruction descriptor.
This was requested by Simon in D44488 to simplify the diff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327640
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Matthew Simpson [Thu, 15 Mar 2018 16:00:29 +0000 (16:00 +0000)]
[ConstantFolding, InstSimplify] Handle more vector GEPs
This patch addresses some additional cases where the compiler crashes upon
encountering vector GEPs. This should fix PR36116.
Differential Revision: https://reviews.llvm.org/D44219
Reference: https://bugs.llvm.org/show_bug.cgi?id=36116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327638
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Zaara Syeda [Thu, 15 Mar 2018 15:34:41 +0000 (15:34 +0000)]
[PowerPC] Optimize TLS initial-exec sequence to use X-Form loads/stores
This patch adds new load/store instructions for integer scalar types
which can be used for X-Form when fed by add with an @tls relocation.
Differential Revision: https://reviews.llvm.org/D43315
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327635
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Simon Pilgrim [Thu, 15 Mar 2018 15:12:12 +0000 (15:12 +0000)]
[X86][Btver2] Remove JAny resource, and map system/microcoded instructions to JALU pipes
Simplifies throughput to the issue width (1/2) instead of permitting any pipe (1/6)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327632
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Sanjay Patel [Thu, 15 Mar 2018 14:48:39 +0000 (14:48 +0000)]
[InstSimplify] add tests with NaN operand for fp binops; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327631
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Simon Pilgrim [Thu, 15 Mar 2018 14:45:30 +0000 (14:45 +0000)]
[X86][SSE] Introduce Float/Vector WriteMove, WriteLoad and Writetore scheduler classes
As discussed on D44428 and PR36726, this patch splits off WriteFMove/WriteVecMove, WriteFLoad/WriteVecLoad and WriteFStore/WriteVecStore scheduler classes to permit vectors to be handled separately from gpr/scalar types.
I've minimised the diff here by only moving various basic SSE/AVX vector instructions across - we can fix the rest when called for. This does fix the MOVDQA vs MOVAPS/MOVAPD discrepancies mentioned on D44428.
Differential Revision: https://reviews.llvm.org/D44471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327630
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Simon Pilgrim [Thu, 15 Mar 2018 14:30:59 +0000 (14:30 +0000)]
[X86] Regenerate schedule tests with zero latency comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327628
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Sanjay Patel [Thu, 15 Mar 2018 14:29:27 +0000 (14:29 +0000)]
[PatternMatch, InstSimplify] allow undef elements when matching any vector FP zero
This matcher implementation appears to be slightly more efficient than
the generic constant check that it is replacing because every use was
for matching FP patterns, but the previous code would check int and
pointer type nulls too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327627
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Sanjay Patel [Thu, 15 Mar 2018 14:04:31 +0000 (14:04 +0000)]
[InstSimplify] remove 'nsz' requirement for frem 0, X
From the LangRef definition for frem:
"The value produced is the floating-point remainder of the two operands.
This is the same output as a libm ‘fmod‘ function, but without any
possibility of setting errno. The remainder has the same sign as the
dividend. This instruction is assumed to execute in the default
floating-point environment."
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327626
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Sjoerd Meijer [Thu, 15 Mar 2018 13:42:28 +0000 (13:42 +0000)]
[AArch64] Codegen tests for the Armv8.2-A FP16 intrinsics
This is a follow up of the AArch64 FP16 intrinsics work;
the codegen tests had not been added yet.
Differential Revision: https://reviews.llvm.org/D44510
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327624
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Ulrich Weigand [Thu, 15 Mar 2018 12:28:48 +0000 (12:28 +0000)]
[Debug] Retain both copies of debug intrinsics in HoistThenElseCodeToIf
When hoisting common code from the "then" and "else" branches of a condition
to before the "if", the HoistThenElseCodeToIf routine will attempt to merge
the debug location associated with the two original copies of the hoisted
instruction.
This is a problem in the special case where the hoisted instruction is a
debug info intrinsic, since for those the debug location is considered
part of the intrinsic and attempting to modify it may resut in invalid
IR. This is the underlying cause of PR36410.
This patch fixes the problem by handling debug info intrinsics specially:
instead of hoisting one copy and merging the two locations, the code now
simply hoists both copies, each with its original location intact. Note
that this is still only done in the case where both original copies are
otherwise (i.e. apart from location metadata) identical.
Reviewed By: aprantl
Differential Revision: https://reviews.llvm.org/D44312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327622
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Brock Wyma [Thu, 15 Mar 2018 11:52:17 +0000 (11:52 +0000)]
[CodeView] Initial support for emitting S_BLOCK32 symbols for lexical scopes
This patch sorts local variables by lexical scope and emits them inside
an appropriate S_BLOCK32 CodeView symbol.
Differential Revision: https://reviews.llvm.org/D42926
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327620
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Fedor Sergeev [Thu, 15 Mar 2018 11:01:19 +0000 (11:01 +0000)]
[New PM][IRCE] port of Inductive Range Check Elimination pass to the new pass manager
There are two nontrivial details here:
* Loop structure update interface is quite different with new pass manager,
so the code to add new loops was factored out
* BranchProbabilityInfo is not a loop analysis, so it can not be just getResult'ed from
within the loop pass. It cant even be queried through getCachedResult as LoopCanonicalization
sequence (e.g. LoopSimplify) might invalidate BPI results.
Complete solution for BPI will likely take some time to discuss and figure out,
so for now this was partially solved by making BPI optional in IRCE
(skipping a couple of profitability checks if it is absent).
Most of the IRCE tests got their corresponding new-pass-manager variant enabled.
Only two of them depend on BPI, both marked with TODO, to be turned on when BPI
starts being available for loop passes.
Reviewers: chandlerc, mkazantsev, sanjoy, asbirlea
Reviewed By: mkazantsev
Differential Revision: https://reviews.llvm.org/D43795
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327619
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Andrei Elovikov [Thu, 15 Mar 2018 09:59:15 +0000 (09:59 +0000)]
[LoopUnroll] Ignore ephemeral values when checking full unroll profitability.
Summary:
Before this patch call graph is like this in the LoopUnrollPass:
tryToUnrollLoop
ApproximateLoopSize
collectEphemeralValues
/* Use collected ephemeral values */
computeUnrollCount
analyzeLoopUnrollCost
/* Bail out from the analysis if loop contains CallInst */
This patch moves collection of the ephemeral values to the tryToUnrollLoop
function and passes the collected values into both ApproximateLoopsize (as
before) and additionally starts using them in analyzeLoopUnrollCost:
tryToUnrollLoop
collectEphemeralValues
ApproximateLoopSize(EphValues)
/* Use EphValues */
computeUnrollCount(EphValues)
analyzeLoopUnrollCost(EphValues)
/* Ignore ephemeral values - they don't contribute to the final cost */
/* Bail out from the analysis if loop contains CallInst */
Reviewers: mzolotukhin, evstupac, sanjoy
Reviewed By: evstupac
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43931
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327617
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Max Kazantsev [Thu, 15 Mar 2018 09:38:00 +0000 (09:38 +0000)]
[SCEV][NFC] Remove TBB, FBB parameters from exit limit computations
Methods `computeExitLimitFromCondCached` and `computeExitLimitFromCondImpl` take
true and false branches as parameters and only use them for asserts and for identifying
whether true/false branch belongs to the loop (which can be done once earlier). This fact
complicates generalization of exit limit computation logic on guards because the guards
don't have blocks to which they go in case of failure explicitly.
The motivation of this patch is that currently this part of SCEV knows nothing about guards
and only works with explicit branches. As result, it fails to prove that a loop
for (i = 0; i < 100; i++)
guard(i < 10);
exits after 10th iteration, while in the equivalent example
for (i = 0; i < 100; i++)
if (i >= 10) break;
SCEV easily proves this fact. We are going to change it in near future, and this is why
we need to make these methods operate on more abstract level.
This patch refactors this code to get rid of these parameters as meaningless and prepare
ground for teaching these methods to work with guards as well as they work with explicit
branching instructions.
Differential Revision: https://reviews.llvm.org/D44419
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327615
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Craig Topper [Thu, 15 Mar 2018 06:49:01 +0000 (06:49 +0000)]
[X86] Add test cases for 512-bit addsub from build_vector.
There is no 512 bit addsub instruction, but we partially match it handle fmaddsub matching. We explicitly bail out for 512 bit vectors after failing the fmaddsub match, but we had no test coverage for that bail out.
We might want to consider splitting and using 256 bit instructions instead of the long sequence seen here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327605
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Craig Topper [Thu, 15 Mar 2018 06:14:55 +0000 (06:14 +0000)]
[X86] Add support for matching FMSUBADD from build_vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327604
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Craig Topper [Thu, 15 Mar 2018 06:14:53 +0000 (06:14 +0000)]
[X86] Remove old TODO. We have coverage for this now.
Coverage was added in r320950.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327603
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Craig Topper [Thu, 15 Mar 2018 06:14:51 +0000 (06:14 +0000)]
[X86] Use MVT in a couple places where we know the type is legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327602
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Aaron Smith [Thu, 15 Mar 2018 06:04:51 +0000 (06:04 +0000)]
[DebugInfo] Add a new method IPDBSession::findLineNumbersBySectOffset
Summary:
Some PDB symbols do not have a valid VA or RVA but have Addr by Section and Offset. For example, a variable in thread-local storage has the following properties:
get_addressOffset: 0
get_addressSection: 5
get_lexicalParentId: 2
get_name: g_tls
get_symIndexId: 12
get_typeId: 4
get_dataKind: 6
get_symTag: 7
get_locationType: 2
This change provides a new method to locate line numbers by Section and Offset from those symbols.
Reviewers: zturner, rnk, llvm-commits
Subscribers: asmith, JDevlieghere
Differential Revision: https://reviews.llvm.org/D44407
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327601
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Lei Huang [Thu, 15 Mar 2018 03:06:44 +0000 (03:06 +0000)]
[PowerPC][NFC] formatting-only fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327599
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George Burgess IV [Thu, 15 Mar 2018 02:58:36 +0000 (02:58 +0000)]
Remove unused variable; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327597
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Lang Hames [Thu, 15 Mar 2018 00:30:14 +0000 (00:30 +0000)]
[ORC] Re-apply r327566 with a fix for test-global-ctors.ll.
Also clang-formats the patch, which I should have done the first time around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327594
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Matt Davis [Wed, 14 Mar 2018 23:30:31 +0000 (23:30 +0000)]
[CleanUp] Remove NumInstructions field from LoopVectorizer's RegisterUsage struct.
Summary:
This variable is largely going unused; aside from reporting number of instructions for in DEBUG builds.
The only use of NumInstructions is in debug output to represent the LoopSize. That value can be can be misleading as it also includes metadata instructions (e.g., DBG_VALUE) which have no real impact. If we do choose to keep this around, we probably should guard it by a DEBUG macro, as it's not used in production builds.
Reviewers: majnemer, congh, rengolin
Reviewed By: rengolin
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D44495
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327589
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Simon Pilgrim [Wed, 14 Mar 2018 23:12:09 +0000 (23:12 +0000)]
[X86][Btver2] Add support for multiple pipelines stages for fpu schedules. NFCI.
This allows us to use JWriteResFpuPair for complex schedule classes as well as single pipe instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327588
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