OSDN Git Service
Richard Osborne [Sun, 5 May 2013 13:20:22 +0000 (13:20 +0000)]
[XCore] Remove '-' from back branch asm syntax.
Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151
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Benjamin Kramer [Sun, 5 May 2013 11:29:14 +0000 (11:29 +0000)]
InlineSpiller: Remove quadratic behavior.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181149
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Stepan Dyatkovskiy [Sun, 5 May 2013 07:48:36 +0000 (07:48 +0000)]
For ARM backend, fixed "byval" attribute support.
Now even the small structures could be passed within byval (small enough
to be stored in GPRs).
In regression tests next function prototypes are checked:
PR15293:
%artz = type { i32 }
define void @foo(%artz* byval %s)
define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2)
foo: "s" stored in R0
foo2: "s" stored in R0, "s2" stored in R2.
Next AAPCS rules are checked:
5.5 Parameters Passing, C.4 and C.5,
"ParamSize" is parameter size in 32bit words:
-- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4.
Parameter should be sent to the stack; NCRN := R4.
-- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4.
Parameter stored in GPRs; NCRN += ParamSize.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181148
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Arnold Schwaighofer [Sun, 5 May 2013 02:14:28 +0000 (02:14 +0000)]
Add missing PatternMatch.cpp to CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181147
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Arnold Schwaighofer [Sun, 5 May 2013 02:01:41 +0000 (02:01 +0000)]
PatternMatch: Fix documentation - 'function' not 'attribute'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181146
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David Majnemer [Sun, 5 May 2013 02:00:10 +0000 (02:00 +0000)]
Remove a recently redundant transform from X86ISelLowering.
X86ISelLowering has support to treat:
(icmp ne (and (xor %flags, -1), (shl 1, flag)), 0)
as if it were actually:
(icmp eq (and %flags, (shl 1, flag)), 0)
However, r179386 has code at the InstCombine level to handle this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181145
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Arnold Schwaighofer [Sun, 5 May 2013 01:54:48 +0000 (01:54 +0000)]
LoopVectorize: Add support for floating point min/max reductions
Add support for min/max reductions when "no-nans-float-math" is enabled. This
allows us to assume we have ordered floating point math and treat ordered and
unordered predicates equally.
radar://
13723044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181144
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Arnold Schwaighofer [Sun, 5 May 2013 01:54:46 +0000 (01:54 +0000)]
PatternMatch: Matcher for (un)ordered floating point min/max
Add support for matching 'ordered' and 'unordered' floating point min/max
constructs.
In LLVM we can express min/max functions as a combination of compare and select.
We have support for matching such constructs for integers but not for floating
point. In floating point math there is no total order because of the presence of
'NaN'. Therefore, we have to be careful to preserve the original fcmp semantics
when interpreting floating point compare select combinations as a minimum or
maximum function. The resulting 'ordered/unordered' floating point maximum
function has to select the same value as the select/fcmp combination it is based
on.
ordered_max(x,y) = max(x,y) iff x and y are not NaN, y otherwise
unordered_max(x,y) = max(x,y) iff x and y are not NaN, x otherwise
ordered_min(x,y) = min(x,y) iff x and y are not NaN, y otherwise
unordered_min(x,y) = min(x,y) iff x and y are not NaN, x otherwise
This matches the behavior of the underlying select(fcmp(olt/ult/.., L, R), L, R)
construct.
Any code using this predicate has to preserve this semantics.
A follow-up patch will use this to implement floating point min/max reductions
in the vectorizer.
radar://
13723044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181143
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Arnold Schwaighofer [Sun, 5 May 2013 01:54:44 +0000 (01:54 +0000)]
LoopVectorizer: Cleanup of miminimum/maximum pattern match code
No need for setting the operands. The pointers are going to be bound by the
matcher.
radar://
13723044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181142
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Arnold Schwaighofer [Sun, 5 May 2013 01:54:42 +0000 (01:54 +0000)]
LoopVectorize: We don't need an identity element for min/max reductions
We can just use the initial element that feeds the reduction.
max(max(x, y), z) == max(max(x,y), max(x,z))
radar://
13723044
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181141
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Dmitri Gribenko [Sun, 5 May 2013 00:40:33 +0000 (00:40 +0000)]
Add ArrayRef constructor from None, and do the cleanups that this constructor enables
Patch by Robert Wilhelm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181138
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Nadav Rotem [Sat, 4 May 2013 23:27:32 +0000 (23:27 +0000)]
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181137
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Nadav Rotem [Sat, 4 May 2013 23:24:56 +0000 (23:24 +0000)]
Fix an odd comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181136
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Tim Northover [Sat, 4 May 2013 20:14:22 +0000 (20:14 +0000)]
AArch64: enable MCJIT and tests now that everything passes.
This removes dire warnings about AArch64 being unsupported and enables
the tests when appropriate on this platform.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181135
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Tim Northover [Sat, 4 May 2013 20:14:14 +0000 (20:14 +0000)]
AArch64: implement 64-bit absolute relocation in MCJIT
This is about the simplest relocation, but surprisingly rare in actual
code.
It occurs in (for example) the MCJIT test test-ptr-reloc.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181134
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Tim Northover [Sat, 4 May 2013 20:14:09 +0000 (20:14 +0000)]
AArch64: add stubs to support long function calls on MCJIT
As with global accesses, external functions could exist anywhere in
memory. Therefore the stub must create a complete 64-bit address. This
patch implements the fragment as (roughly):
movz x16, #:abs_g3:somefunc
movk x16, #:abs_g2_nc:somefunc
movk x16, #:abs_g1_nc:somefunc
movk x16, #:abs_g0_nc:somefunc
br x16
In principle we could save 4 bytes by using a literal-load instead,
but it is unclear that would be more efficient and can only be tested
when real hardware is readily available.
This allows (for example) the MCJIT test 2003-05-07-ArgumentTest to
pass on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181133
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Tim Northover [Sat, 4 May 2013 20:14:04 +0000 (20:14 +0000)]
AArch64: implement relocations for global access
The large memory model (default and main viable for JIT) emits
addresses in need of relocation as
movz x0, #:abs_g3:somewhere
movk x0, #:abs_g2_nc:somewhere
movk x0, #:abs_g1_nc:somewhere
movk x0, #:abs_g0_nc:somewhere
To support this we must implement those four relocations in the
dynamic loader.
This allows (for example) the test-global.ll MCJIT test to pass on
AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181132
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Tim Northover [Sat, 4 May 2013 20:13:59 +0000 (20:13 +0000)]
AArch64: implement first relocation required for MCJIT
R_AARCH64_PCREL32 is present in even trivial .eh_frame sections and so
is required to compile any function without the "nounwind" attribute.
This change implements very basic infrastructure in the RuntimeDyldELF
file and allows (for example) the test-shift.ll MCJIT test to pass
on AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181131
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Tim Northover [Sat, 4 May 2013 20:13:52 +0000 (20:13 +0000)]
Build system changes to enable MCJIT on AArch64
These changes just allow AArch64 to take part in the MCJIT world when
built correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181130
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Tim Northover [Sat, 4 May 2013 18:52:44 +0000 (18:52 +0000)]
AArch64: use __clear_cache under GCCish environments
AArch64 is going to need some kind of cache-invalidation in order to
successfully JIT since it has a weak memory-model. This is provided by
a __clear_cache builtin in libgcc, which acts very much like the
32-bit ARM equivalent (on platforms where it exists).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181129
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Richard Osborne [Sat, 4 May 2013 17:41:01 +0000 (17:41 +0000)]
Fix buildbot failure on 64 bit linux due to std::max() having different
operand types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181128
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Richard Osborne [Sat, 4 May 2013 17:30:05 +0000 (17:30 +0000)]
[XCore] Remove unused operand type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181127
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Richard Osborne [Sat, 4 May 2013 17:24:33 +0000 (17:24 +0000)]
[XCore] Make use of the target independent global address offset folding.
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126
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Richard Osborne [Sat, 4 May 2013 17:17:10 +0000 (17:17 +0000)]
[XCore] Simplify code that checks for an aligned base plus a constant.
The code now makes use of ComputeMaskedBits,
SelectionDAG::isBaseWithConstantOffset and TargetLowering::isGAPlusOffset
where appropriate reducing the amount of logic needed in XCoreISelLowering.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181125
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Richard Osborne [Sat, 4 May 2013 17:01:55 +0000 (17:01 +0000)]
[XCore] Move lowering of thread local storage to a separate pass.
Thread local storage is not supported by the XMOS linker so we handle
thread local variables by lowering the variable to an array of n elements
(where n is the number of hardware threads per core, currently 8
for all XMOS devices) indexed by the the current thread ID.
Previously this lowering was spread across the XCoreISelLowering and the
XCoreAsmPrinter classes. Moving this to a separate pass should be much
cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181124
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Tim Northover [Sat, 4 May 2013 16:54:11 +0000 (16:54 +0000)]
AArch64: assert code model is small for TLS accesses
Supporting TLS in the large memory model is rather difficult at the
moment, so make sure no-one gets into difficulties by mistake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181121
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Tim Northover [Sat, 4 May 2013 16:54:07 +0000 (16:54 +0000)]
AArch64: support literal pool access in large memory model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181120
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Tim Northover [Sat, 4 May 2013 16:54:00 +0000 (16:54 +0000)]
AArch64: support large code model for jump-tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181119
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Tim Northover [Sat, 4 May 2013 16:53:53 +0000 (16:53 +0000)]
AArch64: implement support for blockaddress in large code model
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181118
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Tim Northover [Sat, 4 May 2013 16:53:46 +0000 (16:53 +0000)]
AArch64: implement large code model access to global variables.
The MOVZ/MOVK instruction sequence may not be the most efficient (a
literal-pool load could be better) but adding that would require
reinstating the ConstantIslands pass.
For now the sequence is correct, and that's enough. Beware, as of
commit GNU ld does not appear to support the relocations needed for
this. Its primary purpose (for now) will be to support JITed code,
since in that case there is no guarantee of where your code will end
up in memory relative to external symbols it references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181117
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Richard Osborne [Sat, 4 May 2013 16:40:58 +0000 (16:40 +0000)]
[XCore] Use static relocation model by default.
This allows us to get get rid of a hack in XCoreTargetObjectFile where the
the DataRel* sections were overridden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181116
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Tim Northover [Sat, 4 May 2013 07:36:23 +0000 (07:36 +0000)]
Allow host triple to be correctly overridden in CMake builds
The intended semantics mirror autoconf, where the user is able to
specify a host triple, but if it's left to the build system then
"config.guess" is invoked for the default.
This also renames the LLVM_HOSTTRIPLE define to LLVM_HOST_TRIPLE to
fit in with the style of the surrounding defines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181112
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Rafael Espindola [Sat, 4 May 2013 05:30:49 +0000 (05:30 +0000)]
Optimize llvm-link too.
This takes the linking of almost all modules in a clang build from 6:32
to 0:19.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181105
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Rafael Espindola [Sat, 4 May 2013 05:05:18 +0000 (05:05 +0000)]
Fix a performance bug in the Linker.
Now that we hava a convinient place to keep it, remeber the set of
identified structs as we merge modules.
This speeds up the linking of all the bitcode files in clang with the
gold plugin and -plugin-opt=emit-llvm (i.e., link only, no codegen) from
5:25 minutes to 13.6 seconds!
Patch by Xiaofei Wan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181104
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Rafael Espindola [Sat, 4 May 2013 04:08:02 +0000 (04:08 +0000)]
Implement Linker::LinkModules with Linker::linkInModule.
Flipping which one is the implementation will let us optimize linkInModule.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181102
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Rafael Espindola [Sat, 4 May 2013 03:48:37 +0000 (03:48 +0000)]
Now that Linker.cpp is almost empty, merge it into LinkModules.cpp.
Also remove unused includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181100
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Rafael Espindola [Sat, 4 May 2013 03:06:50 +0000 (03:06 +0000)]
Last batch of cleanups to Linker.h.
Update comments, fix * placement, fix method names that are not
used in clang, add a linkInModule that takes a Mode and put it
in Linker.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181099
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Rafael Espindola [Sat, 4 May 2013 02:43:00 +0000 (02:43 +0000)]
Don't construct or delete a module on the Linker.
The linker is now responsible only for actually linking the modules, it
is up to the clients to create and destroy them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181098
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Rafael Espindola [Sat, 4 May 2013 02:34:41 +0000 (02:34 +0000)]
Don't store the context in the Linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181097
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Rafael Espindola [Sat, 4 May 2013 02:28:57 +0000 (02:28 +0000)]
Remove unused members and constructor arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181096
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Rafael Espindola [Sat, 4 May 2013 02:21:46 +0000 (02:21 +0000)]
Add missing header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181095
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Rafael Espindola [Sat, 4 May 2013 02:13:18 +0000 (02:13 +0000)]
Delete dead code from the linker.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181094
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Krzysztof Parzyszek [Sat, 4 May 2013 01:30:49 +0000 (01:30 +0000)]
Use consistent function names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181090
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Nick Lewycky [Sat, 4 May 2013 01:08:15 +0000 (01:08 +0000)]
Tabs to spaces. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181082
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Amara Emerson [Fri, 3 May 2013 23:57:17 +0000 (23:57 +0000)]
Revert r181009.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181079
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Reed Kotler [Fri, 3 May 2013 23:17:24 +0000 (23:17 +0000)]
Remove some uneeded pseudos in the presence of the naked function attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181072
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Amara Emerson [Fri, 3 May 2013 22:39:03 +0000 (22:39 +0000)]
Delete test instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181066
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Amara Emerson [Fri, 3 May 2013 22:27:48 +0000 (22:27 +0000)]
Temporarily disable failing test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181062
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Bill Wendling [Fri, 3 May 2013 21:53:50 +0000 (21:53 +0000)]
Remove this hack. We can support this better with function attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181059
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Ulrich Weigand [Fri, 3 May 2013 19:53:04 +0000 (19:53 +0000)]
[PowerPC] Avoid using '$' in generated assembler code
PowerPC assemblers are supposed to support a stand-alone '$' symbol
as an alternative of '.' to refer to the current PC. This does not
work in the LLVM assembler parser yet.
To avoid bootstrap failures when using the LLVM assembler as system
assembler, this patch modifies the assembler source code generated
by LLVM to avoid using '$' (and simply use '.' instead).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181054
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Ulrich Weigand [Fri, 3 May 2013 19:52:35 +0000 (19:52 +0000)]
[PowerPC] Parse platform-specifc variant kinds in AsmParser
This patch adds support for PowerPC platform-specific variant
kinds in MCSymbolRefExpr::getVariantKindForName, and also
adds a test case to verify they are translated to the appropriate
fixup type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181053
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Ulrich Weigand [Fri, 3 May 2013 19:51:09 +0000 (19:51 +0000)]
[PowerPC] Add some Book II instructions to AsmParser
This patch adds a couple of Book II instructions (isync, icbi) to the
PowerPC assembler parser. These are needed when bootstrapping clang
with the integrated assembler forced on, because they are used in
inline asm statements in the code base.
The test case adds the full list of Book II storage control instructions,
including associated extended mnemonics. Again, those that are not yet
supported as marked as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052
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Ulrich Weigand [Fri, 3 May 2013 19:50:27 +0000 (19:50 +0000)]
[PowerPC] Support extended mnemonics in AsmParser
This patch adds infrastructure to support extended mnemonics in the
PowerPC assembler parser. It adds support specifically for those
extended mnemonics that LLVM will itself generate.
The test case lists *all* extended mnemonics according to the
PowerPC ISA v2.06 Book I, but marks those not yet supported
as FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051
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Ulrich Weigand [Fri, 3 May 2013 19:49:39 +0000 (19:49 +0000)]
[PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.
The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux. The supported syntax is
intended to be compatible with the GNU assembler.
The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.
Instruction operands will be checked for validity and errors
generated. (Error handling in general could still be improved.)
The patch adds a number of test cases to verify instruction
and operand encodings. The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector.
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.
A number of follow-on check-ins will add extra features. When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050
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Shuxin Yang [Fri, 3 May 2013 19:17:26 +0000 (19:17 +0000)]
Decompose GVN::processNonLocalLoad() (about 400 LOC) into smaller helper functions. No function change.
This function consists of following steps:
1. Collect dependent memory accesses.
2. Analyze availability.
3. Perform fully redundancy elimination, or
4. Perform PRE, depending on the availability
Step 2, 3 and 4 are now moved to three helper routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181047
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Akira Hatanaka [Fri, 3 May 2013 18:37:49 +0000 (18:37 +0000)]
[mips] Split the DSP control register and define one register for each field of
its fields.
This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041
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Nadav Rotem [Fri, 3 May 2013 17:42:55 +0000 (17:42 +0000)]
LoopVectorizer: Add support for if-conversion of PHINodes with 3+ incoming values.
By supporting the vectorization of PHINodes with more than two incoming values we can increase the complexity of nested if statements.
We can now vectorize this loop:
int foo(int *A, int *B, int n) {
for (int i=0; i < n; i++) {
int x = 9;
if (A[i] > B[i]) {
if (A[i] > 19) {
x = 3;
} else if (B[i] < 4 ) {
x = 4;
} else {
x = 5;
}
}
A[i] = x;
}
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181037
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Tom Stellard [Fri, 3 May 2013 17:21:31 +0000 (17:21 +0000)]
R600: Expand vector or, shl, srl, and xor nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035
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Tom Stellard [Fri, 3 May 2013 17:21:24 +0000 (17:21 +0000)]
R600: BFI_INT is a vector-only instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181034
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Tom Stellard [Fri, 3 May 2013 17:21:20 +0000 (17:21 +0000)]
R600: Add pattern for SHA-256 Ma function
This can be optimized using the BFI_INT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033
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Tom Stellard [Fri, 3 May 2013 17:21:14 +0000 (17:21 +0000)]
R600: Clean up comments in Processors.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181032
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Benjamin Kramer [Fri, 3 May 2013 15:55:06 +0000 (15:55 +0000)]
Autoconf: Compile cxxabi.h in C++ mode.
Should fix PR15877.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181026
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Tobias Grosser [Fri, 3 May 2013 15:48:34 +0000 (15:48 +0000)]
RegionInfo: Do not crash if unreachable block is found
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181025
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Benjamin Kramer [Fri, 3 May 2013 14:48:29 +0000 (14:48 +0000)]
CMake: cxxabi.h is only available to C++ compilers, use the right check macro.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181019
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Richard Sandiford [Fri, 3 May 2013 14:32:27 +0000 (14:32 +0000)]
Remove comment that no target supports 128-bit IEEE floats
The soon-to-be-committed SystemZ port uses 128-bit IEEE floats.
MIPS64 GNU/Linux does too (albeit with unusual NaNs).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181016
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Richard Sandiford [Fri, 3 May 2013 14:15:35 +0000 (14:15 +0000)]
[SystemZ] Add MCJIT support
Another step towards reinstating the SystemZ backend. I'll commit
the configure changes separately (TARGET_HAS_JIT etc.), then commit
a patch to enable the MCJIT tests on SystemZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181015
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Ulrich Weigand [Fri, 3 May 2013 12:22:11 +0000 (12:22 +0000)]
[SystemZ] Support System Z as host architecture
The llvm::sys::AddSignalHandler function (as well as related routines) in
lib/Support/Unix/Signals.inc currently registers a signal handler routine
via "sigaction". When this handler is called due to a SIGSEGV, SIGILL or
similar signal, it will show a stack backtrace, deactivate the handler,
and then simply return to the operating system. The intent is that the
OS will now retry execution at the same location as before, which ought
to again trigger the same error condition and cause the same signal to be
delivered again. Since the hander is now deactivated, the OS will take
its default action (usually, terminate the program and possibly create
a core dump).
However, this method doesn't work reliably on System Z: With certain
signals (namely SIGILL, SIGFPE, and SIGTRAP), the program counter stored
by the kernel on the signal stack frame (which is the location where
execution will resume) is not the instruction that triggered the fault,
but then instruction *after it*. When the LLVM signal handler simply
returns to the kernel, execution will then resume at *that* address,
which will not trigger the problem again, but simply go on and execute
potentially unrelated code leading to random errors afterwards.
To fix this, the patch simply goes and re-raises the signal in question
directly from the handler instead of returning from it. This is done
only on System Z and only for those signals that have this particular
problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181010
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Amara Emerson [Fri, 3 May 2013 11:36:35 +0000 (11:36 +0000)]
Add support for reading ARM ELF build attributes.
Build attribute sections can now be read if they exist via ELFObjectFile, and
the llvm-readobj tool has been extended with an option to dump this information
if requested. Regression tests are also included which exercise these features.
Also update the docs with a fixed ARM ABI link and a new link to the Addenda
which provides the build attributes specification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181009
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Richard Sandiford [Fri, 3 May 2013 11:11:15 +0000 (11:11 +0000)]
[SystemZ] Add ELF relocation support
Another step towards reinstating the SystemZ backend. Tests will be
included in the main backend patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181008
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Richard Sandiford [Fri, 3 May 2013 11:05:17 +0000 (11:05 +0000)]
[SystemZ] Add llvm::Triple::systemz
First step towards reinstating the SystemZ backend. Tests will be
included in the main backend patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181007
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Benjamin Kramer [Fri, 3 May 2013 10:20:08 +0000 (10:20 +0000)]
X86: Add target description for btver2; make autodetection logic aware of AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181005
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Pekka Jaaskelainen [Fri, 3 May 2013 07:37:04 +0000 (07:37 +0000)]
Added pocl and TCE blurbs to the ReleaseNotes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181001
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Aaron Ballman [Fri, 3 May 2013 02:52:21 +0000 (02:52 +0000)]
Unbreaking the non-x86 build bots by protecting the AVX test code properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180992
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Aaron Ballman [Fri, 3 May 2013 02:39:21 +0000 (02:39 +0000)]
Correctly testing for AVX support in x86 based off code from Hosts.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180991
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Akira Hatanaka [Fri, 3 May 2013 01:29:31 +0000 (01:29 +0000)]
[mips] Remove "Commutative" from property list of non-commutative intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180988
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Reid Kleckner [Fri, 3 May 2013 00:54:56 +0000 (00:54 +0000)]
Fix missing include in Hexagon code for Release+Asserts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983
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John McCall [Fri, 3 May 2013 00:15:41 +0000 (00:15 +0000)]
In MC asm parsing, account for the possibility of whitespace within
the "identifier" parsed by the frontend callback by skipping forward
until we've consumed a token that ends at the point dictated by the
callback.
In addition, inform the callback when it's parsing an unevaluated
operand (e.g. mov eax, LENGTH A::x) as opposed to an evaluated one
(e.g. mov eax, [A::x]).
This commit depends on a clang commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180978
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Akira Hatanaka [Thu, 2 May 2013 23:07:05 +0000 (23:07 +0000)]
[mips] Handle reading, writing or copying of ccond field of DSP control
register.
- Define pseudo instructions which store or load ccond field of the DSP
control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969
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Bill Wendling [Thu, 2 May 2013 22:52:47 +0000 (22:52 +0000)]
Remove redundant flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180967
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Jyotsna Verma [Thu, 2 May 2013 22:10:59 +0000 (22:10 +0000)]
reverting r180953
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964
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Vincent Lejeune [Thu, 2 May 2013 21:53:03 +0000 (21:53 +0000)]
R600: Signed literals are 64bits wide
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180960
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Vincent Lejeune [Thu, 2 May 2013 21:52:55 +0000 (21:52 +0000)]
R600: If previous bundle is dot4, PV valid chan is always X
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959
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Vincent Lejeune [Thu, 2 May 2013 21:52:46 +0000 (21:52 +0000)]
R600: Add a test to check that use_kill is emitted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180958
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Vincent Lejeune [Thu, 2 May 2013 21:52:40 +0000 (21:52 +0000)]
R600: Improve asmPrint of ALU clause
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957
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Vincent Lejeune [Thu, 2 May 2013 21:52:30 +0000 (21:52 +0000)]
R600: Prettier asmPrint of Alu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956
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Jyotsna Verma [Thu, 2 May 2013 21:21:57 +0000 (21:21 +0000)]
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953
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Shuxin Yang [Thu, 2 May 2013 21:14:31 +0000 (21:14 +0000)]
[GV] Remove dead code which is really difficult to decipher.
Actually it took me couple of hours trying to make sense of them and
only to find they are dead code. I guess the original author used
"allSingleSucc" to indicate if there are any critial edge emanating
from some blocks, and tried to perform code motion (actually speculation)
in the presence of these critical edges; but later on he/she changed mind
and decided to perform edge-splitting first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180951
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Bill Wendling [Thu, 2 May 2013 21:09:03 +0000 (21:09 +0000)]
We don't want FP elimination when doing an Apple-style build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180949
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Aaron Ballman [Thu, 2 May 2013 20:30:27 +0000 (20:30 +0000)]
Replaced usages of size_type with size_t to be more consistent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180947
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Pranav Bhandarkar [Thu, 2 May 2013 20:22:51 +0000 (20:22 +0000)]
Hexagon - Add peephole optimizations for zero extends.
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
sequence of a pair of i32->i64 extensions followed by a "bitwise or"
into COMBINE_rr.
* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
* test/CodeGen/Hexagon/union-1.ll: New test.
* test/CodeGen/Hexagon/combine_ir.ll: Fix test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946
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Richard Sandiford [Thu, 2 May 2013 18:28:03 +0000 (18:28 +0000)]
[mips] Fix the head Mips16RegisterInfo.cpp comment
...aka a test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180936
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Manman Ren [Thu, 2 May 2013 18:11:35 +0000 (18:11 +0000)]
TBAA: remove !tbaa from testing cases if not used.
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180935
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Adrian Prantl [Thu, 2 May 2013 17:27:49 +0000 (17:27 +0000)]
Provide an API to temporarily suppress DebugLocations from being attached
to emitted instructions. Use this if you want an instruction to be
counted towards the prologue or if there is no useful source location.
rdar://problem/
13442648
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180929
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Jyotsna Verma [Thu, 2 May 2013 15:39:30 +0000 (15:39 +0000)]
Hexagon: Honor __builtin_expect by using branch probabilities.
* lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
Given a jump opcode return the right pred.new jump opcode with
a taken vs not-taken hint based on branch probabilities provided
by the target independent module.
* lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
* lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
Enhance existing function use branch probabilities like
HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180923
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Tom Stellard [Thu, 2 May 2013 15:30:12 +0000 (15:30 +0000)]
R600: Use new tablegen syntax for patterns
All but two patterns have been converted to the new syntax. The
remaining two patterns will require COPY_TO_REGCLASS instructions, which
the VLIW DAG Scheduler cannot handle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180922
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Tom Stellard [Thu, 2 May 2013 15:30:07 +0000 (15:30 +0000)]
R600/SI: remove nonsense select pattern
Fortunately this pattern never matched, otherwise
we would have generated incorrect code.
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180921
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Tobias Grosser [Thu, 2 May 2013 14:59:52 +0000 (14:59 +0000)]
Added table of contents declaration in CommandLine Library documentation.
Contributed-by: Dan Liew <daniel.liew@imperial.ac.uk>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180919
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Michael Liao [Thu, 2 May 2013 09:22:04 +0000 (09:22 +0000)]
80-col fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180915
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Michael Liao [Thu, 2 May 2013 09:18:38 +0000 (09:18 +0000)]
Avoid duplicating logic on frame register selecting when lowering eh_return
No functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180914
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Michael Liao [Thu, 2 May 2013 08:21:56 +0000 (08:21 +0000)]
Avoid duplicating logic on frame register selecting when lowering frameaddr
No functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180912
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