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Emil Velikov [Mon, 17 Apr 2017 13:42:37 +0000 (14:42 +0100)]
docs: add sha256 checksums for 17.0.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 17 Apr 2017 13:38:04 +0000 (14:38 +0100)]
docs: add release notes for 17.0.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 17 Apr 2017 13:33:57 +0000 (14:33 +0100)]
Update version to 17.0.4
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Fabio Estevam [Sat, 4 Mar 2017 22:07:27 +0000 (19:07 -0300)]
loader: Move non-error message to debug level
Currently when running mesa on imx6 the following loader warnings
are seen:
MESA-LOADER: device is not located on the PCI bus
MESA-LOADER: device is not located on the PCI bus
MESA-LOADER: device is not located on the PCI bus
Using display 0x1920948 with EGL version 1.4
As this is not an error message, change it to debug level in
order to have a cleaner log output.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
78c57726335fe22cb4579bcf562d2394adc234b5)
Nominated-by: Rob Clark <robdclark@gmail.com> (IRC)
Alex Smith [Thu, 30 Mar 2017 19:03:58 +0000 (21:03 +0200)]
radv: Invalidate L2 for TRANSFER_WRITE barriers
CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write
through L2. Therefore, to make these writes visible to later accesses
we must invalidate L2 rather than just writing it back, to avoid the
possibility that stale data is read through L2.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
[Bas: patch is a backport for 17.0 of the cherry-pick below]
(cherry picked from commit
bc5d587a80b64fb3e0a5ea8067e6317fbca2bbc5)
Julien Isorce [Wed, 15 Mar 2017 17:40:25 +0000 (17:40 +0000)]
radeon_drm_bo: explicitly check return value of drmCommandWriteRead
CID
1313492
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
521860b2a92bab6394546e6af8709c07e2292033)
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
Julien Isorce [Mon, 27 Feb 2017 13:42:17 +0000 (13:42 +0000)]
radeon: initialize hole variable before calling container_of
Like in a few other places in that radeon_drm_bo.c file.
CID 715739.
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
ce27b27c38acd5a92cf45e7ddc2434f2c04191ee)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99515
Nominated-by: Mauro Rossi <issor.oruam@gmail.com>
Julien Isorce [Fri, 10 Mar 2017 17:20:56 +0000 (17:20 +0000)]
winsys/radeon: check null return from radeon_cs_create_fence in cs_flush
Follow-up of patch:
"radeon_cs_create_fence: check null return from radeon_winsys_bo_create"
radeon_drm_cs_flush
radeon_cs_create_fence
radeon_winsys_bo_create
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
d08c0930af8aaef5bdf80df618bb906e0b349830)
[Emil Velikov: resolve trivial conflicts]
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/winsys/radeon/drm/radeon_drm_cs.c
Julien Isorce [Fri, 10 Mar 2017 17:16:05 +0000 (17:16 +0000)]
winsys/radeon: check null in radeon_cs_create_fence
Fixes the following segmentation fault:
radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c
-> if (!bo->handle)
(gdb) bt
0 radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c
1 0x00007fffe73575de in radeon_cs_create_fence radeon_drm_cs.c
2 0x00007fffe7358c48 in radeon_drm_cs_flush radeon_drm_cs.c
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
d09edb01468ca385b6a8ffe29ac434dc42a78d07)
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Wed, 12 Apr 2017 11:05:25 +0000 (12:05 +0100)]
Revert "freedreno: fix memory leak"
This reverts commit
c57a03585052e3bd7d61d1307cae9a922e663c20.
As requested by Rob Clark
"This seems to be causing a performance regression (reported by
Nicolas).. and the leak it fixes is quite hypothetical. (Ie. hit by
apps that destroy/create context many times.)
On master, I think this can be solved by switching on 'reorder' by
default but that is probably too much of a behaviour change for
stable."
Jerome Duval [Wed, 22 Feb 2017 16:02:51 +0000 (16:02 +0000)]
haiku/winsys: fix dt prototype args
Add the missing front_private, introduced with earlier commit.
(cherry picked from commit
62e27170a7f7a90091b4121002b7ce209ac7ccb0)
Fixes:
2b676570960 ("gallium/swrast: fix front buffer blitting. (v2)")
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Jerome Duval [Wed, 22 Feb 2017 16:01:24 +0000 (16:01 +0000)]
haiku: build fixes around debug defines
Move the os/os_misc.h include further up, since it's the one that
implicitly provides the PIPE_OS_HAIKU define.
(cherry picked from commit
40b0c8666c337fd0fdff42ce70703cd300abcf0c)
Fixes:
373f118c6c7 ("gallium: do not wrap header inclusion in")
Nominated-by: Emil Velikov <emil.velikov@collabora.com>
[Emil Velikov: add commit message, fixes tag]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Kenneth Graunke [Tue, 11 Apr 2017 15:33:20 +0000 (08:33 -0700)]
i965: Set kernel features before computing max GL version.
We check these bitfields when computing the Haswell max GL version.
We need to set them ahead of time, or they won't exist, and all our
checks will fail. That sets the max core profile GL version to 4.2.
This introduces the bizarre situation where asking for a GL context
with version 4.3+ fails, but asking for a GL core profile context
with version <= 4.2 actually promotes you a 4.5 context.
GLX_MESA_query_renderer also reported the bogus 4.2 value.
Now it shows 4.5.
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Reported-and-tested-by: Rafael Ristovski <rafael.ristovski@gmail.com>
(cherry picked from commit
02ccd8f52cffcc25e5fefdd0f900cf04230395f4)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/intel_screen.c
Kenneth Graunke [Fri, 3 Mar 2017 02:27:32 +0000 (18:27 -0800)]
i965: Skip register write detection when possible.
Detecting register write support by trial and error introduces a
stall at screen creation time, which it would be nice to avoid.
Certain command parser versions guarantee this will work (see the
giant comment in intelInitScreen2 below, or a few commits ago):
- Ivybridge: version >= 1 (kernel v3.16)
- Baytrail: version >= 2 (kernel v3.19)
- Haswell: version >= 7 (kernel v4.8)
For simplicity, we don't bother with version 1 in this patch.
This assumes that the user hasn't disabled aliasing PPGTT via a kernel
command line parameter. Don't do that - you're only breaking things.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit
5e29af5f772c1e1b02a4cc46d2f7d3b5d2151ad8)
Kenneth Graunke [Fri, 3 Mar 2017 02:21:31 +0000 (18:21 -0800)]
i965: Set screen->cmd_parser_version to 0 if we can't write registers.
If we can't write registers, then the effective command parser version
is 0 - it may exist, but it's not usefully enabling anything.
See kernel commit
1ca3712ca3429a617ed6c5f87718e4f6fe4ae0c6 (in v4.8)
where the kernel starts doing this for us. This makes us do more or
less the same thing on older kernels.
This should preserve a bit of sanity by allowing us to perform a
screen->cmd_parser_version > N check to determine that we really can
use the features promised by command parser version N.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit
31693a13f8fbc52d4f19f1e8800a4edabeecbe19)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/intel_screen.c
Kenneth Graunke [Fri, 3 Mar 2017 02:12:28 +0000 (18:12 -0800)]
i965: Document the sad story of the kernel command parser.
This should help us figure out the complexities of which kernel
versions we need to get various features on various platforms.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit
4a2ad6b145b4dd0d19a8e5e0ee6bed09e08ce0eb)
Ilia Mirkin [Sat, 8 Apr 2017 22:31:35 +0000 (18:31 -0400)]
nouveau: when mapping a persistent buffer, synchronize on former xfers
If the buffer is being used, we should wait for those uses to be
complete before returning the map.
Fixes: GL45-CTS.direct_state_access.buffers_functional
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
d9cc58d6ec56e676b1285508a4118a83f5325833)
Ilia Mirkin [Sat, 8 Apr 2017 18:56:16 +0000 (14:56 -0400)]
nvc0: increase texture buffer object alignment to 256 for pre-GM107
We currently don't pass the low byte of the address via the surface
info, so in order to work with images, these have to implicitly be
aligned to 256. The proprietary driver also doesn't go out of its way to
provide lower alignment.
Fixes GL45-CTS.texture_buffer.texture_buffer_texture_buffer_range
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
8036809799c453b02f4c8fedbb5faaeb19af90c2)
Ilia Mirkin [Sat, 8 Apr 2017 03:23:25 +0000 (23:23 -0400)]
nvc0/ir: fix overwriting of offset register with interpolateAtOffset
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
57a744025a2f705d29f60b0eac6e50f8a1ea6203)
Ilia Mirkin [Sat, 8 Apr 2017 00:17:47 +0000 (20:17 -0400)]
nvc0/ir: fix LSB/BFE/BFI implementations
Overwriting the src register is a very bad idea - it logically maps onto
the TGSI registers, and so is effectively overwriting the source values.
Reported-by: Boyan Ding <boyan.j.ding@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
60f5766db48fe81f55f4b7be47c2be27bdbe2c10)
Jason Ekstrand [Wed, 5 Apr 2017 20:41:56 +0000 (13:41 -0700)]
i965/blorp: Bump the batch space estimate
Commit
f938354362655a378d474c5f79c52cea9852ab91 recently increased the
alignment on vertex buffer data from 32 to 64. This caused us to
consume a bit more batch than we were before and we now go over the
estimate by a small amount on certain blits on gen8+. This commit bumps
then gen8 batch estimate by a bit to compensate. Haswell and older
still seems to be well within the limit.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100582
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
c9c39812b91c8104bc0bea16053312547846249c)
Alex Deucher [Wed, 5 Apr 2017 13:40:53 +0000 (09:40 -0400)]
radeonsi: add new polaris10 pci id
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: 13.0 17.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit
d921af62f5761b331039eee1497861b5826ecf82)
Jason Ekstrand [Fri, 31 Mar 2017 22:23:35 +0000 (15:23 -0700)]
i965/blorp: Align vertex buffers to 64B
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
f938354362655a378d474c5f79c52cea9852ab91)
[Emil Velikov: brw_state_batch has different signature]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/genX_blorp_exec.c
Jason Ekstrand [Fri, 31 Mar 2017 22:21:04 +0000 (15:21 -0700)]
anv/blorp: Align vertex buffers to 64B
This fixes issues seen when adding support for full 48-bit addresses.
The 48-bit addresses themselves have nothing to do with it other than
that it caused the kernel to place buffers slightly differently so they
interacted differently with the caches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
5d1ba2cb04f58b0c887304f0b8adda0b5623a710)
Jason Ekstrand [Mon, 3 Apr 2017 19:25:15 +0000 (12:25 -0700)]
anv/pipeline: Properly handle unset gl_Layer and gl_ViewportIndex
When the shader does not set one of these values, they are supposed to
get a default value of 0. We have hardware bits in 3DSTATE_CLIP for
this but haven't been setting them. This fixes the intermittent failure
of dEQP-VK.geometry.layered.3d.render_to_default_layer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
c6f69eea6ac549fc2ffa46944de4dd82c9b53329)
Jason Ekstrand [Wed, 29 Mar 2017 22:16:15 +0000 (15:16 -0700)]
i965/fs: Always provide a default LOD of 0 for TXS and TXL
We already provide a default LOD for textureQueryLevels and texture() on
non-fragment stages. However, there are more cases where one is needed
such as textureSize(gsampler2DMS*) in SPIR-V. Instead of trying to list
out all of the cases one at a time, just provide the default for all TXS
and TXL operations. This fixes a shader validation error in the new
Sascha deferredmultisampling demo which uses textureSize(gsampler2DMS).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100391
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
3503b2714b98684a2ceba5f4fd9a5bfbfbcaad38)
Marek Olšák [Thu, 23 Mar 2017 23:55:55 +0000 (00:55 +0100)]
targets: export radeon winsys_create functions to silence LLVM warning
It silences the following radeonsi LLVM warning due to a previous
commit adding an LLVM workaround:
"mesa: for the -simplifycfg-sink-common option: may only occur zero or one
times!"
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by; Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
18b12bf53351e1a902dc1f2e527a94ec8d8f3eff)
Michal Srb [Tue, 28 Mar 2017 20:39:28 +0000 (23:39 +0300)]
st: Add cubeMapFace parameter to st_finalize_texture.
st_finalize_texture always accesses image at face 0, but it may not be
set if we are working with cubemap that had other face set.
This fixes crash in piglit
same-attachment-glFramebufferTexture2D-GL_DEPTH_STENCIL_ATTACHMENT.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
52f9ccefcb75a9d42307890d7714b1cd92e864cb)
Thomas Hellstrom [Tue, 28 Mar 2017 19:32:22 +0000 (21:32 +0200)]
gbm/dri: Flush after unmap
Drivers may queue dma operations on the context at unmap time so we need
to flush to make sure the data gets to the bo. Ideally the application
would take care of this, but since there appears to be no exported gbm
flush functionality we need to explicitly flush at unmap time.
This fixes a problem where kmscube on vmwgfx in rgba textured mode would
render using an uninitialized texture rather than the intended
rgba pattern.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
ba8df2286a50117011925e915cd832b4a79f126e)
Squashed with commit
gbm/dri: Check dri extension version before flush after unmap
The commit mentioned below required the __DRI2FlushExtension to have
version 4 or above, for GBM functionality. That broke GBM with some
classic dri drivers. Relax that requirement so that we only flush
after unmap if we have version 4 or above. Drivers that require the flush
for correct functionality should implement the desired version.
Fixes:
ba8df228 ("gbm/dri: Flush after unmap")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
18e2aa063ca8e2aeb22a72253891e6f8f5d0d96b)
Craig Stout [Wed, 29 Mar 2017 19:14:30 +0000 (12:14 -0700)]
anv/cmd_buffer: fix host memory leak
push_constants must be free'd.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100452
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
1da7a11de8113932871487efaeb2674a3d1c644a)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/intel/vulkan/anv_cmd_buffer.c
Emil Velikov [Wed, 12 Apr 2017 09:30:37 +0000 (10:30 +0100)]
Revert "cherry-ignore: add the Flush after unmap in gbm/dri fix"
This reverts commit
3a84f6fd4330a00a8d89c24d569dbb450832602d.
The fix in question has been properly addressed and does not cause
regressions.
Andres Gomez [Sat, 1 Apr 2017 15:47:00 +0000 (18:47 +0300)]
docs: add sha256 checksums for 17.0.3
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Sat, 1 Apr 2017 14:29:34 +0000 (17:29 +0300)]
docs: add release notes for 17.0.3
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Sat, 1 Apr 2017 12:12:39 +0000 (15:12 +0300)]
Update version to 17.0.3
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Thu, 30 Mar 2017 20:45:49 +0000 (23:45 +0300)]
cherry-ignore: corrected typo in the Flush after unmap in gbm/dri fix
The regression was for i915, not i965.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Thu, 30 Mar 2017 13:48:24 +0000 (16:48 +0300)]
cherry-ignore: add the Flush after unmap in gbm/dri fix
The commit caused a regression in i965 (and possibly others) since it
didn't implement v4 of DRI2's flush extension.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Andres Gomez [Tue, 28 Mar 2017 22:24:24 +0000 (01:24 +0300)]
cherry-ignore: add the Invalidate L2 for TRANSFER_WRITE barriers fix
Addressed an earlier commit [
0567ab0407e] which did not land in
branch. This will be backported with a stable specific patch.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Jose Fonseca [Tue, 28 Mar 2017 10:25:04 +0000 (11:25 +0100)]
c11/threads: Include thr/xtimec.h for xtime definition when building with MSVC.
MSVC has been including a xtime definition in thr/xtimec.h ever since
MSVC 2013 (which is the minimum we require for building Mesa), and
including it prevents duplicate definitions when it gets included by
LLVM.
In fact, it looks that MSVC has been including a partial C11 threads
implementation too for some time, which we should consider migrating to
once we eliminate the use of _MTX_INITIALIZER_NP in our tree.
Thanks to the anonymous helper from
https://bugs.freedesktop.org/show_bug.cgi?id=100201#c4 for spotting
this.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100201
CC: "17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
ecfafdcbf51d8919e219539b57ffbd9cd3f8557a)
Jason Ekstrand [Wed, 15 Mar 2017 18:58:52 +0000 (11:58 -0700)]
anv: Flush caches prior to PIPELINE_SELECT on all gens
The programming note that says we need to do this still exists in the
SkyLake PRM and, from looking at the bspec, seems like it may apply to
all hardware generations SNB+. Unfortunately, this isn't particularly
clear cut since there is also language in the bspec that says you can
skip the flushing and stall to get better throughput. Experimentation
with the "Car Chase" benchmark in GL seems to indicate that some form of
flushing is still needed. This commit makes us do the full set of
flushes regardless of hardware generation. We can always reduce the
flushing later.
Reported-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
6baae9625d26d282a72481598f9431fcad3211f6)
Jason Ekstrand [Wed, 15 Mar 2017 18:58:51 +0000 (11:58 -0700)]
anv/cmd_buffer: Fix bad indentation
A bunch of code was indented in such a way that it looked like it went
with the if statement above but it definitely didn't.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
0fe3dcce4c3e8b86a60beefe4c5adc760f2d59f8)
Jason Ekstrand [Fri, 24 Mar 2017 23:30:24 +0000 (16:30 -0700)]
anv/cmd_buffer: Apply flush operations prior to executing secondaries
This fixes rendering issues in the Vulkan port of skia on some hardware.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
01a65dc43be3a4bf6b8a901586f7222218f4b6b3)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/intel/vulkan/genX_cmd_buffer.c
Jason Ekstrand [Fri, 24 Mar 2017 23:20:35 +0000 (16:20 -0700)]
anv/blorp: Use anv_get_layerCount everywhere
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
9319ef96fd5c2489754eae1b058e4087d7259341)
Jason Ekstrand [Fri, 24 Mar 2017 23:20:18 +0000 (16:20 -0700)]
anv: Make anv_get_layerCount a macro
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
1b8fa8dd794c22aba43b16470e75ecaebf902b11)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/intel/vulkan/anv_private.h
Timothy Arceri [Wed, 29 Mar 2017 09:30:19 +0000 (20:30 +1100)]
mesa: update lower_jumps tests after bug fix
This change updates the tests to reflect the IR after
the following bug fix.
Fixes:
c1096b7f1d49 ("glsl: fix lower jumps for returns when loop is
inside an if")
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Bugzilla: https://bugs.freedesktop.org/100441
(cherry picked from commit
e44cba540ee7a07bba643bab4b9e519e90244bd1)
Juan A. Suarez Romero [Tue, 28 Mar 2017 16:00:39 +0000 (18:00 +0200)]
tests/cache_test: allow crossing mount points
When using an overlayfs system (like a Docker container), rmrf_local()
fails because part of the files to be removed are in different mount
points (layouts). And thus cache-test fails.
Letting crossing mount points is not a big problem, specially because
this is just for a test, not to be used in real code.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
caa616ccc4384ea1479865e12b56cf816561a827)
Andres Gomez [Wed, 22 Feb 2017 15:03:22 +0000 (17:03 +0200)]
glsl: on UBO/SSBOs link error reset the number of active blocks to 0
While it's legal to have an active blocks count > 0 on link failure.
Unless we actually assign memory for the blocks array we can end up
segfaulting in calls such as glUniformBlockBinding().
To avoid having to NULL check these api calls we simply reset the
block count to 0 if the array was not created.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Cc: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
bf15b2b515d5f37fc67fea77dea9d2fbc1dc8bf1)
Jason Ekstrand [Wed, 15 Mar 2017 00:52:12 +0000 (17:52 -0700)]
anv/query: Fix the location of timestamp availability
Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.0 13.0" <mesa-dev@lists.freedesktop.org>
(cherry picked from commit
4bbb4b95b8ba02693f5e6990b983ebb66dc6241a)
[Andres Gomez: use genX_cmd_buffer.c instead of genX_query.c]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/intel/vulkan/genX_query.c
Bas Nieuwenhuizen [Mon, 27 Mar 2017 23:48:15 +0000 (01:48 +0200)]
radv: flush DB cache before and after HTILE decompress.
It reads @ writes the DB cache, and we haven't flushed dst caches yet,
so DB cache may be stale. Also the user might be shader read (and probably is),
so also flush after.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: <mesa-stable@lists.freedesktop.org>
Fixes:
f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
(cherry picked from commit
a8c51b1cd9168b621e27cf5308d0dd8fc08f8a4a)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/amd/vulkan/radv_cmd_buffer.c
Timothy Arceri [Sun, 26 Mar 2017 12:34:13 +0000 (23:34 +1100)]
glsl: fix lower jumps for returns when loop is inside an if
Previously we would just escape the loop and move everything
following the loop inside the if to the else branch of a new if
with a return flag conditional. However everything outside the
if the loop was nested in would still get executed.
Adding a new return to the then branch of the new if fixes this
and we just let a follow pass clean it up if needed.
Fixes:
tests/spec/glsl-1.10/execution/vs-nested-return-sibling-loop.shader_test
tests/spec/glsl-1.10/execution/vs-nested-return-sibling-loop2.shader_test
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit
c1096b7f1d49f33c85b1042f82ccb063f63e7c20)
Matt Turner [Thu, 23 Mar 2017 19:12:18 +0000 (12:12 -0700)]
i965/fs: Don't emit SEL instructions for type-converting MOVs.
SEL can only convert between a few integer types, which we basically
never do.
Fixes fs/vs-double-uniform-array-direct-indirect-non-uniform-control-flow
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit
7dccd38b400d3a65da20ddefe282a7bb0b7ccb58)
Xu Randy [Mon, 20 Mar 2017 07:31:35 +0000 (15:31 +0800)]
anv/blorp: Fix a crash in CmdClearColorImage
We should use anv_get_layerCount() to access layerCount of VkImageSub-
resourceRange in anv_CmdClearColorImage and anv_CmdClearDepthStencil-
Image, which handles the VK_REMAINING_ARRAY_LAYERS (~0) case.
Test: Sample multithreadcmdbuf from LunarG can run without crash
Signed-off-by: Xu Randy <randy.xu@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
004468de14170dc7a22322301829ad4f59188ee5)
Axel Davy [Wed, 15 Mar 2017 21:53:36 +0000 (22:53 +0100)]
st/nine: Use atomics for available_texture_mem
Resource dtor can be executed in the worker thread.
Use atomic to avoid threading safety issues.
CC: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Tested-by: James Harvey <lothmordor@gmail.com>
(cherry picked from commit
bdf035ea6f784b90a6cbfd4ce16f3188ab15b2d3)
Axel Davy [Wed, 15 Mar 2017 21:45:03 +0000 (22:45 +0100)]
st/nine: Resolve deadlock in surface/volume dtors when using csmt
Surfaces and Volumes can be freed in the worker thread.
Without this patch, pending_uploads_counter could be non-zero
in the Surfaces or Volumes dtor, leading to deadlock.
Instead decrease properly the counter before releasing the
item.
Also avoid another potential deadlock if the item is not
properly unlocked: Do not call UnlockRect which will cause deadlock,
but free directly using the deadlock safe
nine_context_get_pipe_multithread.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99246
CC: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Axel Davy <axel.davy@ens.fr>
Tested-by: James Harvey <lothmordor@gmail.com>
(cherry picked from commit
bd85bb51c717a1858157c73adcb689e3986b2134)
Rob Clark [Fri, 24 Mar 2017 21:03:05 +0000 (17:03 -0400)]
freedreno: fix memory leak
Otherwise blitter would still hold a ref to, for example, sampler-
views.
To reproduce:
glmark2 -b desktop:duration=2 --run-forever
Fixes:
a8e6734 ("freedreno: support for using generic clear path")
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
c03f6f12bbe6fb491c9362b3fd5d39b9f4fd05fd)
Jan Vesely [Thu, 2 Mar 2017 00:45:03 +0000 (19:45 -0500)]
clover: use pipe_resource references
v2: buffers are created with one reference.
v3: add pipe_resource reference to mapping object
v4: rename to pres and drop inline initializers
CC: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit
14b543bdc94df06897f98057c40df84b16f2e944)
Marek Olšák [Thu, 23 Mar 2017 23:17:23 +0000 (00:17 +0100)]
radeonsi: don't hang on shader compile failure
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
(cherry picked from commit
518d8341627ac80f8757fd09cc3cd5c2884f58e0)
Tim Rowley [Tue, 21 Mar 2017 16:42:31 +0000 (11:42 -0500)]
swr: [rasterizer jitter] fix llvm >= 5.0 build break
Function::getArgumentList() doesn't exist anymore, switch to using
arg_begin() (existed back to at least llvm-3.6.0).
Reviewed-by: Vedran Miletić <vedran@miletic.net>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
08f864abd9e241c7db9c99212a66cdad69bdd4d8)
Jason Ekstrand [Wed, 22 Mar 2017 00:16:46 +0000 (17:16 -0700)]
anv/image: Return early when unbinding an image
Found by inspection.
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
c942faf8f37d14e7934a21c15ad2438dde2d501e)
Nicolai Hähnle [Wed, 22 Feb 2017 13:00:29 +0000 (14:00 +0100)]
mesa/main: fix MultiDrawElements[BaseVertex] validation of primcount
primcount must be a GLsizei as in the signature for MultiDrawElements
or bad things can happen.
Furthermore, an error should be flagged when primcount is negative.
Curiously, this code used to work somewhat correctly even when primcount
was negative, because the loop that checks count[i] would iterate out of
bounds and almost certainly hit a negative value at some point.
Found by an ASAN error in
GL45-CTS.gtf32.GL3Tests.draw_elements_base_vertex.draw_elements_base_vertex_primcount
Note that the OpenGL spec seems to have s/primcount/drawcount/ at some
point, and the code still reflects the old language.
v2: provide the correct spec quotes (pointed out by Ian)
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
(cherry picked from commit
c11dcfb5e9b051b9036949b3e40a9dc15138bd97)
Kenneth Graunke [Thu, 2 Mar 2017 19:33:37 +0000 (11:33 -0800)]
i965: Fall back to GL 4.2/4.3 on Haswell if the kernel isn't new enough.
In commit
d2590eb65ff28a9cbd592353d15d7e6cbd2c6fc6 I enabled GL 4.5
on Haswell...but failed to check if we could do indirect compute
shader dispatch...and query buffer objects.
Indirect compute shader dispatch requires command parser version 5
(kernel commit
7b9748cb513a6bef4af87b79f0da3ff7e8b56cd8, which is in
Linux v4.4). On earlier kernels we would have disabled
ARB_compute_shader, which is a mandatory part of OpenGL 4.3+.
Query buffer objects currently require MI_MATH and MI_LOAD_REGISTER_REG,
which mean command parser version 7 (Linux v4.8). On earlier kernels
we would have disabled ARB_query_buffer_object, which is a mandatory
part of OpenGL 4.4+.
The new version support looks like:
- Kernel 4.1 and older => OpenGL 3.3
- Kernel 4.2-4.3 => OpenGL 4.2
- Kernel 4.4-4.7 => OpenGL 4.3
- Kernel 4.8+ => OpenGL 4.5
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
(cherry picked from commit
9b324e4dca4754801e5db59aba0ab559f2cf35ea)
Nanley Chery [Tue, 7 Mar 2017 19:17:05 +0000 (11:17 -0800)]
intel: Correct the BDW surface state size
The PRMs state that this packet is 16 DWORDS long. Ensure that the last
three DWORDS are zeroed as required by the hardware when allocating a
null surface state.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
(cherry picked from commit
7c50f9903f58ef04ff393505a383d06f499f1fdc)
Xu,Randy [Sat, 18 Mar 2017 11:20:17 +0000 (19:20 +0800)]
anv/genX: Solve the vkCreateGraphicsPipelines crash
The crash is due to NULL pColorBlendState, which is legal if the
pipeline has rasterization disabled or if the subpass of the render pass
the pipeline is created against does not use any color attachments.
Test: Sample subpasses from LunarG can run without crash
Signed-off-by: Xu,Randy <randy.xu@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
57595cb0739d50a3fbd0841d7475bd775f3e24f3)
Dave Airlie [Sun, 19 Mar 2017 04:17:14 +0000 (14:17 +1000)]
radv: fix primitive reset index emission
This was meant to be checking the index type to get the correct
index not the last emitted one. This fixes:
dEQP-VK.pipeline.input_assembly.primitive_restart.index_type_uint32.triangle_strip_with_adjacency
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
d06e168b878be45029bf66c2ac627d16144a7823)
Ilia Mirkin [Sat, 4 Mar 2017 18:52:48 +0000 (13:52 -0500)]
st/mesa: set result writemask based on ir type
This prevents textureQueryLevels, which maps as LODQ, from ending up
with a xyzw writemask, which is illegal.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100061
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
dab88e9af7a35ebcdd0fc87df97f4b13e908552a)
Karol Herbst [Sun, 19 Mar 2017 00:08:56 +0000 (01:08 +0100)]
nvc0/ir: treat FMA like MAD for operand propagation
Helps mainly Feral-ported games, due to their use of fma()
shader-db changes:
total instructions in shared programs :
3901147 ->
3842505 (-1.50%)
total gprs used in shared programs : 471258 -> 467359 (-0.83%)
total local used in shared programs : 27405 -> 27361 (-0.16%)
total bytes used in shared programs :
35749888 ->
35214176 (-1.50%)
local gpr inst bytes
helped 17 1829 4091 4091
hurt 4 44 3 3
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
09f16de7e624938d46a63b8285fc5b21050962e9)
Alex Deucher [Fri, 17 Mar 2017 15:13:09 +0000 (11:13 -0400)]
radeonsi: add new polaris12 pci id
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit
c2a97fb7ae991fa52adfd1dabbebbe1803261863)
Jason Ekstrand [Wed, 15 Mar 2017 03:48:47 +0000 (20:48 -0700)]
anv/GetQueryPoolResults: Actually implement the spec
The Vulkan spec is fairly clear about when we should and should not
write query pool results. We're also supposed to return VK_NOT_READY if
VK_QUERY_RESULT_PARTIAL_BIT is not set and we come across any queries
which are not yet finished. This fixes rendering corruptions on The
Talos Principle where geometry flickers in and out due to bogus query
results being returned by the driver. These issues are most noticable
on Sky Lake GT4 2hen running on "ultra" settings.
Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100182
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
08df015b9de8ccb16ce6db93890910f8a02be4c6)
[Andres Gomez: use anv_query.c instead of genX_query.c]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/intel/vulkan/genX_query.c
Jason Ekstrand [Wed, 15 Mar 2017 01:02:41 +0000 (18:02 -0700)]
anv/query: Invalidate the correct range
Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
81840130c0f147ed6ae4c26872c2f04a2167bc54)
[Andres Gomez: use anv_query.c instead of genX_query.c]
Signed-off-by: Andres Gomez <agomez@igalia.com>
Conflicts:
src/intel/vulkan/genX_query.c
Topi Pohjolainen [Wed, 15 Mar 2017 19:31:07 +0000 (21:31 +0200)]
i965/gen8+: Do full stall when switching pipeline
just as earlier gens do.
CC: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96743
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
(cherry picked from commit
bd25d9670b466043cdb5d9668f82accbd587c889)
Emil Velikov [Mon, 20 Mar 2017 14:17:20 +0000 (14:17 +0000)]
docs: add sha256 checksums for 17.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 20 Mar 2017 14:07:38 +0000 (14:07 +0000)]
docs: add release notes for 17.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 20 Mar 2017 14:02:15 +0000 (14:02 +0000)]
Update version to 17.0.2
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Bas Nieuwenhuizen [Wed, 15 Mar 2017 17:49:29 +0000 (18:49 +0100)]
Revert "radv: Emit cache flushes before CP DMA."
This reverts commit
cce43f6d8c40222099badaf52344d6a0eed993f3.
Redundant, as the flush already happens at si_cp_dma_prepare.
Acked-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
ad4dee521d7968a88393dc3685e7c593d27efba5)
Alex Smith [Thu, 16 Mar 2017 16:40:07 +0000 (16:40 +0000)]
radv/ac: Fix shared memory offset calculation
The index passed to get_shared_memory_ptr is an attribute slot index,
i.e. the index of a vec4 within LDS. Therefore this must be scaled by
sizeof(vec4) to give the LDS byte offset.
Fixes:
f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
ce4058dafd2dd283addaa99e8d5b51e53f634f9b)
James Legg [Thu, 16 Mar 2017 17:48:13 +0000 (17:48 +0000)]
radv: Fix using more than 4 bound descriptor sets
Avoid a buffer overflow in ac_nir_to_llvm.c's create_function when
using more than 4 descriptor sets. radv claims support for 8.
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
e88cac1df03d01a9e8a1de1a4a2ee888149e727a)
Samuel Pitoiset [Tue, 14 Mar 2017 23:59:13 +0000 (00:59 +0100)]
radeonsi: disable sinking common instructions down to the end block
Initially this was a workaround for a bug introduced in LLVM 4.0
in the SimplifyCFG pass that caused image instrinsics to disappear
(because they were badly sunk). Finally, this is a win because it
decreases SGPR spilling and increases the number of waves a bit.
Although, shader-db results are good I think we might want to
remove it in the future once the issue is fixed. For now, enable
it for LLVM >= 4.0.
This also fixes a rendering issue with the speedometer in Dirt Rally.
More information can be found here https://reviews.llvm.org/D26348.
Thanks to Dave Airlie for the patch.
v2: - add a FIXME comment
- use if (HAVE_LLVM >= 0x0400) instead
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99484
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97988
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
7751ed39e40e08e5aa0633d018c9f25ad17f9bb0)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
Alex Smith [Tue, 14 Mar 2017 15:26:32 +0000 (15:26 +0000)]
radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBuffer
Need to flush before updating the buffer to ensure that the copy is
ordered after previous accesses (assuming the app has performed the
appropriate barriers).
This fixes potential issues due to draws prior to an update reading
the new buffer content, despite having the necessary barriers between
them.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
e0cc32b85bd8cf5c2202037838a208983e2d793a)
Bas Nieuwenhuizen [Tue, 14 Mar 2017 20:46:54 +0000 (21:46 +0100)]
radv: Emit cache flushes before CP DMA.
The flushes could be due to TRANSFER barriers.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
cce43f6d8c40222099badaf52344d6a0eed993f3)
Jason Ekstrand [Fri, 3 Mar 2017 01:39:11 +0000 (17:39 -0800)]
nir/intrinsics: Make load_barycentric_input take a 2-component coor
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
60d1aac28a1f44ac166e72262e378e063155d6fd)
Jason Ekstrand [Fri, 3 Mar 2017 07:03:03 +0000 (23:03 -0800)]
anv/blorp: Only set a clear color for resolves if fast-cleared
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
678fd00f2f5b213d0317ba51a8163c4c5bd1f3dc)
Jason Ekstrand [Fri, 10 Mar 2017 00:37:23 +0000 (16:37 -0800)]
anv/blorp: Turn off AUX after doing a CCS_D resolve
For render passes with multiple subpasses on gen7, we only fast-clear at
the top but an input attachment use can cause us to do a resolve in the
middle of the render pass. Once we've done so, we are no longer have a
fast-cleared surface so we can just set aux_usage to NONE.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
273b720310863c2084c55f1371b2d27c2d96dbda)
Matt Turner [Thu, 2 Mar 2017 04:43:21 +0000 (04:43 +0000)]
clover: Work around build failure with AltiVec.
Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=587210
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68504
Acked-by: Francisco Jerez <currojerez@riseup.net>
(cherry picked from commit
7d1195c1e4d071fe796bf5f210c468ea1cc86225)
Ilia Mirkin [Wed, 1 Mar 2017 16:09:30 +0000 (11:09 -0500)]
nvc0: increase alignment to 256 for texture buffers on fermi
When binding as textures, the alignment can be 16. However when binding
as an image, the address has to be aligned to 256. (Also when binding as
an RT, but that can't happen with GL or current gallium APIs.)
Reported-by: Roy Spliet <nouveau@spliet.org>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
32dd8d59b6d1b6828e16e854d589d0f04536da14)
Gregory Hainaut [Mon, 6 Mar 2017 04:25:32 +0000 (15:25 +1100)]
glapi: fix typo in count_scale
2*4=8
Signed-off-by: Gregory Hainaut <gregory.hainaut@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit
2ab5eccf5de4a68d0d8d2668f6c5244cc6a41846)
Jacob Lifshay [Wed, 1 Mar 2017 04:30:57 +0000 (20:30 -0800)]
vulkan/wsi: Improve the DRI3 error message
This commit improves the message by telling them that they could probably
enable DRI3. More importantly, it includes a little heuristic to check
to see if we're running on AMD or NVIDIA's proprietary X11 drivers and,
if we are, doesn't emit the warning. This way, users with both a discrete
card and Intel graphics don't get the warning when they're just running
on the discrete card.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99715
Co-authored-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kai Wasserbäch <kai@dev.carbon-project.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Rene Lindsay <rjklindsay@hotmail.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Cc: "17.0" <mesa-dev@lists.freedesktop.org>
(cherry picked from commit
3d8feb38e8fdbc05b591164cb934b48a495adfbc)
Jason Ekstrand [Wed, 1 Mar 2017 16:39:49 +0000 (08:39 -0800)]
anv: Properly handle destroying NULL devices and instances
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: "17.0 13.0" <mesa-dev@lists.freedesktop.org>
(cherry picked from commit
e3d33a23e6cbe2b73b412a56bb4fc4aa6852d081)
Nanley Chery [Wed, 22 Feb 2017 02:17:59 +0000 (18:17 -0800)]
anv/image: Remove extra dependency on HiZ-specific variable
surf_usage is only useful to image views that may use HiZ buffers.
Storage image views don't use HiZ buffers.
v2: Update commit message and add an assertion.
Fixes:
055ff2ec521 ("anv: Replace anv_image_has_hiz() with ISL_AUX_USAGE_HIZ")
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
258af3a856328934d30b7cdf626d5fdba76852f2)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/intel/vulkan/anv_image.c
Dave Airlie [Mon, 13 Mar 2017 20:50:59 +0000 (06:50 +1000)]
radv: setup llvm target data layout
Ported from radeonsi, pointed out by Tom.
"This prevents LLVM from using sext instructions for local memory
offsets and allows the backend to fold immediate offsets into the
instruction. This also prevents some incorrect code generation for
ptrtoint and inttoptr instructions."
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Tom Stellard <tstellar@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
b8ee70384adc3286d18febba7a92047118cc0f0f)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
Marek Olšák [Mon, 6 Mar 2017 00:47:52 +0000 (01:47 +0100)]
radeonsi: mark all bound shader buffer ranges as initialized
This should prevent cases when a buffer was incorrectly mapped without
synchronization just because this wasn't done.
Cc: 13.0 17.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
71a2e4e9452a6890197f8b629b2d8359bdd58913)
Jason Ekstrand [Sat, 11 Mar 2017 07:00:49 +0000 (23:00 -0800)]
anv: Stall before fast-clear operations
During initial CCS bring-up, I discovered that you have to do a full CS
stall prior to doing a CCS resolve as well as afterwards. It appears
that the same is needed for fast-clears as well. This fixes rendering
corruptions on The Talos Principle on Sky Lake GT4. The issue hasn't
been demonstrated on any other hardware however, given that this appears
to be a "too many things in the pipe" problem, having it be easier to
reproduce on a system with more EUs makes sense. The issues with
resolves is demonstrable on a GT3 or GT2 so this is probably also a
problem on all GTs.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
6b644e571e2344691e4d58ff0bba3ddc059c1a5d)
Jason Ekstrand [Sat, 4 Mar 2017 18:52:43 +0000 (10:52 -0800)]
anv: Accurately advertise dynamic descriptor limits
The number of dynamic descriptors is limited by both the number of
descriptors and the total number of dynamic things. Because there isn't
a single "maximum dynamic things" limit, we need to divide by two so
that they can create the maximum of both UBOs and SSBOs.
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Cc: "17.0 13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
5e44ef4a76d9a3681fb6be605319250d4ab800ee)
Emil Velikov [Thu, 9 Mar 2017 00:38:21 +0000 (00:38 +0000)]
i965: move brw_define.h ifndef guard to the top
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
077078ce77e8653725def01ed291eb486989a9ad)
[Emil Velikov: resolve trivial conflicts]
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_defines.h
Dave Airlie [Tue, 7 Mar 2017 05:08:42 +0000 (05:08 +0000)]
radv: disable mip point pre clamping.
No idea what this does, but disabling it fixes a bunch
of failing CTS tests in the lod area, so let's go with that.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
d81bd2f75462646d3803d683a28f6682a2ce3078)
Fredrik Höglund [Tue, 7 Mar 2017 00:53:22 +0000 (01:53 +0100)]
radv/ac: fix multiple descriptor sets with dynamic buffers
The dynamic_offset_offset in the descriptor set binding layout is
relative to the dynamic_offset_start for the set in the pipeline
layout.
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
162beb2abbe6b81d81863b3ac88ec8effcbf7c9d)
Fredrik Höglund [Tue, 7 Mar 2017 00:53:20 +0000 (01:53 +0100)]
radv: fix the dynamic buffer index in vkCmdBindDescriptorSets
This fixes the wrong dynamic buffer descriptors being updated when
firstSet > 0.
Cc: 17.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Fredrik Höglund <fredrik@kde.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
0941d1a574f46c558b0037be81d9a57004f4290b)
Bas Nieuwenhuizen [Mon, 6 Mar 2017 22:23:57 +0000 (23:23 +0100)]
radv: Disable HTILE for textures with multiple layers/levels.
It has issues and the fix I'm working on is too complicated for stable,
so disable for now.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
CC: 13.0 17.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
0ab2dd361fd80c3840b1547cb7e05b4361eaf928)
Alex Smith [Mon, 6 Mar 2017 14:54:28 +0000 (14:54 +0000)]
radv: Emit pending flushes before executing a secondary command buffer
If we have any pending flushes on the primary command buffer, these
must be performed before executing the secondary buffer.
This fixes potential corruption when the contents of a subpass which
clears any of its render targets are given in a secondary buffer: the
flushes after a fast clear would not have been performed until the
vkCmdEndRenderPass call.
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: 13.0 17.0 <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
290d7e892dfa6d04767142f4f6d7ec689933a105)
Dave Airlie [Sun, 5 Mar 2017 23:26:16 +0000 (23:26 +0000)]
radv: drop Z24 support.
This isn't exposed in -pro, the hw docs say it is deprecated,
so let's not bother with it.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
(cherry picked from commit
cc59e24a6bc9bf8b51a22785beb07089770bec8d)
Ilia Mirkin [Fri, 3 Mar 2017 01:18:24 +0000 (20:18 -0500)]
nvc0: take extra pushbuf space into account for pushbuf_space calls
See detailed explanation of why this is needed in commit
eb60a89bc3a.
This spot was missed/overlooked. Basically as a result of the fact
that BEGIN_* ends up calling PUSH_SPACE, which in turn adds an extra 8
to the requested amount, we have to be mindful of that when doing bare
nouveau_pushbuf_space calls.
Reportedly this fixes some crashes when replaying a hitman trace taken
on radeonsi.
Fixes:
eb60a89bc3a ("nouveau: take extra push space into account for pushbuf_space calls")
Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
Reported-by: Karol Herbst <nouveau@karolherbst.de>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
8e6d67685e10b001e07f92a7a6aaff4fe987b6f2)
Nanley Chery [Mon, 27 Feb 2017 18:23:33 +0000 (10:23 -0800)]
anv/pass: Avoid accessing attachment array out of bounds
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
178f9e5f29f3fe83eb5af99a69d7c583c30d21d1)