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Yevhenii Kolesnikov [Thu, 7 Nov 2019 15:22:26 +0000 (17:22 +0200)]
meson: Fix linkage of libgallium_nine with libgalliumvl
Do not link libgallium_nine with libgalliumvl_stub if it's already
linked with libgalliumvl. Linking with stub leads to "duplicate
symbol" errors.
Fixes:
6b4c7047d57178d3362a710ad503057c6a582ca3
("meson: build gallium nine state_tracker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2040
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
(cherry picked from commit
9af22ccddcd1a983df5e0c6732a4e8f5ebf4d9cf)
Bas Nieuwenhuizen [Mon, 25 Nov 2019 22:58:04 +0000 (23:58 +0100)]
radv: Allocate cmdbuffer space for buffer marker write.
Fixes:
946193ae008 "radv: add support for VK_AMD_buffer_marker"
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
25bc9102d89f4390e0edc0a5f09fcde9de80f776)
Gert Wollny [Mon, 18 Nov 2019 10:57:00 +0000 (11:57 +0100)]
r600: Disable eight bit three channel formats
Commit
0899bf55 made some deqp-gles3 tests related to RGB8 PBOs fail
on R600 because it exposed PIPE_FORMAT_R8G8B8_UNORM and R600 doesn't
propely handle this. Disabling this format also for buffers fixes the
issue.
In addition, disabling also the related RGB8 integer formats for buffers
fixes some deqp-gles3 tests:
dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rgb8ui_cube
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8i_2d
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8i_cube
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8ui_2d
dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb8ui_cube
dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8i_2d_array
dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8i_3d
dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8ui_2d_array
dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb8ui_3d
dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8i_2d_array
dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8i_3d
dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8ui_2d_array
dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb8ui_3d
Fixes:
0899bf55
st/mesa: Map MESA_FORMAT_RGB_UNORM8 <-> PIPE_FORMAT_R8G8B8_UNORM
Closes #2118
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
e41958e344cb4b15d01008140a1ee08817104334)
Timothy Arceri [Sun, 24 Nov 2019 23:08:26 +0000 (10:08 +1100)]
radv: create a fresh fork for each pipeline compile
In order to prevent a potential malicious pipeline tainting our
secure compile process and interfering with successive pipelines
we want to create a fresh fork for each pipeline compile.
Benchmarking has shown that simply forking on each pipeline
creation doubles the total time it takes to compile a fossilize db
collection. So instead here we fork the process at device creation
so that we have a slim copy of the device and then fork this
otherwise idle and untainted process each time we compile a
pipeline. Forking this slim copy of the device results in only a
20% increase in compile time vs a 100% increase.
Fixes:
cff53da3 ("radv: enable secure compile support")
(cherry picked from commit
f54c4e85ce089964e4d2ed39157f07226a41d11f)
Timothy Arceri [Wed, 13 Nov 2019 03:51:48 +0000 (14:51 +1100)]
radv: add a secure_compile_open_fifo_fds() helper
This will be used to create a communication pipe between the user
facing device and a freshly forked (per pipeline compile) slim copy
of that device.
We can't use pipe() here because the fork will not be a direct fork
of the user facing process. Instead we use a previously forked
copy of the process that was forked at device creation in order to
reduce the resources required for the fork and avoid performance
issues.
Fixes:
cff53da3748d ("radv: enable secure compile support")
(cherry picked from commit
1663bb1f772dacadaec2d80f8286cfb76c4bb200)
Timothy Arceri [Sun, 24 Nov 2019 23:00:20 +0000 (10:00 +1100)]
radv: add some infrastructure for fresh forks for each secure compile
In the following commits we want to be able to fork an existing lightweight
fork created at device creation time. In order for the user facing process
to communicate with this new fresh fork we create some members here to hold
FIFO file descriptors and a unique id.
Here we also add a new fork enum that we use to tell the lightweight
process to create a fresh fork.
For more information on why we create a fresh fork see the following
commits.
(cherry picked from commit
ef54f15da9ac11fafcbd6c91a7fcdac734436db8)
Zebediah Figura [Tue, 5 Nov 2019 16:21:21 +0000 (10:21 -0600)]
Revert "draw: revert using correct order for prim decomposition."
This reverts commit
f97b731c82afb06cfd6ffebc90a3e098a9a1b308.
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/250
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
(cherry picked from commit
a3c8bc10aa9294bd78c0e2cf5818fb4b8a42cd7a)
Ian Romanick [Mon, 18 Nov 2019 19:52:47 +0000 (11:52 -0800)]
intel/fs: Disable conditional discard optimization on Gen4 and Gen5
The CMP instruction on Gen4 and Gen5 generates one bit (the LSB) of
valid data and 31 bits of junk. Results of comparisons that are used as
Boolean values need to have a fixup applied to generate the proper 0/~0
values.
Calling fs_visitor::nir_emit_alu with need_dest=false prevents the fixup
code from being generated. This results in a sequence like:
cmp.l.f0.0(16) g8<1>F g14<8,8,1>F 0x0F /* 0F */
...
cmp.l.f0.0(16) g4<1>F g6<8,8,1>F 0x0F /* 0F */
(+f0.1) or.z.f0.1(16) null<1>UD g4<8,8,1>UD g8<8,8,1>UD
instead of
cmp.l.f0.0(16) g8<1>F g14<8,8,1>F 0x0F /* 0F */
...
cmp.l.f0.0(16) g4<1>F g6<8,8,1>F 0x0F /* 0F */
or(16) g4<1>UD g4<8,8,1>UD g8<8,8,1>UD
(+f0.1) and.z.f0.1(16) null<1>UD g4<8,8,1>UD 1UD
I examined a couple of the shaders hurt by this change, and ALL of them
would have been affected by this bug. :(
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1836
Fixes:
0ba9497e66a ("intel/fs: Improve discard_if code generation")
Iron Lake
total instructions in shared programs:
8122757 ->
8122957 (<.01%)
instructions in affected programs: 8307 -> 8507 (2.41%)
helped: 0
HURT: 100
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.84% max: 6.67% x̄: 2.81% x̃: 2.76%
95% mean confidence interval for instructions value: 2.00 2.00
95% mean confidence interval for instructions %-change: 2.58% 3.03%
Instructions are HURT.
total cycles in shared programs:
188510100 ->
188510376 (<.01%)
cycles in affected programs: 76018 -> 76294 (0.36%)
helped: 0
HURT: 55
HURT stats (abs) min: 2 max: 12 x̄: 5.02 x̃: 4
HURT stats (rel) min: 0.07% max: 3.75% x̄: 0.86% x̃: 0.56%
95% mean confidence interval for cycles value: 4.33 5.71
95% mean confidence interval for cycles %-change: 0.60% 1.12%
Cycles are HURT.
GM45
total instructions in shared programs:
4994403 ->
4994503 (<.01%)
instructions in affected programs: 4212 -> 4312 (2.37%)
helped: 0
HURT: 50
HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
HURT stats (rel) min: 0.84% max: 6.25% x̄: 2.76% x̃: 2.72%
95% mean confidence interval for instructions value: 2.00 2.00
95% mean confidence interval for instructions %-change: 2.45% 3.07%
Instructions are HURT.
total cycles in shared programs:
128928750 ->
128928982 (<.01%)
cycles in affected programs: 67442 -> 67674 (0.34%)
helped: 0
HURT: 47
HURT stats (abs) min: 2 max: 12 x̄: 4.94 x̃: 4
HURT stats (rel) min: 0.09% max: 3.75% x̄: 0.75% x̃: 0.53%
95% mean confidence interval for cycles value: 4.19 5.68
95% mean confidence interval for cycles %-change: 0.50% 1.00%
Cycles are HURT.
(cherry picked from commit
e51eda99dfd6a66b066e371005e7a54ecc38fc11)
Yevhenii Kolesnikov [Mon, 7 Oct 2019 12:59:52 +0000 (15:59 +0300)]
glsl: Enable textureSize for samplerExternalOES
From OES_EGL_image_external_essl3
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1901
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Dave Airlie [Wed, 20 Nov 2019 19:53:03 +0000 (05:53 +1000)]
llvmpipe/ppc: fix if/ifdef confusion in backport.
Fixes:
32aba91c07f (llvmpipe: use ppc64le/ppc64 Large code model for JIT-compiled shaders)
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Hyunjun Ko [Fri, 21 Jun 2019 03:18:33 +0000 (03:18 +0000)]
freedreno/ir3: fix printing output registers of FS.
Fixes:
cea39af2fbf1 ("freedreno/ir3: Generalize ir3_shader_disasm()")
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
d0f38394b146fa61197c66a0a0f95fa83f58cec8)
Alejandro Piñeiro [Tue, 19 Nov 2019 10:13:15 +0000 (11:13 +0100)]
v3d: adds an extra MOV for any sig.ld*
Specifically when we are in non-uniform control flow, as we would need
to set the condition for the last instruction. If (for example) a
image atomic load stores directly their value on a NIR register,
last_inst would be a nop, and would fail when set the condition.
Fixes piglit test:
spec/glsl-es-3.10/execution/cs-ssbo-atomic-if-else-2.shader_test
Fixes:
6281f26f064ada ("v3d: Add support for shader_image_load_store.")
v2: (Changes suggested by Eric Anholt)
* Cover all sig.ld* signals, not just ldunif and ldtmu, as all of
them have the same restriction.
* Update comment explaining why we add a MOV in that case
* Tweak commit message.
v3:
* Drop extra set of parens (Eric)
* Add missing ld signal to is_ld_signal to fix shader-db regression.
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
b4bc59e37ec0969d70e87d233e4e82431ec2e092)
Jose Maria Casanova Crespo [Fri, 15 Nov 2019 13:46:30 +0000 (14:46 +0100)]
v3d: Fix predication with atomic image operations
Fixes dEQP test:
dEQP-GLES31.functional.synchronization.inter_call.with_memory_barrier.image_atomic_multiple_interleaved_write_read
Fixes piglit test:
spec/glsl-es-3.10/execution/cs-image-atomic-if-else.shader_test
Fixes:
6281f26f064ada ("v3d: Add support for shader_image_load_store.")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
d983055184320a843d0f056b4c0f7af53cff47ab)
Bas Nieuwenhuizen [Thu, 31 Oct 2019 21:53:30 +0000 (22:53 +0100)]
radv: Do not change scratch settings while shaders are active.
When the scratch ringbuffer settings are changed, the shader unit has
to be idle or we will have shaders using old and new settings.
That combination is not supported on the HW (likely the offset is
ringbuffer idx * WAVESIZE * 1024).
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
4eb2a1dc6fc32a047d53620a929eae0bb255f9da)
Eric Engestrom [Sun, 17 Nov 2019 09:51:52 +0000 (09:51 +0000)]
vulkan: delete typo'd header
Two files exist in that directory:
- vulkan_xlib_randr.h
- vulkan_xlib_xrandr.h
Both were imported in
205c271562db8cb2effc ("vulkan: Update the XML and
headers to 1.1.70") with identical contents (ie. the
VK_EXT_acquire_xlib_display extension), but the former was never
included anywhere and can't be found upstream [1], while the latter is
included in vulkan.h and found upstream.
[1] https://github.com/KhronosGroup/Vulkan-Headers/tree/master/include/vulkan
Fixes:
205c271562db8cb2effc ("vulkan: Update the XML and headers to 1.1.70")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
344859c32d00e444e4e820642541628b36c0622e)
Dylan Baker [Wed, 20 Nov 2019 17:25:03 +0000 (09:25 -0800)]
VERSION: bump for 19.3.0-rc4
Jason Ekstrand [Fri, 8 Nov 2019 15:33:07 +0000 (09:33 -0600)]
anv: Stop bounds-checking pushed UBOs
The bounds checking is actually less safe than just pushing the data.
If the bounds checking actually ever kicks in and it's not on the last
UBO push range, then the shrinking will cause all subsequent ranges to
be pushed to the wrong place in the GRF. One of the behaviors we
definitely don't want is for OOB UBO access to result in completely
unrelated UBOs returning garbage values. It's safer to just push the
UBOs as-requested. If we're really concerned about robustness, we can
emit shader code to do bounds checking which should be stupid cheap (a
CMP followed by SEL).
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Brian Paul [Wed, 9 Oct 2019 18:05:16 +0000 (12:05 -0600)]
Call shmget() with permission 0600 instead of 0777
A security advisory (TALOS-2019-0857/CVE-2019-5068) found that
creating shared memory regions with permission mode 0777 could allow
any user to access that memory. Several Mesa drivers use shared-
memory XImages to implement back buffers for improved performance.
This path changes the shmget() calls to use 0600 (user r/w).
Tested with legacy Xlib driver and llvmpipe.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
(cherry picked from commit
02c3dad0f3b4d26e0faa5cc51d06bc50d693dcdc)
Rob Clark [Mon, 18 Nov 2019 17:42:03 +0000 (09:42 -0800)]
Revert "freedreno/ir3: enable pre-fs texture fetch for a6xx"
This reverts commit
f30c256ec05618fb40dccbd94a3434b2f63db478.
See
088a2a4cab031f1505d531698109f330f94f3072
Fixes:
f30c256ec05 ("freedreno/ir3: enable pre-fs texture fetch for a6xx")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Danylo Piliaiev [Thu, 14 Nov 2019 13:36:27 +0000 (15:36 +0200)]
i965: Unify CC_STATE and BLEND_STATE atoms on Haswell as a workaround
Re-emitting 3DSTATE_CC_STATE_POINTERS after emitting
3DSTATE_BLEND_STATE_POINTERS fixes the shadow flickering in
SuperTuxCart and Tropico 6 which was seen only on Haswell.
The reason for this is unknown and fix was found empirically.
The closest mention in PRM is that it should improve performance.
From the HSW PRM, volume 2b, page 823 (3DSTATE_BLEND_STATE_POINTERS):
"When the BLEND_STATE pointer changes but not the CC_STATE pointer,
driver needs to force a CC_STATE pointer change to improve
blend performance in pixel backend."
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1834
Fixes:
eca4a654 ("i965: Disable dual source blending when shader doesn't support it on gen8+")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
6f17fe0606a144f977d8b70a7ee9f8371abc144b)
Jonathan Marek [Fri, 15 Nov 2019 20:34:09 +0000 (15:34 -0500)]
freedreno/registers: fix a6xx_2d_blit_cntl ROTATE
A change from
b7093882 got overwritten by
610c8c93
Fixes:
610c8c93 ("freedreno/registers: Update with GS, HS and DS registers")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
75e58d1fae94f68d75c04770b1cadc6c1b112f6c)
Jonathan Marek [Fri, 15 Nov 2019 17:38:28 +0000 (12:38 -0500)]
freedreno/ir3: disable texture prefetch for 1d array textures
Prefetch only supports the basic 2D texture case, checking is_array is
needed because 1d array textures pass the coord num_components==2 test.
Fixes:
2a0d45ae ("freedreno/ir3: Add a NIR pass to select tex instructions eligible for pre-fetch")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
(cherry picked from commit
0f5743429c76b385db9c513102b2010213ffbb8c)
Ben Crocker [Wed, 13 Nov 2019 20:27:24 +0000 (20:27 +0000)]
llvmpipe: use ppc64le/ppc64 Large code model for JIT-compiled shaders
Large programs, e.g. gnome-shell and firefox, may tax the
addressability of the Medium code model once a (potentially unbounded)
number of dynamically generated JIT-compiled shader programs are
linked in and relocated. Yet the default code model as of LLVM 8 is
Medium or even Small.
The cost of changing from Medium to Large is negligible:
- an additional 8-byte pointer stored immediately before the shader entrypoint;
- change an add-immediate (addis) instruction to a load (ld).
Testing with WebGL Conformance
(https://www.khronos.org/registry/webgl/sdk/tests/webgl-conformance-tests.html)
yields clean runs with this change (and crashes without it).
Testing with glxgears shows no detectable performance difference.
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=
1753327,
1753789,
1543572,
1747110, and
1582226
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/223
Co-authored by: Nemanja Ivanovic <nemanjai@ca.ibm.com>, Tom Stellard <tstellar@redhat.com>
CC: mesa-stable@lists.freedesktop.org
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
(cherry picked from commit
9c3be6d21fa6a45852045d0286b80fb420f82fe3)
Conflicts resolved Dylan (PIPE_ARCH -> UTIL_ARCH rename)
Rhys Perry [Mon, 11 Nov 2019 14:19:51 +0000 (14:19 +0000)]
aco: fix 64-bit fsign with 0
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes:
93c8ebfa ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
(cherry picked from commit
be1d11249bde1e041f6eb9c0acedb041ab450c4b)
Rhys Perry [Mon, 11 Nov 2019 14:15:04 +0000 (14:15 +0000)]
aco: don't combine literals into v_cndmask_b32/v_subb/v_addc
No pipeline-db changes
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes:
93c8ebfa ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
(cherry picked from commit
b062b92ab1a6504772a63a6b44f89b4579aef9a3)
Dylan Baker [Thu, 14 Nov 2019 16:46:22 +0000 (08:46 -0800)]
cherry-ignore: update for 19.3.0-rc4 cycle
Tapani Pälli [Tue, 12 Nov 2019 15:33:08 +0000 (17:33 +0200)]
Revert "dri_interface: add interface for EGL_EXT_image_flush_external"
This reverts commit
7520478461d8ab1cda415ff689d6b9058213ff43.
This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
(cherry picked from commit
1a093a06d6b7f33b4edb621c8d1920ff69dff630)
Tapani Pälli [Tue, 12 Nov 2019 15:32:56 +0000 (17:32 +0200)]
Revert "st/dri: assume external consumers of back buffers can write to the buffers"
This reverts commit
1d1b4578211dcc69cfab8879d0cdafaba1eec948.
This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
(cherry picked from commit
7951eb146c1bb57c6d2231a9675046c535530b6a)
Tapani Pälli [Tue, 12 Nov 2019 15:32:49 +0000 (17:32 +0200)]
Revert "st/dri: add support for EGL_EXT_image_flush_external"
This reverts commit
1d122c104a7a3d9348ab347e1e843b7e2bf3b498.
This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
(cherry picked from commit
25f596e6ba4ef469fbd219aee288dd96624055eb)
Tapani Pälli [Tue, 12 Nov 2019 15:32:41 +0000 (17:32 +0200)]
Revert "egl: handle EGL_IMAGE_EXTERNAL_FLUSH_EXT"
This reverts commit
34b1aa957a3f44ea9587ec43311e8434d3782cc1.
This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
(cherry picked from commit
ff05f16c9988d5794028dba2d437e8796be85fdd)
Tapani Pälli [Tue, 12 Nov 2019 15:32:33 +0000 (17:32 +0200)]
Revert "egl: implement new functions from EGL_EXT_image_flush_external"
This reverts commit
c1c574fdf18f2aeb1c03f9670bf00e1dcd22d99d.
This series caused unexpected flickering artifacts with Iris driver on
Chrome OS and EGL_EXT_image_flush_external spec has not been published
yet.
Acked-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Kristian H. Kristensen <hoegsberg@google.com>
(cherry picked from commit
e64b91e34aa04a137a322ae9444c1c603383c6d4)
Paulo Zanoni [Tue, 12 Nov 2019 00:49:15 +0000 (16:49 -0800)]
intel/compiler: fix nir_op_{i,u}*32 on ICL
On ICL we have the src1 restriction which is applied through
fix_byte_src() and potentially changes the type of the operands from 8
to 32 bits. When this change happens, we fall into the "else if
(bit_size < 32)" case and miscompute src_type because it takes into
consideration bit_size (8) instead of the adjusted size of temp_op
(32). This results in the shader reading unused memory, giving us
mostly failures, but occasional passes due to whatever was already in
the registers we were reading.
This commit fixes a lot of dEQP subgroup i8vec2 tests on ICL, such as:
dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2
This can also be verified by simply changing fix_byte_src() to apply
on all platforms.
Fixes:
5847de6e9afe ("intel/compiler: don't use byte operands for src1 on ICL")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
(cherry picked from commit
eb6352162dde1445f1fe7a408e79f4ecfdf3703c)
Caio Marcelo de Oliveira Filho [Tue, 12 Nov 2019 18:42:09 +0000 (10:42 -0800)]
anv: Initialize depth_bounds_test_enable when not explicitly set
This was causing uninitialized value to end up propagated to the
3DSTATE_DEPTH_BOUNDS packet, leading to asserts on packet
building due to the value being greater than 1.
Fixes:
939ddccb7a5 ("anv: Add support for depth bounds testing.")
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
(cherry picked from commit
0aaf47f7cd50b9c07c1297fe8daff1b2693a6729)
Ian Romanick [Thu, 24 Oct 2019 21:41:20 +0000 (14:41 -0700)]
nir/algebraic: Mark other comparison exact when removing a == a
This prevents some additional optimizations that would change the
original result. This includes things like (b < a && b < c) => b <
min(a, c) and !(a < b) => b >= a. Both of these optimizations were
specifically observed in the piglit tests added in piglit!160.
This was discovered while investigating
https://gitlab.freedesktop.org/mesa/mesa/issues/1958. However, the
problem in that issue was Chrome or Angle is replacing calls to isnan()
with some stuff that we (correctly) optimize to false. If they had left
the calls to isnan() alone, everything would have just worked.
No shader-db changes on any Intel platform.
I also tried marking the comparison generated by the isnan() function
precise. The precise marker "infects" every computation involved in
calculating the parameter to the isnan() function, and this severely
hurt all of the (few) shaders in shader-db that use isnan().
I also considered adding a new ir_unop_isnan opcode that would implement
the functionality. During GLSL IR-to-NIR translation, the resulting
comparison operation would be marked exact (and the samething would need
to happen in SPIR-V translation).
This approach taken by this patch seemed easier, but we may want to do
the ir_unop_isnan thing anyway.
Fixes:
d55835b8bdf ("nir/algebraic: Add optimizations for "a == a && a CMP b"")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
(cherry picked from commit
9be4a422a055d1e829d56c3cc91e1fc2f6e8fb31)
Ian Romanick [Thu, 24 Oct 2019 20:41:59 +0000 (13:41 -0700)]
nir/algebraic: Add the ability to mark a replacement as exact
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
(cherry picked from commit
ea19f2fb68f54171683b6c490b2cd6df96f854c7)
Rob Clark [Fri, 8 Nov 2019 20:55:27 +0000 (12:55 -0800)]
freedreno/ir3: fix gpu hang with pre-fs-tex-fetch
For pre-fs-dispatch texture fetch, we need to assign bary_ij to r0.x,
even if it is not used in the shader (ie. only varying use is for tex
coords). But if, for example, gl_FragCoord is used, it could get
assigned on top of bary_ij, resulting in a GPU hang.
The solution to this is two-fold: (1) the inputs/outputs rework has the
benefit of making RA realize bary_ij is a vec2, even if there are no
split/collect instructions (due to no varying fetches in the shader
itself). And (2) extend the live ranges of meta:input instructions to
the first non-input, to prevent RA from assigning the same register to
multiple inputs.
Backport note: because of (1) above, a better solution for 19.3 would be
to revert
f30c256ec05.
Fixes:
f30c256ec05 ("freedreno/ir3: enable pre-fs texture fetch for a6xx")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit
b22617fb57be54a859a8d62a5e545afcb38266e9)
Rhys Perry [Tue, 12 Nov 2019 15:53:15 +0000 (15:53 +0000)]
aco: don't propagate vgprs into v_readlane/v_writelane
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
93c8ebfa ('aco: Initial commit of independent AMD compiler')
(cherry picked from commit
2c98d79d114d3ed82a9e60519d666f51a1172cd3)
Rhys Perry [Tue, 12 Nov 2019 15:44:17 +0000 (15:44 +0000)]
aco: fix read_invocation with VGPR lane index
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
93c8ebfa ('aco: Initial commit of independent AMD compiler')
(cherry picked from commit
5a1bacb6f916d9a46a3d44830a4eb4bd3dca7d23)
Rhys Perry [Tue, 12 Nov 2019 15:28:52 +0000 (15:28 +0000)]
aco: fix shuffle with uniform operands
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes:
93c8ebfa ('aco: Initial commit of independent AMD compiler')
(cherry picked from commit
f97d9334263a4dd8878c4e259fb5afcdc1334904)
Daniel Schürmann [Thu, 7 Nov 2019 15:22:55 +0000 (16:22 +0100)]
aco: preserve kill flag on moved operands during RA
Fixes:
93c8ebfa780ebd1495095e794731881aef29e7d3 aco: Initial commit of independent AMD compiler
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit
b6f5085dfee81d9c54fcda883d2b06742134084a)
Daniel Schürmann [Fri, 8 Nov 2019 15:36:11 +0000 (16:36 +0100)]
aco: fix invalid access on Pseudo_instructions
Fixes:
93c8ebfa780ebd1495095e794731881aef29e7d3 aco: Initial commit of independent AMD compiler
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit
a2a6880743d7370a6425593f22d9e98317bfc3b2)
Marek Olšák [Mon, 11 Nov 2019 22:04:15 +0000 (17:04 -0500)]
st/mesa: fix Sanctuary and Tropics by disabling ARB_gpu_shader5 for them
They use the "sample" keyword as a variable name.
Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
e00791c5525000652472cdcfe55d59f43ec3d85e)
Lionel Landwerlin [Thu, 11 Jul 2019 12:21:04 +0000 (15:21 +0300)]
anv/wsi: signal the semaphore in the acquireNextImage
We seem to have forgotten about the semaphore in the
acquireNextImageInfo.
v2: Signal semaphore/fence regardless of presentation status (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
edc6606d4e515707b22674a0b3357c02de52378e)
Lionel Landwerlin [Thu, 19 Sep 2019 22:24:53 +0000 (01:24 +0300)]
anv: remove list items on batch fini
This doesn't seem to fix anything because those destroy() calls happen
right before the command buffer object & its list of batch_bo is also
destroyed. Still looks a bit cleaner.
v2: Found a second occurence
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v2)
Fixes:
26ba0ad54d ("vk: Re-name command buffer implementation files")
Cc: <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
935f8f0e56a409b10fac86e18f68be776cdff29f)
Lionel Landwerlin [Thu, 29 Aug 2019 11:54:12 +0000 (14:54 +0300)]
anv: invalidate file descriptor of semaphore sync fd at vkQueueSubmit
We always close the in_fence at the end the anv_cmd_buffer_execbuf()
so when we take it from the semaphore, let's not forget to invalidate
it.
Note that the code leaks the fence_in if we get any error before
reaching the close(). Let's fix that in another patch or better,
rewrite the whole thing!
v2: drop redundant fd = -1 (Jason)
v3: Update commit message (Jason)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
048f0690ee4b39f865d4d6ad82a6c0290dcaaf41)
Lionel Landwerlin [Mon, 11 Nov 2019 10:32:50 +0000 (12:32 +0200)]
mesa: check framebuffer completeness only after state update
The change made in
88d665830f27 ("mesa: check draw buffer completeness
on glClearBufferfi/glClearBufferiv") correctly updated the state prior
to checking the framebuffer completeness on glClearBufferiv but not in
glClearBufferfi.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Fixes:
88d665830f27 ("mesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv")
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/issues/2072
(cherry picked from commit
f93bb903020bac21a36e240b2c19a4733c2405ee)
Laurent Carlier [Wed, 6 Nov 2019 15:04:50 +0000 (16:04 +0100)]
egl: avoid local modifications for eglext.h Khronos standard header file
Move differences in eglextchromium.h header file, then provide the same header than libglvnd-1.2
So program that omit to include eglextchromium.h will fail to build with both mesa and libglvnd headers.
Fixes:
a0a8109f "include: add the definition of EGL_EXT_image_flush_external"
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
57acf921e28eebb76e22f9abb96008885ec44441)
Eric Engestrom [Wed, 6 Nov 2019 19:53:28 +0000 (19:53 +0000)]
egl: move #include of local headers out of Khronos headers
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
eaf43966027cf9654e91ca57aecc8f5a65b58f49)
Dylan Baker [Wed, 13 Nov 2019 19:17:01 +0000 (11:17 -0800)]
Bump version for -rc3
Dylan Baker [Mon, 11 Nov 2019 17:52:12 +0000 (09:52 -0800)]
cherry-ignore: Update for 19.3-rc3 cycle
Eric Engestrom [Tue, 10 Sep 2019 16:06:09 +0000 (17:06 +0100)]
egl: fix _EGL_NATIVE_PLATFORM fallback
When the X11 or Haiku platforms were compiled in, they would bypass the
`_EGL_NATIVE_PLATFORM` fallback by always returning themselves instead.
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
86d3a346f1576acb6c2f8c3be3853a6a3e226b5c)
Erik Faye-Lund [Fri, 8 Nov 2019 11:22:00 +0000 (12:22 +0100)]
zink: correct depth-stencil format
When using packed vulkan-formats on little-endian systems, we need to
swap the components for the gallium formats. And since Zink isn't
big-endian safe yet, little-endian is the only endianess we care about
right now.
This fixes a bunch of piglit tests, amongs others:
- spec@arb_depth_texture@depth-level-clamp
- spec@arb_depth_texture@depthstencil-render-miplevels * d=z24
- spec@arb_depth_texture@fbo-depth-gl_depth_component24-blit
- spec@arb_depth_texture@fbo-depth-gl_depth_component24-copypixels
- spec@arb_depth_texture@fbo-depth-gl_depth_component24-drawpixels
- spec@arb_depth_texture@fbo-depth-gl_depth_component24-readpixels
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes:
8d46e35d16e ("zink: introduce opengl over vulkan")
(cherry picked from commit
b4d47e21d7004412a16c12b762239dbeee665752)
Caio Marcelo de Oliveira Filho [Fri, 8 Nov 2019 23:58:15 +0000 (15:58 -0800)]
spirv: Don't leak GS initialization to other stages
The stage specific fields of shader_info are in an union. We've
likely been lucky that this value was either overwritten or ignored by
other stages. The recent change in shader_info layout in commit
84a1a2578da ("compiler: pack shader_info from 160 bytes to 96 bytes")
made this issue visible.
Fixes:
cf2257069cb ("nir/spirv: Set a default number of invocations for geometry shaders")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
087ecd9ca58a84cf85e66323b44140e7304d5f93)
Timur Kristóf [Wed, 6 Nov 2019 12:29:26 +0000 (13:29 +0100)]
ac: Handle invalid GFX10 format correctly in ac_get_tbuffer_format.
It happens that some games try to access a vertex buffer without
a valid format. This case was incorrectly handled by
ac_get_tbuffer_format which made ACO emit an invalid instruction.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
911a8261419f48dcd756f78832fa5a5f4c5b8d93)
Prodea Alexandru-Liviu [Thu, 7 Nov 2019 22:04:50 +0000 (22:04 +0000)]
Meson: Remove lib prefix from graw and osmesa when building with Mingw.
Also remove version sufix from osmesa swrast on Windows.
v2: Make sure we don't remove lib prefix on *nix platforms.
Signed-off-by: Prodea Alexandru-Liviu <liviuprodea@yahoo.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Cc: "19.3" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
1a05811936dd8d0c3a367c6f00629624ef39d537)
Daniel Schürmann [Wed, 6 Nov 2019 17:25:15 +0000 (18:25 +0100)]
aco: workaround Tonga/Iceland hardware bug
The workaround got accidentally moved to the wrong place
Fixes:
08d510010b7586387e363460b98e6a45bbe97164 aco: increase accuracy of SGPR limits
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
a47e232ccd1df7a3f5dd1f92722772e8b81c90ed)
Lepton Wu [Sat, 2 Nov 2019 06:41:29 +0000 (23:41 -0700)]
gallium: dri2: Use index as plane number.
This fix wrong color when playing video under Android + virgl
configuration.
Fixes:
2decad495f3 ("gallium/dri2: Support images with multiple planes for modifiers")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Lepton Wu <lepton@chromium.org>
(cherry picked from commit
5a40e153fd7df58a6419cf2e6211828d7d31cf4e)
Erik Faye-Lund [Thu, 31 Oct 2019 19:05:58 +0000 (20:05 +0100)]
zink: disable fragment-shader texture-lod
We don't support nir_texop_txd, which is required by this cap. So let's
disable it for now.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes:
8d46e35d16e ("zink: introduce opengl over vulkan")
(cherry picked from commit
b385ad0c75cf7288b278402d23e35267492e8dda)
Duncan Hopkins [Wed, 30 Oct 2019 12:26:23 +0000 (13:26 +0100)]
zink: make sure src image is transfer-src-optimal
Fixes:
d2bb63c8d4c ("zink: Use optimal layout instead of general. Reduces valid layer warnings. Fixes RADV image noise.")
(cherry picked from commit
aa64b6dc7f67852bf2a197c00232a28d812d5563)
Erik Faye-Lund [Wed, 30 Oct 2019 10:18:58 +0000 (11:18 +0100)]
zink: do not advertize coherent mapping
We do not support them yet, so let's not pretend.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes:
8d46e35d16e ("zink: introduce opengl over vulkan")
(cherry picked from commit
a32a92f53a3bbb2f2748c0093c9f380a98a08f06)
Erik Faye-Lund [Tue, 29 Oct 2019 22:19:53 +0000 (23:19 +0100)]
zink: always allow mutating the format
There's no good way to know if a texture-view will be created, so we
just have to accept it for all resources.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes:
8d46e35d16e ("zink: introduce opengl over vulkan")
(cherry picked from commit
ca87a53b4661ae15d0c26d2ef0dbdc5a7009dee6)
Erik Faye-Lund [Tue, 29 Oct 2019 22:16:30 +0000 (23:16 +0100)]
zink: use actual format for render-pass
We should use the format derived from the image-view here, not from the
image itselt. Otherwise, we'll end up with incompatible render-passes.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes:
8d46e35d16e ("zink: introduce opengl over vulkan")
(cherry picked from commit
f3a72fd61c22d43e51d02b919af72aaa0587eb9b)
Kristian H. Kristensen [Tue, 5 Nov 2019 23:42:23 +0000 (15:42 -0800)]
freedreno/a6xx: Disable geometry shaders for release
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Acked-by: Rob Clark <robdclark@gmail.com>
Pierre-Eric Pelloux-Prayer [Mon, 4 Nov 2019 14:04:20 +0000 (15:04 +0100)]
radeonsi: fix shader disk cache key
Use unsigned values otherwise signed extension will produce a 64 bits value where
the 32 left-most bits are 1.
Fixes:
307e5cc8fd7 ("radeonsi: tell the shader disk cache what IR is used")
Dylan Baker [Wed, 6 Nov 2019 17:08:45 +0000 (09:08 -0800)]
Bump VERSION to 19.3.0-rc2
Dylan Baker [Thu, 10 Oct 2019 22:10:56 +0000 (15:10 -0700)]
meson: Add dep_glvnd to egl deps when building with glvnd
Otherwise if glvnd is not installed systemwide, but only in a prefix,
it's headers wont be found. This happens because if it's headers are in
/usr/include/ then another dependence will provide the necessary -I
arguments and compilation will work.
Fixes:
035ec7a2bb2d5e413ac945b8f012185a0e187d5e
("meson: Add support for EGL glvnd")
Acked-by: Eric Engestrom <eric@engestrom.ch>
(cherry picked from commit
5d085ad052aac1f35cef7b60c0e6ecad65a6807b)
Paulo Zanoni [Fri, 1 Nov 2019 21:28:48 +0000 (14:28 -0700)]
intel/compiler: remove the operand restriction for src1 on GLK
Commit
5847de6e9afe implemented a restriction that applies to ICL, but
wrongly marked it as also applying to GLK. Reviewers or MR !1125
pointed this, and the commit history shows removal of GLK to parts of
the patch, but it turns there was still a left-over GLK check in the
code.
This code was breaking some of the i8vec2 tests on GLK, for example:
dEQP-VK.subgroups.arithmetic.compute.subgroupadd_i8vec2
Removing the GLK check solves the issue for GLK. I don't see a reason
on why implementing this restriction would actually break GLK, so
there's still more to investigate here since this bug may be affecting
ICL+, but let's apply the real GLK fix while we analyze and discuss
the other possible issues.
Fixes:
5847de6e9afe ("intel/compiler: don't use byte operands for src1
on ICL")
BSpec: 3017
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
(cherry picked from commit
b57383a9445eae153fbf91fad8592d273b14e546)
Daniel Schürmann [Thu, 31 Oct 2019 16:33:35 +0000 (17:33 +0100)]
aco: fix accidential reordering of instructions when scheduling
Fixes:
86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit
efe737fc4f8f76f7d0b3bd8655eafc3196576a3d)
Daniel Schürmann [Fri, 1 Nov 2019 08:06:26 +0000 (09:06 +0100)]
aco: only use single-dword loads/stores for spilling
Fixes:
86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit
5c7dcb15e0cc98fe9fa5fa25f320f2bdd71187c3)
Daniel Schürmann [Thu, 31 Oct 2019 12:25:44 +0000 (13:25 +0100)]
aco: fix immediate offset for spills if scratch is used
Fixes:
86786999189c43b4a2c8e1c1a18b55cd2f369fff "aco: implement VGPR spilling"
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit
d97c0bdd5558e4e00ede38afac879606aff5f04b)
Lionel Landwerlin [Wed, 30 Oct 2019 11:51:08 +0000 (13:51 +0200)]
anv: Properly handle host query reset of performance queries
The host query reset entry point didn't use the availability offset
for performance queries.
To fix this, reorder the availability of performance queries to match
other queries.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
2b5f30b1d9 ("anv: implement VK_INTEL_performance_query")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
ee6fbb95a74d0dfc00fe77778828c73e6a1447fb)
Kenneth Graunke [Mon, 4 Nov 2019 07:50:38 +0000 (23:50 -0800)]
iris: Fix "Force Zero RTA Index Enable" setting again
In
2ca0d913ea8, we began updating cso_fb->layers to the actual layer
count, rather than 0. This fixed cases where we were setting "Force
Zero RTA Index Enable" even when doing layered rendering. Sadly, it
also broke the check entirely: cso_fb->layers is now 1 for non-layered
cases, but the Force Zero RTA Index check was still comparing for 0.
Fixes:
2ca0d913ea8 ("iris: Fix framebuffer layer count")
(cherry picked from commit
fc7b7480867d6049ca12f87d9b6ab0d9ad55d59f)
Dylan Baker [Fri, 25 Oct 2019 20:48:38 +0000 (13:48 -0700)]
nir: correct use of identity check in python
Python has the identity operator `is`, and the equality operator `==`.
Using `is` with strings sometimes works in CPython due to optimizations
(they have some kind of cache), but it may not always work.
Fixes:
96c4b135e34d0804e41bfbc28fc1b5050c49d71e
("nir/algebraic: Don't put quotes around floating point literals")
Reviewed-by: Matt Turner <mattst88@gmail.com>
(cherry picked from commit
717606f9f32af6540b68336e676fca9dd16f282a)
Samuel Pitoiset [Fri, 1 Nov 2019 08:34:12 +0000 (09:34 +0100)]
radv: fix compute pipeline keys when optimizations are disabled
If an app first creates a compute pipeline with
VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT set, then re-compile it
without that flag, the driver should re-compile the compute shader.
Otherwise, it will return the unoptimized one.
Fixes:
ce188813bfe ("radv: add initial support for VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
(cherry picked from commit
9ab27647ff5379e8095a70c23dd16792f074c8c7)
Lionel Landwerlin [Fri, 1 Nov 2019 17:43:00 +0000 (19:43 +0200)]
mesa: check draw buffer completeness on glClearBufferfi/glClearBufferiv
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit
88d665830f27087cb2188e03b0b734acc144c593)
Bas Nieuwenhuizen [Fri, 1 Nov 2019 00:07:02 +0000 (01:07 +0100)]
radv: Close all unnecessary fds in secure compile.
The seccomp filter allows read/write, let us make sure nobody can
do anything with this.
Fixes:
cff53da3748 "radv: enable secure compile support"
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
8efb8f55a617bebe5f33b9745cc22a2490828db8)
Daniel Schürmann [Thu, 31 Oct 2019 20:39:33 +0000 (21:39 +0100)]
docs/relnotes/new_features.txt: Add note about ACO
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Jan Zielinski [Tue, 29 Oct 2019 18:29:27 +0000 (19:29 +0100)]
gallium/swr: Fix depth values for blit scenario
Erik Faye-Lund [Wed, 30 Oct 2019 12:57:21 +0000 (13:57 +0100)]
zink: emit line-width when using polygon line-mode
When switching this to dynamic state, I forgot that this also needs to
be emitted when we use a polygon-mode set to lines.
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes:
6d30abb4f14 ("zink: use dynamic state for line-width")
(cherry picked from commit
b7674829a102b3e751e8d5fc9b29d9e9079dce4a)
Alyssa Rosenzweig [Sat, 26 Oct 2019 19:10:22 +0000 (15:10 -0400)]
pipe-loader: Build kmsro loader for with all kmsro targets
Build failure reported by i965 CI, triggered by building dynamic
pipeloaders with kmsro drivers (besides 'frost). At this point, there's
no reason to actually do that -- mesa CI didn't mind -- but let's not
break the build.
v2: Simplify script. Add extra dependencies for v3d.
Fixes:
afb0d08cb0f ("pipe-loader: Default to kmsro if probe fails")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Clayton Craft <clayton.a.craft@intel.com>
Tested-by: Clayton Craft <clayton.a.craft@intel.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
(cherry picked from commit
bf15318991e3111fa3d94a9d3d564c7c539b9f23)
Jason Ekstrand [Wed, 30 Oct 2019 19:37:45 +0000 (14:37 -0500)]
anv: Set the batch allocator for compute pipelines
Otherwise relocations just up and crash.
Fixes:
a3153162a9b "anv: Delay allocation of relocation lists"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit
9ef198c59a0cf003b4545e345d34b93d9e4c538b)
Jason Ekstrand [Wed, 30 Oct 2019 16:43:53 +0000 (11:43 -0500)]
anv/tests: Zero-initialize instances
Some of the tests were actually relying on some of those uninitialized
bits to be non-zero. In particular, a couple want use_softpin = true.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit
9076e9f3751341063679eb227116060070549a37)
Jason Ekstrand [Fri, 25 Oct 2019 20:42:22 +0000 (15:42 -0500)]
anv: Fix a potential BO handle leak
Fixes:
731c4adcf9b "anv/allocator: Add support for non-userptr"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
(cherry picked from commit
bb257e1852473e3bc49bb9e0fe014741894f7bd0)
Pierre-Eric Pelloux-Prayer [Tue, 29 Oct 2019 18:45:48 +0000 (19:45 +0100)]
mesa: enable msaa in clear_with_quad if needed
If the DrawBuffer sample count is > 1 and msaa is enabled we must also
enable msaa when clearing it.
Fixes:
ea5b7de138b ("radeonsi: make gl_SampleMaskIn = 0x1 when MSAA is disabled")
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1991
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Witold Baryluk <witold.baryluk@gmail.com>
(cherry picked from commit
8a723282e3f7a312ab0ca3aa9157e5b76ec182af)
Bas Nieuwenhuizen [Wed, 30 Oct 2019 14:00:39 +0000 (15:00 +0100)]
radv: Fix disk_cache_get size argument.
Got some int->pointer warnings and 20 is not a valid pointer ....
Fixes:
2e3a635ee69 "radv: Add an early exit in the secure compile if we already have the cache entries."
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
6ced684e2743dec5b6db397fc45e464abf21b5e3)
Bas Nieuwenhuizen [Thu, 31 Oct 2019 01:36:23 +0000 (02:36 +0100)]
anv: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.
CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
3e86d553a470c484b6a2c60bc7866759ec21fea5)
Bas Nieuwenhuizen [Thu, 31 Oct 2019 01:35:51 +0000 (02:35 +0100)]
turnip: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.
CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
72f858fc07746eb1d7360b47636006202a075e84)
Bas Nieuwenhuizen [Thu, 31 Oct 2019 01:33:46 +0000 (02:33 +0100)]
radv: Remove _mesa_locale_init/fini calls.
The resulting locale is not used for Vulkan, and it is not reference
counted, giving issues when multiple instances are created.
CC: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
344ba56b0f36e77c3d4a935717854f1bf8000a2e)
Pierre-Eric Pelloux-Prayer [Wed, 30 Oct 2019 13:28:01 +0000 (14:28 +0100)]
radeonsi: tell the shader disk cache what IR is used
Until
8bef4df196fbb the IR (TGSI or NIR) was used in disk_cache driver_flags.
This commit restores this features to avoid crashing when switching from
one IR to the other.
As radeonsi's default is TGSI, I used "driver_flags & 0x8000000 = 0" for TGSI
to keep the same driver_flags.
Fixes:
8bef4df196f ("radeonsi: add si_debug_options for convenient adding/removing of options")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
(cherry picked from commit
2afeed301010917c4eae55dcd2544f9d329df934)
Mauro Rossi [Thu, 31 Oct 2019 00:59:07 +0000 (01:59 +0100)]
android: aco: fix Lower to CSSA
Fixes the following building error:
external/mesa/src/amd/compiler/aco_spill.cpp:1768:
error: undefined reference to 'aco::lower_to_cssa(aco::Program*, aco::live&, radv_nir_compiler_options const*)'
Fixes:
0b8216b ("aco: Lower to CSSA")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
(cherry picked from commit
d688e4166ca9c49a980a78ce91846fd7072df8fd)
Jordan Justen [Fri, 15 Feb 2019 19:35:28 +0000 (11:35 -0800)]
iris/gen11+: Move flush for render target change
When starting a BLORP operation, we do the BTI-change flush. However,
when ending it and transitioning back to regular drawing, we change the
render target again - without a set_framebuffer_state() call. We need
to do the BTI flush there too. BLORP flags IRIS_DIRTY_RENDER_BUFFER
now, which will cause the next draw to get the BTI flush again.
(explanation of fix by Ken)
Fixes:
2b956a093a1 ("iris: totally untested icelake support")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
bb0c5c487e63e88acbb792f092dd8f392bad8540)
Jordan Justen [Fri, 15 Feb 2019 19:31:31 +0000 (11:31 -0800)]
iris: Add IRIS_DIRTY_RENDER_BUFFER state flag
Fixes:
2b956a093a1 ("iris: totally untested icelake support")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
a2c3c65a31de90fdb55f76f2894860dfbafe2043)
Ian Romanick [Tue, 29 Oct 2019 19:18:16 +0000 (12:18 -0700)]
intel/compiler: Report the number of non-spill/fill SEND messages on vec4 too
This make shader-db's report.py work on Haswell and earlier platforms.
The problem is that the script would detect the "sends" output for
scalar shaders and expect in in vec4 shaders too. When it didn't find
it, the script would fail with:
Traceback (most recent call last):
File "./report.py", line 351, in <module>
main()
File "./report.py", line 182, in main
before_count = before[p][m]
KeyError: 'sends'
Fixes:
f192741ddd8 ("intel/compiler: Report the number of non-spill/fill SEND messages")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
(cherry picked from commit
7b3f38ef69769f1d2bc022186b404885396b1136)
Bas Nieuwenhuizen [Wed, 30 Oct 2019 20:58:42 +0000 (21:58 +0100)]
radv: Fix timeout handling in syncobj wait.
libdrm returns -errno instead of directly the ioctl ret of -1.
Fixes:
1c3cda7d277 "radv: Add syncobj signal/reset/wait to winsys."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit
ec770085c270cb167c02f299f6985744682933b1)
Ilia Mirkin [Mon, 14 Oct 2019 06:40:11 +0000 (02:40 -0400)]
nv50/ir: mark STORE destination inputs as used
Observed an issue when looking at the code generatedy by the
image-vertex-attrib-input-output piglit test. Even though the test
itself worked fine (due to TIC 0 being used for the image), this needs
to be fixed.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
(cherry picked from commit
1b9d1e13d8e14c348f6d6c8fab5f31e8768a1371)
Lionel Landwerlin [Wed, 30 Oct 2019 22:03:30 +0000 (00:03 +0200)]
intel/dev: set default num_eu_per_subslice on gen12
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
8125d7960b ("intel/dev: Add preliminary device info for Tigerlake")
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
(cherry picked from commit
e02c181bfdc554f298f861bb39d20f0bfd7c2dca)
Ilia Mirkin [Mon, 4 Feb 2019 04:25:07 +0000 (23:25 -0500)]
gm107/ir: fix loading z offset for layered 3d image bindings
Unfortuantely we don't know if a particular load is a real 2d image (as
would be a cube face or 2d array element), or a layer of a 3d image.
Since we pass in the TIC reference, the instruction's type has to match
what's in the TIC (experimentally). In order to properly support
bindless images, this also can't be done by looking at the current
bindings and generating appropriate code.
As a result all plain 2d loads are converted into a pair of 2d/3d loads,
with appropriate predicates to ensure only one of those actually
executes, and the values are all merged in.
This goes somewhat against the current flow, so for GM107 we do the OOB
handling directly in the surface processing logic. Perhaps the other
gens should do something similar, but that is left to another change.
This fixes dEQP tests like image_load_store.3d.*_single_layer and GL-CTS
tests like shader_image_load_store.non-layered_binding without breaking
anything else.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "20.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit
869e32593a9096b845dd6106f8f86e1c41fac968)
Dylan Baker [Wed, 30 Oct 2019 21:58:09 +0000 (14:58 -0700)]
VERSION: bump to rc1
Jordan Justen [Fri, 25 Oct 2019 11:20:37 +0000 (04:20 -0700)]
docs/relnotes/new_features.txt: Add note about gen12 support
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Jordan Justen [Tue, 20 Mar 2018 15:23:35 +0000 (08:23 -0700)]
intel/eu/validate/gen12: Add TGL to eu_validate tests.
These reworks were combined into this patch:
* Matt Turner: i965: Disable NoDDChk/NoDDClr test on Gen12+
* Francisco Jerez: intel/eu/validate/gen12: Disable
qword_low_power_no_depctrl eu_validate test.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>