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Arnd Bergmann [Thu, 25 Sep 2014 15:53:39 +0000 (17:53 +0200)]
Merge tag 'tegra-for-3.18-soc' of git://git./linux/kernel/git/swarren/linux-tegra into next/soc
Pull "ARM: tegra: core SoC code changes for 3.18" from Stephen Warren:
the primary change here gets its address information from DT rather than
iomap.h. This removes one more user of iomap.h, and will help allow the
code to move to a location that can be shared between arch/arm and
arch/arm64.
An unused header file was also removed.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'tegra-for-3.18-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: remove unused tegra_emc.h
ARM: tegra: Initialize flow controller from DT
of: Add NVIDIA Tegra flow controller bindings
Arnd Bergmann [Thu, 25 Sep 2014 15:42:57 +0000 (17:42 +0200)]
Merge tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx into next/soc
Pull "arm: Xilinx Zynq cleanup patches for v3.18" from Michal Simek:
- PM support
- Fix L2 useless setting
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'zynq-cleanup-for-3.18' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: Remove useless L2C AUX setting
ARM: zynq: Rename 'zynq_platform_cpu_die'
ARM: zynq: Remove hotplug.c
ARM: zynq: Synchronise zynq_cpu_die/kill
ARM: zynq: cpuidle: Remove pointless code
ARM: zynq: Remove invalidate cache for cpu die
ARM: zynq: PM: Enable DDR clock stop
ARM: zynq: DT: Add DDRC node
Documentation: devicetree: Add binding for Synopsys DDR controller
ARM: zynq: PM: Enable A9 internal clock gating feature
Carlo Caione [Wed, 10 Sep 2014 20:16:59 +0000 (22:16 +0200)]
ARM: meson: add basic support for MesonX SoCs
This patch adds the basic machine file for the MesonX SoCs. Only Meson6
is populated.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Carlo Caione [Tue, 9 Sep 2014 19:38:00 +0000 (21:38 +0200)]
ARM: meson: debug: add debug UART for earlyprintk support
Add the UART definitions needed to support earlyprintk for MesonX SoCs
on UARTAO.
Signed-off-by: Carlo Caione <carlo@caione.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Vincent Stehlé [Thu, 21 Aug 2014 23:31:20 +0000 (01:31 +0200)]
irq: Export handle_fasteoi_irq
Export handle_fasteoi_irq to be able to use it in e.g. the Zynq gpio driver
since commit
6dd859508336 ("gpio: zynq: Fix IRQ handlers").
This fixes the following link issue:
ERROR: "handle_fasteoi_irq" [drivers/gpio/gpio-zynq.ko] undefined!
Signed-off-by: Vincent Stehlé <vincent.stehle@laposte.net>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Vincent Stehle <vincent.stehle@laposte.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Linus Walleij <linus.walleij@linaro.org>
Link: http://lkml.kernel.org/r/1408663880-29179-1-git-send-email-vincent.stehle@laposte.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Olof Johansson [Wed, 24 Sep 2014 18:27:17 +0000 (11:27 -0700)]
Merge tag 'imx-soc-3.18' of git://git./linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: SoC updates for 3.18" from Shawn Guo:
The i.MX SoC updates for 3.18:
- Add initial devicetree support for i.MX1
- Support GPT per clock source from OSC for i.MX6
- A couple of parent selection corrections for i.MX6SL clock driver
- Support more chip revision for i.MX6
- Convert pr_warning to pr_warn
- Add exclusive gate clock support
- Add BYPASS support for i.MX6 PLL clocks
- Update i.MX6 clock tree for audio use case
- A couple of VF610 clock driver updates
* tag 'imx-soc-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (30 commits)
ARM: imx_v6_v7_defconfig updates
ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIM
arm: mach-imx: Convert pr_warning to pr_warn
ARM: imx: source gpt per clk from OSC for system timer
ARM: imx: add gpt_3m clk for i.mx6qdl
ARM: imx: fix register offset of pll7_usb_host gate clock
ARM: clk-imx6sl: refine clock tree for SSI
ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver
ARM: imx6sx: add BYPASS support for PLL clocks
ARM: imx6sl: add BYPASS support for PLL clocks
ARM: imx6q: add BYPASS support for PLL clocks
ARM: imx: add an exclusive gate clock type
ARM: clk-imx6q: refine clock tree for SSI
ARM: clk-imx6q: refine clock tree for ASRC
ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
ARM: clk-imx6q: refine clock tree for ESAI
ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks
ARM: clk-imx6sl: Remove csi_lcdif_sels[]
ARM: imx: clk-vf610: Add USBPHY clocks
ARM: imx: add cpufreq support for i.mx6sx
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 18:17:26 +0000 (11:17 -0700)]
Merge tag 'renesas-soc4-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Fourth Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
Fourth Round of Renesas ARM Based SoC Soc Updates for v3.18
* r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF
* tag 'renesas-soc4-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF
Signed-off-by: Olof Johansson <olof@lixom.net>
Matthias Brugger [Mon, 18 Aug 2014 14:58:00 +0000 (16:58 +0200)]
ARM: mediatek: Add earlyprintk support for mt6589
Enable low-level debug for Mediatek mt6589 SoC on UART0.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Wei Xu [Wed, 24 Sep 2014 09:07:48 +0000 (17:07 +0800)]
ARM: hisi: Fix platmcpm compilation when ARMv6 is selected
When compiling with "ARCH=arm" and "allmodconfig",
with commit:
9cdc99919a95e8b54c1998b65bb1bfdabd47d27b [2/7] ARM: hisi: enable MCPM implementation
we will get:
/tmp/cc6DjYjT.s: Assembler messages:
/tmp/cc6DjYjT.s:63: Error: selected processor does not support ARM mode `ubfx r1,r0,#8,#8'
/tmp/cc6DjYjT.s:761: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:762: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:769: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:775: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:776: Error: selected processor does not support ARM mode `dsb '
/tmp/cc6DjYjT.s:795: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:801: Error: selected processor does not support ARM mode `isb '
/tmp/cc6DjYjT.s:802: Error: selected processor does not support ARM mode `dsb '
Fix platmcpm compilation when ARMv6 is selected.
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 05:21:54 +0000 (22:21 -0700)]
ARM: debug: fix alphanumerical order on debug uarts
HIP04 was added out of order, but so was the previous HISI debug uart
support as well. Minor reshuffling of order.
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 05:20:10 +0000 (22:20 -0700)]
Merge tag 'D01-for-3.18' of git://github.com/hisilicon/linux-hisi into next/soc
Merge "pull request for hisilicon hip04 soc and D01 board updates" from Wei Xu:
ARM: mach-hisi: Hisilicon hip04 soc and D01 board updates for 3.18
- Add the CONFIG_MCPM_QUAD_CLUSTER configuration to enlarge cluster number from 2 to 4
- Enable MCPM on HiP04 SoC
- Enable 16 cores on HiP04 SoC
- Add platform & Fabric controller devicetree binding document for HiP04 SoC
- Add hip04.dtsi & hip04-d01.dts for hip04 SoC platform and D01 board
- Enable HiP04 SoC in both hi3xxx_defconfig & multi_v7_defconfig
- Add the support of Hisilicon HiP04 debug uart
* tag 'D01-for-3.18' of git://github.com/hisilicon/linux-hisi:
ARM: debug: add HiP04 debug uart
ARM: config: enable hisilicon hip04
ARM: dts: add hip04 dts
document: dt: add the binding on HiP04
ARM: hisi: enable HiP04
ARM: hisi: enable MCPM implementation
ARM: mcpm: support 4 clusters
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 05:15:16 +0000 (22:15 -0700)]
Merge tag 'renesas-clk2-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Second Round of Renesas ARM Based SoC Clk Updates for v3.18" from Simon Horman.
* Add r8a7740, sh73a0 SoCs to MSTP bindings
* tag 'renesas-clk2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
Olof Johansson [Wed, 24 Sep 2014 05:04:19 +0000 (22:04 -0700)]
Merge tag 'soc-for-v3.18' of git://git./linux/kernel/git/tmlind/linux-omap into next/soc
SoC related changes for omaps for v3.18 merge window:
- PM changes to make the code easier to use on newer SoCs
- PM changes for newer SoCs suspend and resume and wake-up events
- Minor clean-up to remove dead Kconfig options
Note that these have a dependency to the fixes-v3.18-not-urgent
tag and is based on a commit in that series.
* tag 'soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (514 commits)
ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7
ARM: dts: OMAP3+: Add PRM interrupt
ARM: omap: Remove stray ARCH_HAS_OPP references
ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
ARM: OMAP5 / DRA7: PM: Update CPU context register offset
ARM: AM437x: use pdata quirks for pinctrl information
ARM: DRA7: use pdata quirks for pinctrl information
ARM: OMAP5: use pdata quirks for pinctrl information
ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug
ARM: OMAP4+: PM: use only valid low power state for suspend
ARM: OMAP4+: PM: Make logic state programmable
ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms
...
Michal Simek [Fri, 29 Aug 2014 14:08:58 +0000 (16:08 +0200)]
ARM: zynq: Remove useless L2C AUX setting
AUX setting has no effect that's why remove it.
Warning log:
L2C: platform provided aux values match the hardware, so
have no effect. Please remove them.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:14 +0000 (14:19 -0700)]
ARM: zynq: Rename 'zynq_platform_cpu_die'
Match the naming pattern of all other SMP ops and rename
zynq_platform_cpu_die --> zynq_cpu_die.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:13 +0000 (14:19 -0700)]
ARM: zynq: Remove hotplug.c
The hotplug code contains only a single function, which is an SMP
function. Move that to platsmp.c where all other SMP runctions reside.
That allows removing hotplug.c and declaring the cpu_die function
static.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:12 +0000 (14:19 -0700)]
ARM: zynq: Synchronise zynq_cpu_die/kill
Avoid races and add synchronisation between the arch specific
kill and die routines.
The same synchronisation issue was fixed on IMX platform
by this commit:
"ARM: imx: fix sync issue between imx_cpu_die and imx_cpu_kill"
(sha1:
2f3edfd7e27ad4206acbc2ae99c9df5f46353024)
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Daniel Lezcano [Tue, 2 Sep 2014 21:19:11 +0000 (14:19 -0700)]
ARM: zynq: cpuidle: Remove pointless code
The core is not powered down, it is pointless to call the cpu_pm notifiers and
switch to the global timer.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Daniel Lezcano [Tue, 2 Sep 2014 21:19:10 +0000 (14:19 -0700)]
ARM: zynq: Remove invalidate cache for cpu die
As there is no Power management unit on this board, it is not possible to power
down a core, just WFI is allowed. There is no point to invalidate the cache and
exit coherency.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-and-tested-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:09 +0000 (14:19 -0700)]
ARM: zynq: PM: Enable DDR clock stop
The DDR controller can detect idle periods and leverage low power
features clock stop. When new requests occur, the DDRC resumes
normal operation.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:08 +0000 (14:19 -0700)]
ARM: zynq: DT: Add DDRC node
Add the DDR controller to the Zynq devicetree.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:07 +0000 (14:19 -0700)]
Documentation: devicetree: Add binding for Synopsys DDR controller
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 2 Sep 2014 21:19:06 +0000 (14:19 -0700)]
ARM: zynq: PM: Enable A9 internal clock gating feature
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fabio Estevam [Wed, 10 Sep 2014 02:40:41 +0000 (23:40 -0300)]
ARM: imx_v6_v7_defconfig updates
The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by
default.
The fsl sai driver is used by the vf610-twr board, so let's enable it by
default.
simple-audio-card driver is used by the vf610-twr board, so let's enable it by
default.
Generated this patch by doing:
- make imx_v6_v7_defconfig
- make menuconfig and manually select options
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fabio Estevam [Fri, 5 Sep 2014 14:34:23 +0000 (11:34 -0300)]
ARM: imx_v4_v5_defconfig: Select CONFIG_IMX_WEIM
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by
default.
Generated this patch by doing:
- make imx_v4_v5_defconfig
- make menuconfig and manually select CONFIG_IMX_WEIM
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v4_v5_defconfig
,which results in some additional cleanups.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Joe Perches [Sat, 13 Sep 2014 18:31:15 +0000 (11:31 -0700)]
arm: mach-imx: Convert pr_warning to pr_warn
Use the more common pr_warn.
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Anson Huang [Thu, 11 Sep 2014 03:29:42 +0000 (11:29 +0800)]
ARM: imx: source gpt per clk from OSC for system timer
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock
can be from OSC instead of ipg_per, as ipg_per's rate
may be scaled when system enter low bus mode, to keep
system timer NOT drift, better to make gpt per clock
at fixed rate, here add support for gpt per clock to
be from OSC which is at fixed rate always.
There are some difference on this implementation of
gpt per clock source, see below for details:
i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock
of OSC / 8 for gpt per clk;
i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC
for gpt per clk, and we must enable GPT_CR_24MEM to
enable OSC clk source for gpt per, GPT_PR_PRESCALER24M
is for pre-scaling of this OSC clk, here set it to 8
to make gpt per clk is 3MHz;
i.MX6SL: ipg_per can be from OSC directly, so no need to
implement this new clk source for gpt per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Anson Huang [Thu, 11 Sep 2014 03:29:40 +0000 (11:29 +0800)]
ARM: imx: add gpt_3m clk for i.mx6qdl
Add gpt_3m clock for i.mx6qdl, as gpt can source clock
from OSC, some i.MX6 series SOCs has fixed divider of
8 for gpt clock, so here add a fix clk of gpt_3m.
i.MX6Q TO1.0 has no gpt_3m option, so force it to be
from ipg_per.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Fri, 12 Sep 2014 02:40:28 +0000 (10:40 +0800)]
ARM: imx: fix register offset of pll7_usb_host gate clock
There is a copy&paste error on register offset of pll7_usb_host gate
clock introduced by i.MX6 PLL bypass support patches. The error breaks
the ENET function, because it overwrites the pll6_enet gate bit.
Correct the offset for all i.MX6 clock drivers.
Thanks to Fugang Duan <B38611@freescale.com> for spotting the error.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shengjiu Wang [Tue, 9 Sep 2014 09:13:25 +0000 (17:13 +0800)]
ARM: clk-imx6sl: refine clock tree for SSI
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Tue, 26 Aug 2014 15:06:33 +0000 (23:06 +0800)]
ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver
Since ENABLE and BYPASS bits of PLLs are now implemented as separate
gate and mux clocks by clock drivers, the code handling these two bits
can be removed from clk-pllv3 driver.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Mon, 1 Sep 2014 07:15:57 +0000 (15:15 +0800)]
ARM: imx6sx: add BYPASS support for PLL clocks
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sx.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Mon, 1 Sep 2014 06:29:53 +0000 (14:29 +0800)]
ARM: imx6sl: add BYPASS support for PLL clocks
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS
support for PLL clocks" for imx6q. The difference is that only anaclk1
is available on imx6sl.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Mon, 1 Sep 2014 06:17:48 +0000 (14:17 +0800)]
ARM: imx6q: add BYPASS support for PLL clocks
The imx6q clock driver currently hard-codes all PLL clocks to source
from OSC24M without BYPASS support. The patch adds the missing lvds_in
clock which is mutually exclusive with lvds_gate, and implements BYPASS
and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary
Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits
are implemented as mux clocks, and ENABLE bit of PLL clocks is
implemented as a gate clock after BYPASS mux.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shawn Guo [Tue, 26 Aug 2014 07:06:33 +0000 (15:06 +0800)]
ARM: imx: add an exclusive gate clock type
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e.
LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously.
This patches adds an exclusive gate clock type specifically for such
case. The clock driver will need to call imx_clk_gate_exclusive() to
register a gate clock with parameter exclusive_mask indicating the mask
of gate bits which are mutually exclusive to this gate clock.
Right now, it only handles the exclusive gate clocks which are defined
in a single hardware register, which is the case we're running into
today. But it can be extended to handle exclusive gate clocks defined
in different registers later if needed.
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shengjiu Wang [Thu, 4 Sep 2014 09:48:59 +0000 (17:48 +0800)]
ARM: clk-imx6q: refine clock tree for SSI
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shengjiu Wang [Thu, 4 Sep 2014 09:48:58 +0000 (17:48 +0800)]
ARM: clk-imx6q: refine clock tree for ASRC
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share
the same gate bits.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fancy Fang [Thu, 4 Sep 2014 08:33:12 +0000 (16:33 +0800)]
ARM: clk-imx6sl: correct the pxp and epdc axi clock selections
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL
clocks are not the same. So split the epdc_pxp_sels into two different
clock selections 'pxp_axi_sels' and 'epdc_axi_sels'.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
Signed-off-by: Robby Cai <R63905@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Shengjiu Wang [Fri, 8 Aug 2014 07:02:47 +0000 (15:02 +0800)]
ARM: clk-imx6q: refine clock tree for ESAI
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename
'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'.
Make the clock for ESAI more clear and align them with imx6sx.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fabio Estevam [Tue, 19 Aug 2014 18:21:12 +0000 (15:21 -0300)]
ARM: clk-imx6sl: Select appropriate parents for LCDIF clocks
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and
PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Fabio Estevam [Tue, 19 Aug 2014 18:21:11 +0000 (15:21 -0300)]
ARM: clk-imx6sl: Remove csi_lcdif_sels[]
Currently csi_lcdif_sels[] is a shared array for the providing the possible
clock parents for csi and lcdif blocks.
This is not correct, as csi and lcdif do not share the same clock parents.
Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in
order to describe the parents correctly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Mon, 18 Aug 2014 20:07:12 +0000 (22:07 +0200)]
ARM: imx: clk-vf610: Add USBPHY clocks
This commit adds PLL7 which is required for USBPHY1. It also adds
the USB PHY and USB Controller clocks and the gates to enable them.
Acked-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Anson Huang [Wed, 25 Jun 2014 09:10:12 +0000 (17:10 +0800)]
ARM: imx: add cpufreq support for i.mx6sx
Add cpufreq support for i.MX6SX, using common
i.MX6Q cpufreq driver.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Stefan Agner [Tue, 29 Jul 2014 14:20:28 +0000 (16:20 +0200)]
ARM: imx: clk-vf610: introduce clks_init_on
At the end of the boot process, the clock framework might disable
required main PLL's. So far, this was no issue since drivers
requested clocks, which are descended of the main PLL's (e.g.
pll1_pfd1, which provides the system clock).
To archive the full 500MHz system clock, DDR clock need to be a
descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The
bootloader sets up the clocks accordingly before making use of
DDR at all. However, in Linux, there is no driver using PLL2,
which lead to PLL2 being disabled by the clock framework.
With this patch, we make sure that the main system clock and the
DDR clock are initially enabled and are kept enabled.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Alexander Shiyan [Sat, 26 Jul 2014 09:45:28 +0000 (13:45 +0400)]
ARM: i.MX1: Add devicetree support
This patch adds basic devicetree support for i.MX1 based SoCs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Jason Liu [Tue, 5 Nov 2013 04:03:18 +0000 (12:03 +0800)]
ARM: i.MX6: add more chip revision support
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This
TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3
and TO1.4 are never revealed.
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Arnd Bergmann [Thu, 11 Sep 2014 07:45:18 +0000 (09:45 +0200)]
Merge tag 'renesas-dt-timers2-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Pull "Second Round of Renesas ARM Based SoC DT Timers Updates for v3.18" from Simon Horman:
* kzm9g-reference: Enable CMT1 in device tree
* Use SoC-specific timer compat strings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-dt-timers2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g-reference: Enable CMT1 in device tree
ARM: shmobile: sh73a0: Add CMT1 device to DT
ARM: shmobile: r8a7740: Use SoC-specific 48-bit CMT compat string
ARM: shmobile: r8a7779: Use SoC-specific TMU compat string
ARM: shmobile: r8a7791: Use SoC-specific 48-bit CMT compat string
ARM: shmobile: r7s72100: Use SoC-specific MTU2 compat string
ARM: shmobile: r8a7790: Use SoC-specific 48-bit CMT compat string
Simon Horman [Wed, 10 Sep 2014 00:43:31 +0000 (09:43 +0900)]
ARM: shmobile: r8a7794: Remove unnecessary #ifdef CONFIG_USE_OF
The r8a7794 support is always compiled using ARCH_MULTIPLATFORM which
selects USE_OF. So #ifdef CONFIG_USE_OF is unnecessary.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fabio Estevam [Tue, 9 Sep 2014 17:43:10 +0000 (14:43 -0300)]
ARM: imx: Remove mach-mxt_td60 board file
All the current support of mach-mxt_td60 board can be converted to devicetree.
Remove the board file.
Cc: Alan Carvalho de Assis <acassis@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Nishanth Menon [Tue, 9 Sep 2014 17:15:33 +0000 (12:15 -0500)]
ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7
OMAP4, OMAP5 and DRA7 share a lot of common logic and data structures.
These have been enabled in the previous patches, however, this also
means that OMAP5 or DRA7 only builds also need to build OMAP4 logic.
Update to reuse OMAP4 logic.
This fixes the 'undefined reference to 'omap4_pm_init_early'' in
OMAP5 or DRA7 only builds.
Fixes:
6af16a1dac5465c ("ARM: DRA7: Add hook in SoC initcalls to enable pm initialization")
Fixes:
628ed4717000789 ("ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization")
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Ulrich Hecht [Tue, 2 Sep 2014 09:13:04 +0000 (11:13 +0200)]
clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindings
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Arnd Bergmann [Tue, 9 Sep 2014 15:09:35 +0000 (17:09 +0200)]
Merge tag 'renesas-soc3-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Pull "Third Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman:
* Initial r8a7794 SoC support
* Support Cortex-A7 in shmobile_init_delay()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Initial r8a7794 SoC support
ARM: shmobile: support Cortex-A7 in shmobile_init_delay()
Arnd Bergmann [Tue, 9 Sep 2014 15:07:30 +0000 (17:07 +0200)]
Merge tag 'renesas-r8a7740-multiplatform-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM Based SoC r8a7740 Multiplatform Updates for v3.18" from Simon Horman:
* Enable multiplatform support for r8a7740 SoC and remove
its DT-reference C board DTS files.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-r8a7740-multiplatform-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: armadillo800eva reference: Remove DTS
ARM: shmobile: armadillo800eva reference: Remove C board code
ARM: shmobile: r8a7740: Add restart callback
ARM: shmobile: armadillo800eva: Build DTS for multiplatform
ARM: shmobile: armadillo800eva: Sync DTS
ARM: shmobile: r8a7740: Multiplatform support
Ulrich Hecht [Mon, 8 Sep 2014 00:57:08 +0000 (09:57 +0900)]
ARM: shmobile: kzm9g-reference: Enable CMT1 in device tree
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Ulrich Hecht [Mon, 8 Sep 2014 00:57:06 +0000 (09:57 +0900)]
ARM: shmobile: sh73a0: Add CMT1 device to DT
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:44 +0000 (09:27 +0900)]
ARM: shmobile: r8a7740: Use SoC-specific 48-bit CMT compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7740 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:48 +0000 (09:27 +0900)]
ARM: shmobile: r8a7779: Use SoC-specific TMU compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7779 TMU
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:46 +0000 (09:27 +0900)]
ARM: shmobile: r8a7791: Use SoC-specific 48-bit CMT compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7791 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:47 +0000 (09:27 +0900)]
ARM: shmobile: r7s72100: Use SoC-specific MTU2 compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r7s72100 MTU2
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Mon, 8 Sep 2014 00:27:45 +0000 (09:27 +0900)]
ARM: shmobile: r8a7790: Use SoC-specific 48-bit CMT compat string
In general Renesas hardware is not documented to the extent
where the relationship between IP blocks on different SoCs can be assumed
although they may appear to operate the same way. Furthermore the
documentation typically does not specify a version for individual
IP blocks. For these reasons a convention of using the SoC name in place
of a version and providing SoC-specific compat strings has been adopted.
Although not universally liked this convention is used in the bindings for
a number of drivers for Renesas hardware. The purpose of this patch is to
make use of the SoC-specific CMT compat string for the r8a7790 48-bit CMT
clock source.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Simon Horman [Tue, 9 Sep 2014 02:50:00 +0000 (11:50 +0900)]
Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' into dt-timers-for-v3.18
Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
Nishanth Menon [Fri, 22 Aug 2014 14:03:50 +0000 (09:03 -0500)]
ARM: dts: OMAP3+: Add PRM interrupt
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM
And for DRA7, provide crossbar number for prm interrupt.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Mark Brown [Sat, 6 Sep 2014 10:14:16 +0000 (11:14 +0100)]
ARM: omap: Remove stray ARCH_HAS_OPP references
OPP is now a normal kernel library selected by its users rather than a
feature that architectures need to enable so ARCH_HAS_OPP serves no
function any more - remove the selects.
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Rajendra Nayak [Fri, 22 Aug 2014 14:02:34 +0000 (09:02 -0500)]
ARM: DRA7: Add hook in SoC initcalls to enable pm initialization
With consolidated code, now we can add the required hooks for
DRA7 to enable power management.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: minor modifications]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Tony Lindgren [Mon, 8 Sep 2014 22:20:15 +0000 (15:20 -0700)]
Merge branch 'pull/v3.18/for-omap-soc' of https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/soc
Tony Lindgren [Mon, 8 Sep 2014 22:04:24 +0000 (15:04 -0700)]
Merge branch 'pull/v3.18/powerdomain-fixes' of https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/fixes-not-urgent
Santosh Shilimkar [Tue, 20 May 2014 21:19:23 +0000 (16:19 -0500)]
ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization
With consolidated code, now we can add the required hooks for
OMAP5 to enable power management.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor rebase updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Rajendra Nayak [Mon, 27 May 2013 10:16:44 +0000 (15:46 +0530)]
ARM: OMAP5 / DRA7: Enable CPU RET on suspend
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR
and instead attempt a CPU RET and side effect, MPU RET in suspend.
NOTE: the hardware was originally designed to be capable of achieving
deep power states such as OFF and OSWR, however due to various issues
and risks, deepest valid state was determined to be CSWR - hence we use
the errata framework to handle this case.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: updates]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Fri, 6 Jun 2014 22:30:43 +0000 (17:30 -0500)]
ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplug
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug
logic. On OMAP5, DRA7, we do not need this in place yet, also,
currently the CPU startup pointer is located in omap4_cpu_pm_info
instead of cpu_pm_ops.
So, isolate the function to hotplug_restart pointer in cpu_pm_ops
where it should have belonged, initalize them as per valid startup
pointers for OMAP4430/60 as in current logic, however provide
dummy_cpu_resume to be the startup location as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: split this out of original code and isolate it]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Rajendra Nayak [Fri, 3 May 2013 10:04:40 +0000 (15:34 +0530)]
ARM: OMAP5 / DRA7: PM: Avoid all SAR saves
Get rid of all assumptions about always having a sar base on *all*
OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at
this point for OMAP5 either.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: Split and optimize]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Thu, 12 Apr 2012 11:31:52 +0000 (17:01 +0530)]
ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomains
In addition to the standard power-management technique, the OMAP5 / DRA7
MPU subsystem also employs an SR3-APG (mercury) power management
technology to reduce leakage.
It allows for full logic and memories retention on MPU_C0 and MPU_C1 and
is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the
OMAP5 and DRA7 family of processors.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor consolidation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Fri, 8 Feb 2013 11:37:31 +0000 (17:07 +0530)]
ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by default
Enables MPUSS ES2 power management mode using ES2_PM_MODE in
AMBA_IF_MODE register.
0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together.
Broken! Fortunately, we do not support this anymore.
0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode
independently.
This is one time settings thanks to always ON domain.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[nm@ti.com: minor conflict resolutions, consolidation for DRA7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Wed, 6 Feb 2013 10:21:45 +0000 (15:51 +0530)]
ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependency
With EMIF clock-domain put under hardware supervised control, memory
corruption and untraceable crashes are observed on OMAP5. Further
investigation revealed that there is a weakness in the PRCM on this
specific dynamic depedency.
The recommendation is to set MPUSS static dependency towards EMIF
clock-domain to avoid issues. This recommendation holds good for DRA7
family of devices as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: conflict resolution, dra7]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Santosh Shilimkar [Wed, 6 Feb 2013 14:09:07 +0000 (19:39 +0530)]
ARM: OMAP5 / DRA7: PM: Update CPU context register offset
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code
so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same
context offset as well.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[rnayak@ti.com: for DRA7]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: rebase, split/merge etc..]
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Keerthy [Mon, 7 Apr 2014 06:24:49 +0000 (11:54 +0530)]
ARM: AM437x: use pdata quirks for pinctrl information
Provide pdata-quirks for Am437x processor family.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Nishanth Menon [Fri, 23 May 2014 04:39:54 +0000 (23:39 -0500)]
ARM: DRA7: use pdata quirks for pinctrl information
Provide pdata-quirks for DRA7 processor family.
Signed-off-by: Nishanth Menon <nm@ti.com>
Nishanth Menon [Thu, 22 May 2014 20:19:29 +0000 (15:19 -0500)]
ARM: OMAP5: use pdata quirks for pinctrl information
Provide pdata-quirks for OMAP5 processor family.
Signed-off-by: Nishanth Menon <nm@ti.com>
Nishanth Menon [Thu, 24 Jul 2014 15:24:19 +0000 (10:24 -0500)]
ARM: OMAP4+: PM: Use only valid low power state for CPU hotplug
Not all SoCs support OFF mode - for example DRA74/72. So, use valid
power state during CPU hotplug.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Fri, 6 Jun 2014 06:17:37 +0000 (01:17 -0500)]
ARM: OMAP4+: PM: use only valid low power state for suspend
We are using power domain state as RET and logic state as OFF. This
state is OSWR. This may not always be supported on ALL power domains. In
fact, on certain power domains, this might result in a hang on certain
platforms. Instead, depend on powerdomain data to provide accurate
information about the supported powerdomain states and use the
appropriate function to query and use it as part of suspend path.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Fri, 6 Jun 2014 02:40:39 +0000 (21:40 -0500)]
ARM: OMAP4+: PM: Make logic state programmable
Move the logic state as different for each power domain. This allows us
to customize the deepest power state we should target over all for each
powerdomain in the follow on patches.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Fri, 6 Jun 2014 06:04:20 +0000 (01:04 -0500)]
ARM: OMAP2+: powerdomain: introduce logic for finding valid power domain
powerdomain configuration in OMAP is done using PWRSTCTRL register for
each power domain. However, PRCM lets us write any value we'd like to
the logic and power domain target states, however the SoC integration
tends to actually function only at a few discrete states. These valid
states are already in our powerdomains_xxx_data.c file.
So, provide a function to easily query valid low power state that the
power domain is allowed to go to.
Based on work originally done by Jean Pihet <j-pihet@ti.com>
https://patchwork.kernel.org/patch/
1325091/ . There is no attempt to
create a new powerdomain solution here, except fixing issues seen
attempting invalid programming attempts. Future consolidation to the
generic powerdomain framework should consider this requirement as
well.
Similar solutions have been done in product kernels in the past such
as:
https://android.googlesource.com/kernel/omap.git/+blame/android-omap-panda-3.0/arch/arm/mach-omap2/pm44xx.c
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Sat, 7 Jun 2014 00:36:41 +0000 (19:36 -0500)]
ARM: OMAP2+: powerdomain: pwrdm_for_each_clkdm iterate only valid clkdms
No need to invoke callback when the clkdm pointer is NULL.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Wed, 20 Aug 2014 13:13:16 +0000 (08:13 -0500)]
ARM: OMAP5: powerdomain data: fix powerdomain powerstate
Update the power domain power states for final production chip
capability. OFF mode, OSWR etc have been descoped for various domains.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Fri, 6 Jun 2014 06:21:51 +0000 (01:21 -0500)]
ARM: OMAP: DRA7: powerdomain data: fix powerdomain powerstate
DRA7 supports only CSWR for CPU, MPU power domains. Core power domain
supports upto INA.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Kevin Hilman <khilman@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Tue, 12 Aug 2014 12:05:19 +0000 (07:05 -0500)]
ARM: OMAP3+: PRM: register interrupt information from DT
Allow the PRM interrupt information to be picked up from device tree.
OMAP3 may use legacy boot and needs to be compatible with old dtbs
(without interrupt populated), for these, we use the value which is
pre-populated.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Mon, 11 Aug 2014 19:58:23 +0000 (14:58 -0500)]
ARM: OMAP4+: PRM: Enable wakeup capability for OMAP5, DRA7
OMAP5 and DRA7 can now use pinctrl based I/O daisychain wakeup
capability. So, enable the support.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Fri, 23 May 2014 05:20:37 +0000 (00:20 -0500)]
ARM: OMAP4+: PRM: remove "wkup" event
"wkup" event at bit offset 0 exists only on OMAP3.
OMAP4430/60 PRM_IRQSTATUS_A9, OMAP5/DRA7 PRM_IRQSTATUS_MPU
register bit 0 is DPLL_CORE_RECAL_ST not wakeup event like OMAP3.
The same applies to AM437x as well.
Remove the wrong definition.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Thu, 22 May 2014 20:19:29 +0000 (15:19 -0500)]
ARM: OMAP4+: PRM: register interrupt information from DT
Allow the PRM interrupt information to be picked up from device tree.
the only exception is for OMAP4 which uses values pre-populated and allows
compatibility with older dtb.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Thu, 22 May 2014 20:00:55 +0000 (15:00 -0500)]
ARM: OMAP4: PRM: use the generic prm_inst to allow logic to be abstracted
use the generic function to pick up the prm_instance for a generic logic
which can be reused from OMAP4+
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Nishanth Menon [Thu, 22 May 2014 19:53:54 +0000 (14:53 -0500)]
ARM: OMAP4+: prminst: provide function to find prm_dev instance offset
PRM device instance can vary depending on SoC. We already handle the
same during reset of the device, However, this is also needed
for other logic instances. So, first abstract this out to a generic
function.
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Arnd Bergmann [Fri, 5 Sep 2014 20:46:24 +0000 (22:46 +0200)]
Merge tag 'integrator-for-v3.18-1' of git://git./linux/kernel/git/linusw/linux-integrator into next/soc
Merge "single Integrator patch" from Linus Walleij:
This sets up the dynamically detected IM-PD1 GPIO lines
by way of GPIO descriptors, avoiding any use of the GPIO
global numberspace.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'integrator-for-v3.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: integrator: add MMCI device to IM-PD1
Arnd Bergmann [Fri, 5 Sep 2014 20:45:57 +0000 (22:45 +0200)]
Merge tag 'renesas-clk-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Clk Updates for v3.18" from Simon Horman:
* Add r8a7794 support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-clk-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
clk: shmobile: Add r8a7794 support
Arnd Bergmann [Fri, 5 Sep 2014 15:42:18 +0000 (17:42 +0200)]
Merge tag 'renesas-cleanup-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Cleanup Updates for v3.18" from Simon Horman:
* Remove Genmai board code
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-cleanup-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r7s72100: Remove legacy board support
ARM: shmobile: r7s72100: genmai: Remove legacy board file
ARM: shmobile: r7s72100: genmai: Remove reference board file
Arnd Bergmann [Fri, 5 Sep 2014 15:40:32 +0000 (17:40 +0200)]
Merge tag 'renesas-dt-timers-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC DT Timers Updates for v3.18" from Simon Horman:
* Enable timers using DT when booting boards without Legacy-C code
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-dt-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: genmai-reference: Enable MTU2 in device tree
ARM: shmobile: r7s72100: Add MTU2 device to DT
ARM: shmobile: marzen-reference: Enable TMU0 in device tree
ARM: shmobile: koelsch-reference: Enable CMT0 in device tree
ARM: shmobile: lager-reference: Enable CMT0 in device tree
ARM: shmobile: r8a7779: Add TMU devices to DT
ARM: shmobile: r8a7791: Add CMT devices to DT
ARM: shmobile: r8a7790: Add CMT devices to DT
Conflicts:
arch/arm/mach-shmobile/setup-r8a7779.c
Arnd Bergmann [Fri, 5 Sep 2014 15:36:52 +0000 (17:36 +0200)]
Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18" from Simon Horman:
When booting using the r8a7740/armadillo800eva using dt-reference:
* Use CCF to initialise clocks via DT
* Initialise timers via DT
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7740: Remove r8a7740_add_standard_devices_dt
ARM: shmobile: armadillo800eva-reference: Do not use r8a7740_add_standard_devices_dt()
ARM: shmobile: armadillo800eva-reference: Enable CMT1 in device tree
ARM: shmobile: r8a7740: Add CMT1 device to DT
ARM: shmobile: armadillo800eva-reference: add clock overrides to DTS
ARM: shmobile: r8a7740: add MSTP clock assignments to DT
ARM: shmobile: r8a7740: add SoC clocks to DTS
ARM: shmobile: r8a7740: clock register bits
Arnd Bergmann [Fri, 5 Sep 2014 15:29:29 +0000 (17:29 +0200)]
Merge tag 'renesas-soc2-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Second Round Of Renesas ARM Based SoC Updates For v3.18" from Simon Horman:
* Move legacy INTC definitions from irqs.h to intc.h
* Remove duplicate CPUFreq bits on r8a73a0/ape6evm
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Move legacy INTC definitions from irqs.h to intc.h
ARM: shmobile: ape6evm: Remove duplicate CPUFreq bits
ARM: shmobile: sh73a0: Remove duplicate CPUFreq bits
Arnd Bergmann [Fri, 5 Sep 2014 15:11:36 +0000 (17:11 +0200)]
Merge tag 'renesas-init-delay-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Init Delay Updates For v3.18" from Simon Horman:
* Use shmobile_init_delay across a wider range of SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-init-delay-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: kzm9g: Use shmobile_init_delay()
ARM: shmobile: bockw: Use shmobile_init_delay()
ARM: shmobile: r8a7778: Use shmobile_init_delay()
ARM: shmobile: sh73a0: Use shmobile_init_delay()
ARM: shmobile: Remove shmobile_setup_delay()
ARM: shmobile: r8a73a4: Use shmobile_init_delay()
ARM: shmobile: sh7372: Use shmobile_init_delay()
ARM: shmobile: r8a7778: Update DTS to include CPU frequency
ARM: shmobile: sh73a0: Update DTS to include CPU frequency
ARM: shmobile: sh7372: Update DTS to include CPU frequency
ARM: shmobile: kzm9g-reference: Remove unneeded nr_irqs initialization
ARM: shmobile: kzm9g: Remove unneeded nr_irqs initialization
ARM: shmobile: marzen: Remove NR_IRQS_LEGACY
ARM: shmobile: ape6evm: Use shmobile_init_delay()
ARM: shmobile: ape6evm: Add shmobile_init_late()
ARM: shmobile: bockw: Add shmobile_init_late()
ARM: shmobile: marzen: Add shmobile_init_late()
ARM: shmobile: kzm9g: Add shmobile_init_late()
Arnd Bergmann [Fri, 5 Sep 2014 15:08:14 +0000 (17:08 +0200)]
Merge tag 'renesas-soc-for-v3.18' of git://git./linux/kernel/git/horms/renesas into next/soc
Merge "Renesas ARM Based SoC Updates for v3.18" from Simon Horman:
* Remove unnecessary nr_irqs initialisation on sh73a0, sh7372,
and r8a7779 SoCs
* Use defines hardcoded numbers for DMA
* Rework multiplatform include workaround
* Correctly use shmobile_init_late on a wider range of SoCs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* tag 'renesas-soc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: sh73a0: Remove unneeded nr_irqs initialization
ARM: shmobile: sh7372: Remove unneeded nr_irqs initialization
ARM: shmobile: r8a7779: Remove NR_IRQS_LEGACY
ARM: shmobile: dma: Use defines instead of hardcoded numbers
ARM: shmobile: Rework multiplatform include workaround
ARM: shmobile: r7s72100: Add shmobile_init_late()
ARM: shmobile: r8a73a4: Add shmobile_init_late()
ARM: shmobile: r8a7778: Fix shmobile_init_late()
ARM: shmobile: r8a7779: Fix shmobile_init_late()
ARM: shmobile: sh73a0: Add shmobile_init_late()
ARM: shmobile: r8a7778: Add missing call to shmobile_init_late()
Ulrich Hecht [Thu, 4 Sep 2014 14:02:28 +0000 (16:02 +0200)]
ARM: shmobile: Initial r8a7794 SoC support
Initial support for the r8a7794 SoC, based on work by Hisashi Nakamura.
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Ulrich Hecht [Thu, 4 Sep 2014 14:02:27 +0000 (16:02 +0200)]
ARM: shmobile: support Cortex-A7 in shmobile_init_delay()
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>