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Andrea Di Biagio [Thu, 5 Apr 2018 16:42:32 +0000 (16:42 +0000)]
[documentation][llvm-mca] Update the documentation.
Scheduling models can now describe processor register files and retire control
units. This updates the existing documentation and the README file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329311
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Craig Topper [Thu, 5 Apr 2018 16:32:48 +0000 (16:32 +0000)]
[X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128 which uses WriteShuffle256.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329310
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Philip Pfaffe [Thu, 5 Apr 2018 15:58:27 +0000 (15:58 +0000)]
Fix r329293: Add a missing CMake dependency
The unittest plugin indirectly includes Attributes.gen, so make sure its
target depends on the appropriate tablegen target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329308
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Andrea Di Biagio [Thu, 5 Apr 2018 15:53:31 +0000 (15:53 +0000)]
Fix the buildbots after r329304.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329306
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Andrea Di Biagio [Thu, 5 Apr 2018 15:41:41 +0000 (15:41 +0000)]
[MC][Tablegen] Allow models to describe the retire control unit for llvm-mca.
This patch adds the ability to describe properties of the hardware retire
control unit.
Tablegen class RetireControlUnit has been added for this purpose (see
TargetSchedule.td).
A RetireControlUnit specifies the size of the reorder buffer, as well as the
maximum number of opcodes that can be retired every cycle.
A zero (or negative) value for the reorder buffer size means: "the size is
unknown". If the size is unknown, then llvm-mca defaults it to the value of
field SchedMachineModel::MicroOpBufferSize. A zero or negative number of
opcodes retired per cycle means: "there is no restriction on the number of
instructions that can be retired every cycle".
Models can optionally specify an instance of RetireControlUnit. There can only
be up-to one RetireControlUnit definition per scheduling model.
Information related to the RCU (RetireControlUnit) is stored in (two new fields
of) MCExtraProcessorInfo. llvm-mca loads that information when it initializes
the DispatchUnit / RetireControlUnit (see Dispatch.h/Dispatch.cpp).
This patch fixes PR36661.
Differential Revision: https://reviews.llvm.org/D45259
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329304
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Sanjay Patel [Thu, 5 Apr 2018 15:36:55 +0000 (15:36 +0000)]
[PatternMatch] define m_FNeg using m_FSub
Using cstfp_pred_ty in the definition allows us to match vectors with undef elements.
This replicates the change for m_Not from D44076 / rL326823 and continues
towards making all pattern matchers allow undef elements in vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329303
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Hiroshi Inoue [Thu, 5 Apr 2018 15:27:06 +0000 (15:27 +0000)]
[PowerPC] fix assertion failure due to missing instruction in P9InstrResources.td
This patch adds L(W|H|B)ZXTLS_32 instructions introduced by https://reviews.llvm.org/rL327635 in P9InstrResources.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329299
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Sanjay Patel [Thu, 5 Apr 2018 15:07:35 +0000 (15:07 +0000)]
[InstCombine] add vector and vector undef tests for FP folds; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329294
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Philip Pfaffe [Thu, 5 Apr 2018 15:04:13 +0000 (15:04 +0000)]
Re-land r329273: [Plugins] Add a slim plugin API to work together with the new PM
Fix unittest: Do not link LLVM into the test plugin.
Additionally, remove an unrelated change that slipped in in r329273.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329293
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Pavel Labath [Thu, 5 Apr 2018 14:32:10 +0000 (14:32 +0000)]
[Testing/Support]: Better matching of Error failure states
Summary:
The existing Failed() matcher only allowed asserting that the operation
failed, but it was not possible to verify any details of the returned
error.
This patch adds two new matchers, which make this possible:
- Failed<InfoT>() verifies that the operation failed with a single error
of a given type.
- Failed<InfoT>(M) additionally check that the contained error info
object is matched by the nested matcher M.
To make these work, I've changed the implementation of the ErrorHolder
class. Now, instead of just storing the string representation of the
Error, it fetches the ErrorInfo objects and stores then as a list of
shared pointers. This way, ErrorHolder remains copyable, while still
retaining the full information contained in the Error object.
In case the Error object contains two or more errors, the new matchers
will fail to match, instead of trying to match all (or any) of the
individual ErrorInfo objects. This seemed to be the most sensible
behavior for when one wants to match exact error details, but I could be
convinced otherwise...
Reviewers: zturner, lhames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D44925
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329288
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Tim Northover [Thu, 5 Apr 2018 14:26:06 +0000 (14:26 +0000)]
ARM: Do not spill CSR to stack on entry to noreturn functions
A noreturn nounwind function can be expected to never return in any way, and by
never returning it will also never have to restore any callee-saved registers
for its caller. This makes it possible to skip spills of those registers during
function entry, saving some stack space and time in the process. This is rather
useful for embedded targets with limited stack space.
Should fix PR9970.
Patch by myeisha (pmb).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329287
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Krzysztof Parzyszek [Thu, 5 Apr 2018 14:25:52 +0000 (14:25 +0000)]
[Hexagon] Remove default values from lambda parameters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329286
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Brian Gesiak [Thu, 5 Apr 2018 14:08:16 +0000 (14:08 +0000)]
[Lexicon] Add "ICE", internal compiler error
Test Plan:
1. `ninja docs-llvm-html`
2. Confirm that the rendered docs HTML contains the new "ICE" entry
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329285
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Andrea Di Biagio [Thu, 5 Apr 2018 13:59:52 +0000 (13:59 +0000)]
[MC] Fix spaces between values printed by EmitRegisterFileInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329284
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Sam Parker [Thu, 5 Apr 2018 13:46:17 +0000 (13:46 +0000)]
[DAGCombine] Revert r329160
Again, broke the big endian stage 2 builders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329283
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Sanjay Patel [Thu, 5 Apr 2018 13:24:26 +0000 (13:24 +0000)]
[InstCombine] cleanup; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329282
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Simon Pilgrim [Thu, 5 Apr 2018 13:11:36 +0000 (13:11 +0000)]
[SchedModel] Complete models shouldn't match against itineraries when they don't use them (PR35639)
For schedule models that don't use itineraries, checkCompleteness still checks that an instruction has a matching itinerary instead of skipping and going straight to matching the InstRWs. That doesn't seem to match what happens in TargetSchedule.cpp
This patch causes problems for a number of models that had been incorrectly flagged as complete.
Differential Revision: https://reviews.llvm.org/D43235
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329280
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Florian Hahn [Thu, 5 Apr 2018 13:07:39 +0000 (13:07 +0000)]
[LoopInterchange] Require asserts for test using -stats (NFC)
This fixes a buildbot failure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329279
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Alexander Kornienko [Thu, 5 Apr 2018 12:48:22 +0000 (12:48 +0000)]
Minor fix in docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329277
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Philip Pfaffe [Thu, 5 Apr 2018 12:42:12 +0000 (12:42 +0000)]
Revert "[Plugins] Add a slim plugin API to work together with the new PM"
This reverts commit
ecf3ba1ab45edb1b0fadce716a7facf50dca4fbb/r329273.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329276
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Andrea Di Biagio [Thu, 5 Apr 2018 11:36:50 +0000 (11:36 +0000)]
[llvm-mca] Remove flag -max-retire-per-cycle, and update the docs.
This is done in preparation for D45259.
With D45259, models can specify the size of the reorder buffer, and the retire
throughput directly via tablegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329274
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Philip Pfaffe [Thu, 5 Apr 2018 11:29:37 +0000 (11:29 +0000)]
[Plugins] Add a slim plugin API to work together with the new PM
Summary:
Add a new plugin API. This closes the gap between pass registration and out-of-tree passes for the new PassManager.
Unlike with the existing API, interaction with a plugin is always
initiated from the tools perspective. I.e., when a plugin is loaded, it
resolves and calls a well-known symbol `llvmGetPassPluginInfo` to obtain
details about the plugin. The fundamental motivation is to get rid of as
many global constructors as possible. The API exposed by the plugin
info is kept intentionally minimal.
Reviewers: chandlerc
Reviewed By: chandlerc
Subscribers: bollu, grosser, lksbhm, mgorny, llvm-commits
Differential Revision: https://reviews.llvm.org/D35258
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329273
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Simon Pilgrim [Thu, 5 Apr 2018 10:48:38 +0000 (10:48 +0000)]
[UpdateTestChecks] Moved core functionality of add_asm_checks into add_checks
As discussed on D45272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329270
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Florian Hahn [Thu, 5 Apr 2018 10:39:23 +0000 (10:39 +0000)]
[LoopInterchange] Add stats counter for number of interchanged loops.
Reviewers: samparker, karthikthecool, blitz.opensource
Reviewed By: samparker
Differential Revision: https://reviews.llvm.org/D45209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329269
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Simon Dardis [Thu, 5 Apr 2018 10:30:17 +0000 (10:30 +0000)]
[mips] Regenerate test before posting patch for constant multiplication (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329268
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Fedor Sergeev [Thu, 5 Apr 2018 10:29:37 +0000 (10:29 +0000)]
allow custom OptBisect classes set to LLVMContext
This patch introduces a way to set custom OptPassGate instances to LLVMContext.
A new instance field OptBisector and a new method setOptBisect() are added
to the LLVMContext classes. These changes allow to set a custom OptBisect class
that can make its own decisions on skipping optional passes.
Another important feature of this change is ability to set different instances
of OptPassGate to different LLVMContexts. So the different contexts can be used
independently in several compiling threads of one process.
One unit test is added.
Patch by Yevgeny Rouban.
Reviewers: andrew.w.kaylor, fedor.sergeev, vsk, dberlin, Eugene.Zelenko, reames, skatkov
Reviewed By: andrew.w.kaylor, fedor.sergeev
Differential Revision: https://reviews.llvm.org/D44464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329267
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Simon Pilgrim [Thu, 5 Apr 2018 10:26:13 +0000 (10:26 +0000)]
[UpdateTestChecks] Split core functionality of add_ir_checks into add_checks
Cherry picked from D45272, also added some setup for add_asm_checks to use add_checks as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329266
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Simon Pilgrim [Thu, 5 Apr 2018 09:50:58 +0000 (09:50 +0000)]
[UpdateTestChecks] Make add_asm_checks more like add_ir_checks
Towards merging them as mentioned on D45272
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329265
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Florian Hahn [Thu, 5 Apr 2018 09:48:45 +0000 (09:48 +0000)]
[LoopInterchange] Preserve LoopInfo after interchanging.
LoopInterchange relies on LoopInfo being up-to-date, so we should
preserve it after interchanging. This patch updates restructureLoops to
move the BBs of the interchanged loops to the right place.
Reviewers: davide, efriedma, karthikthecool, mcrosier
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D45278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329264
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Simon Pilgrim [Thu, 5 Apr 2018 09:30:42 +0000 (09:30 +0000)]
[UpdateTestChecks] Remove unnecessary return from add_ir_checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329262
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Clement Courbet [Thu, 5 Apr 2018 07:35:28 +0000 (07:35 +0000)]
[llvm-exegesis] Check for libpfm headers.
HAVE_LIBPFM is only defined if the libpfm headers are present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329261
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Puyan Lotfi [Thu, 5 Apr 2018 06:56:44 +0000 (06:56 +0000)]
[MIR-Canon] Fixing warnings in Non-assert builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329258
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Clement Courbet [Thu, 5 Apr 2018 05:57:23 +0000 (05:57 +0000)]
[llvm-exegesis] Suppress a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329257
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Craig Topper [Thu, 5 Apr 2018 05:19:36 +0000 (05:19 +0000)]
[X86] Revert r329251-329254
It's failing on the bots and I'm not sure why.
This reverts:
[X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents.
[X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128 which uses WriteShuffle256.
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
[X86] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329256
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Craig Topper [Thu, 5 Apr 2018 04:42:03 +0000 (04:42 +0000)]
[X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents.
Mostly vector load, store, and move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329254
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Craig Topper [Thu, 5 Apr 2018 04:42:02 +0000 (04:42 +0000)]
[X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128 which uses WriteShuffle256.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329253
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Craig Topper [Thu, 5 Apr 2018 04:42:01 +0000 (04:42 +0000)]
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge.
We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329252
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Craig Topper [Thu, 5 Apr 2018 04:41:59 +0000 (04:41 +0000)]
[X86] Auto-generate complete checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329251
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Taewook Oh [Thu, 5 Apr 2018 04:16:23 +0000 (04:16 +0000)]
[CallSiteSplitting] Do not perform callsite splitting inside landing pad
Summary:
If the callsite is inside landing pad, do not perform callsite splitting.
Callsite splitting uses utility function llvm::DuplicateInstructionsInSplitBetween, which eventually calls llvm::SplitEdge. llvm::SplitEdge calls llvm::SplitCriticalEdge with an assumption that the function returns nullptr only when the target edge is not a critical edge (and further assumes that if the return value was not nullptr, the predecessor of the original target edge always has a single successor because critical edge splitting was successful). However, this assumtion is not true because SplitCriticalEdge returns nullptr if the destination block is a landing pad. This invalid assumption results assertion failure.
Fundamental solution might be fixing llvm::SplitEdge to not to rely on the invalid assumption. However, it'll involve a lot of work because current API assumes that llvm::SplitEdge never fails. Instead, this patch makes callsite splitting to not to attempt splitting if the callsite is in a landing pad.
Attached test case will crash with assertion failure without the fix.
Reviewers: fhahn, junbuml, dberlin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45130
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329250
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Teresa Johnson [Thu, 5 Apr 2018 03:16:57 +0000 (03:16 +0000)]
[gold] Add debug-pass-manager option, and use it to test new-pass-manager
Summary: Follow up from r314963.
Reviewers: pcc
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45293
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329249
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Gerolf Hoflehner [Thu, 5 Apr 2018 02:44:46 +0000 (02:44 +0000)]
[IR] Upgrade comment token in objc retain release marker
Older compiler issued '#' instead of ';'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329248
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Puyan Lotfi [Thu, 5 Apr 2018 00:27:15 +0000 (00:27 +0000)]
[MIR-Canon] Improving performance by switching to named vregs.
No more skipping thounsands of vregs. Much faster running time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329246
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Puyan Lotfi [Thu, 5 Apr 2018 00:08:15 +0000 (00:08 +0000)]
[MIR-Canon] Adding support for multi-def -> user distance reduction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329243
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Sam Clegg [Wed, 4 Apr 2018 22:27:58 +0000 (22:27 +0000)]
[WebAssembly] Only write 32-bits for WebAssembly::OPERAND_OFFSET32
A bug was found where an offset of -1 would generate an encoding
of max int64 which is invalid in the binary format.
Differential Revision: https://reviews.llvm.org/D45280
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329238
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Peter Collingbourne [Wed, 4 Apr 2018 21:55:44 +0000 (21:55 +0000)]
AArch64: Implement support for the shadowcallstack attribute.
The implementation of shadow call stack on aarch64 is quite different to
the implementation on x86_64. Instead of reserving a segment register for
the shadow call stack, we reserve the platform register, x18. Any function
that spills lr to sp also spills it to the shadow call stack, a pointer to
which is stored in x18.
Differential Revision: https://reviews.llvm.org/D45239
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329236
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Vitaly Buka [Wed, 4 Apr 2018 21:46:27 +0000 (21:46 +0000)]
Don't inline @llvm.icall.branch.funnel
Summary: @llvm.icall.branch.funnel is musttail with variable number of
arguments. After inlining current backend can't separate call targets from call
arguments.
Reviewers: pcc
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D45116
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329235
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Zhaoshi Zheng [Wed, 4 Apr 2018 21:08:11 +0000 (21:08 +0000)]
[MemorySSA] Fix spelling errors in MemorySSA.cpp. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329230
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Evgeniy Stepanov [Wed, 4 Apr 2018 20:44:59 +0000 (20:44 +0000)]
hwasan: add -hwasan-match-all-tag flag
Sometimes instead of storing addresses as is, the kernel stores the address of
a page and an offset within that page, and then computes the actual address
when it needs to make an access. Because of this the pointer tag gets lost
(gets set to 0xff). The solution is to ignore all accesses tagged with 0xff.
This patch adds a -hwasan-match-all-tag flag to hwasan, which allows to ignore
accesses through pointers with a particular pointer tag value for validity.
Patch by Andrey Konovalov.
Differential Revision: https://reviews.llvm.org/D44827
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329228
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Jessica Paquette [Wed, 4 Apr 2018 19:13:31 +0000 (19:13 +0000)]
[MachineOutliner] Add `useMachineOutliner` target hook
The MachineOutliner has a bunch of target hooks that will call llvm_unreachable
if the target doesn't implement them. Therefore, if you enable the outliner on
such a target, it'll just crash. It'd be much better if it'd just *not* run
the outliner at all in this case.
This commit adds a hook to TargetInstrInfo that returns false by default.
Targets that implement the hook make it return true. The outliner checks the
return value of this hook to decide whether or not to continue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329220
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Eric Fiselier [Wed, 4 Apr 2018 19:01:51 +0000 (19:01 +0000)]
[Analysis] Support aligned new/delete functions.
Summary:
Clang's __builtin_operator_new/delete was recently taught about the aligned allocation overloads (r328134). This patch makes LLVM aware of them as well.
This allows the compiler to perform certain optimizations including eliding new/delete calls.
Reviewers: rsmith, majnemer, dblaikie, vsk, bkramer
Reviewed By: bkramer
Subscribers: ckennelly, llvm-commits
Differential Revision: https://reviews.llvm.org/D44769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329218
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Eric Fiselier [Wed, 4 Apr 2018 18:23:00 +0000 (18:23 +0000)]
Revert "[Analysis] Support aligned new/delete functions."
This reverts commit
bee3bbd9bdd3ab3364b8fb0cdb6326bc1ae740e0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329217
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Mandeep Singh Grang [Wed, 4 Apr 2018 18:20:28 +0000 (18:20 +0000)]
[AArch64] Change std::sort to llvm::sort in response to r327219
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.
To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.
Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches.
Reviewers: t.p.northover, jmolloy, RKSimon, rengolin
Reviewed By: rengolin
Subscribers: dexonsmith, rengolin, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D44853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329216
91177308-0d34-0410-b5e6-
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Eric Fiselier [Wed, 4 Apr 2018 18:12:01 +0000 (18:12 +0000)]
[Analysis] Support aligned new/delete functions.
Summary:
Clang's __builtin_operator_new/delete was recently taught about the aligned allocation overloads (r328134). This patch makes LLVM aware of them as well.
This allows the compiler to perform certain optimizations including eliding new/delete calls.
Reviewers: rsmith, majnemer, dblaikie, vsk, bkramer
Reviewed By: bkramer
Subscribers: ckennelly, llvm-commits
Differential Revision: https://reviews.llvm.org/D44769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329215
91177308-0d34-0410-b5e6-
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Jessica Paquette [Wed, 4 Apr 2018 18:07:07 +0000 (18:07 +0000)]
[MachineOutliner] Fix typo; NFC
There was a typo in an unreachable statement in one of the outliner target
hooks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329213
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 4 Apr 2018 17:54:19 +0000 (17:54 +0000)]
[X86] Separate BSWAP32r and BSWAP64r scheduling data in SandyBridge/Haswell/Broadwell/Skylake scheduler models.
The BSWAP64r version is 2 uops and BSWAP32r is only 1 uop. The regular expressions also looked for a non-existant BSWAP16r.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329211
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Zachary Turner [Wed, 4 Apr 2018 17:41:05 +0000 (17:41 +0000)]
Fix a compilation failure with non MSVC compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329209
91177308-0d34-0410-b5e6-
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Zachary Turner [Wed, 4 Apr 2018 17:29:09 +0000 (17:29 +0000)]
[llvm-pdbutil] Add the ability to explain binary files.
Using this, you can use llvm-pdbutil to export the contents of a
stream to a binary file, then run explain on the binary file so
that it treats the offset as an offset into the stream instead
of an offset into a file. This makes it easy to compare the
contents of the same stream from two different files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329207
91177308-0d34-0410-b5e6-
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Lei Huang [Wed, 4 Apr 2018 16:43:50 +0000 (16:43 +0000)]
[Power9]Legalize and emit code for quad-precision fma instructions
Legalize and emit code for the following quad-precision fma:
* xsmaddqp
* xsnmaddqp
* xsmsubqp
* xsnmsubqp
Differential Revision: https://reviews.llvm.org/D44843
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329206
91177308-0d34-0410-b5e6-
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Pavel Labath [Wed, 4 Apr 2018 14:54:08 +0000 (14:54 +0000)]
Fix build breakage from r329201
Some compilers do not like having an enum type and a variable with the
same name (AccelTableKind). I rename the variable to TheAccelTableKind.
Suggestions for a better name welcome.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329202
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Pavel Labath [Wed, 4 Apr 2018 14:42:14 +0000 (14:42 +0000)]
Re-commit r329179 after fixing build&test issues
- MSVC was not OK with a static_assert referencing a non-static member
variable, even though it was just in a sizeof(expression). I move the
assert into the emit function, where it is probably more useful.
- Tests were failing in builds which did not have the X86 target
configured. Since this functionality is not target-specific, I have
removed the target specifiers from the .ll files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329201
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Clement Courbet [Wed, 4 Apr 2018 14:32:09 +0000 (14:32 +0000)]
[llvm-exegesis] Temporarily disable a few tests.
These are failing on clang-ppc64le-linux-lnt, though the subdirectory is
not even supposed to be built in CMakeLists. Disable the tests until we
understand what's going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329200
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Roman Lebedev [Wed, 4 Apr 2018 14:10:13 +0000 (14:10 +0000)]
[InstCombine] [NFC] Add tests for getting rid of select of bittest (PR36950 / PR17564)
Summary: See [[ https://bugs.llvm.org/show_bug.cgi?id=36950 | PR36950 ]], [[ https://bugs.llvm.org/show_bug.cgi?id=17564 | PR17564 ]], D45065, D45108
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D45107
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329198
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Dmitry Preobrazhensky [Wed, 4 Apr 2018 13:54:55 +0000 (13:54 +0000)]
[AMDGPU][MC] Enabled instruction TBUFFER_LOAD_FORMAT_XYZ for SI/CI
See bug 36958: https://bugs.llvm.org/show_bug.cgi?id=36958
Differential Revision: https://reviews.llvm.org/D45099
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329197
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Simon Pilgrim [Wed, 4 Apr 2018 13:53:51 +0000 (13:53 +0000)]
[SLPVectorizer][X86] Regenerate some tests. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329196
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 4 Apr 2018 13:33:21 +0000 (13:33 +0000)]
[llvm-exegesis] Temporarily disable some tests.
The tests fail on clang-x86-windows-msvc2015:
unknown file: error: SEH exception with code 0x3221225477 thrown in the test body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329195
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Clement Courbet [Wed, 4 Apr 2018 13:30:23 +0000 (13:30 +0000)]
[llvm-exegesis] Only run unit tests on x86_64 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329193
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Simon Pilgrim [Wed, 4 Apr 2018 13:25:45 +0000 (13:25 +0000)]
[X86][Btver2] Strip unnecessary check prefixes from resources tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329192
91177308-0d34-0410-b5e6-
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Nico Weber [Wed, 4 Apr 2018 13:23:24 +0000 (13:23 +0000)]
Remove llvm-build's --write-make-fragment which looks like a remnant from the autoconf build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329191
91177308-0d34-0410-b5e6-
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Nico Weber [Wed, 4 Apr 2018 13:06:22 +0000 (13:06 +0000)]
Revert r329179 (and follow-up unsuccessful fix attempts 329184, 329186); it doesn't build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329190
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Tim Corringham [Wed, 4 Apr 2018 13:02:09 +0000 (13:02 +0000)]
Add AMDPAL Code Conventions section to AMD docs
Summary:
This is a first version of the AMDPAL code conventions.
Further updates will undoubtably be required to fully
document AMDPAL.
Subscribers: nhaehnle, llvm-commits
Differential Revision: https://reviews.llvm.org/D45246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329188
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Dmitry Preobrazhensky [Wed, 4 Apr 2018 13:01:17 +0000 (13:01 +0000)]
[AMDGPU][MC] Added support of 3-element addresses for MIMG instructions
See bug 35999: https://bugs.llvm.org/show_bug.cgi?id=35999
Differential Revision: https://reviews.llvm.org/D45084
Reviewers: artem.tamazov, arsenm, timcorringham
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329187
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Nico Weber [Wed, 4 Apr 2018 12:58:49 +0000 (12:58 +0000)]
Attempt to fix bots more after r329179.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329186
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 4 Apr 2018 12:58:41 +0000 (12:58 +0000)]
[llvm-exegesis] Add missing link libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329185
91177308-0d34-0410-b5e6-
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Nico Weber [Wed, 4 Apr 2018 12:54:34 +0000 (12:54 +0000)]
Attempt to fix bots after r329179.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329184
91177308-0d34-0410-b5e6-
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Nico Weber [Wed, 4 Apr 2018 12:37:44 +0000 (12:37 +0000)]
Sort targetgen calls in lib/Target/*/CMakeLists.
Makes it easier to see mistakes such as the one fixed in r329178 and makes
the different target CMakeLists more consistent.
Also remove some stale-looking comments from the Nios2 target cmakefile.
No intended behavior change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329181
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Pavel Labath [Wed, 4 Apr 2018 12:28:20 +0000 (12:28 +0000)]
[CodeGen] Generate DWARF v5 Accelerator Tables
Summary:
This patch adds a DwarfAccelTableEmitter class, which generates an
accelerator table, as specified in DWARF v5 standard. At the moment it
only generates a DIE offset column and (if we are indexing more than one
compile unit) a CU column.
Indexing type units is not currently supported, as we don't even have
the ability to generate DWARF v5-compatible compile units.
The implementation is not data-source agnostic like the one generating
apple tables. This was not necessary as we currently only have one user
of this code, and without a second user it was not obvious to me how to
best abstract this. (The difference between these tables and the apple
ones is that they need a lot more metadata about the debug info they are
indexing).
The generation is triggered by the --accel-tables argument, which
supersedes the --dwarf-accel-tables arg -- the latter was a simple
on-off switch, but not we can choose between two kinds of accelerator
tables we can generate.
This is tested by parsing the generated tables with llvm-dwarfdump and
the DWARFVerifier, and I've also checked that GNU readelf is able to
make sense of the tables.
Differential Revision: https://reviews.llvm.org/D43286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329179
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Nico Weber [Wed, 4 Apr 2018 12:27:43 +0000 (12:27 +0000)]
Remove duplicate tablegen lines from AVR target.
They were added in r285274, in what looks like a merge mishap.
AVRGenMCCodeEmitter.inc is the only non-dupe tablegen invocation added in that
revision.
Also sort the tablegen lines to make this easier to spot in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329178
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Clement Courbet [Wed, 4 Apr 2018 12:12:38 +0000 (12:12 +0000)]
[llvm-exegesis] Do not initialize FileDescriptor when libpfm is not
available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329177
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 4 Apr 2018 12:01:46 +0000 (12:01 +0000)]
[llvm-exegesis] Fix compilation on lld-x86_64-darwin13
YAMLTraits does not know how to serialize `size_t` portably. Use `int`
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329176
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Clement Courbet [Wed, 4 Apr 2018 12:01:43 +0000 (12:01 +0000)]
[llvm-exegesis][NFC] Fix compilation warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329175
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 4 Apr 2018 12:01:38 +0000 (12:01 +0000)]
[llvm-exegesis][NFC] Fix a few warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329174
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Andrea Di Biagio [Wed, 4 Apr 2018 11:53:13 +0000 (11:53 +0000)]
[Tablegen] Slightly refactor method SubtargetEmitter::EmitExtraProcessorInfo.
This patch moves most of the logic from EmitExtraProcessorInfo to a couple of
helper functions. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329173
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Clement Courbet [Wed, 4 Apr 2018 11:48:15 +0000 (11:48 +0000)]
[llvm-exegesis] Fix build when libpfm is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329172
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 4 Apr 2018 11:45:53 +0000 (11:45 +0000)]
[llvm-exegesis] Fix compilation on some clang versions.
default initialization of an object of const type 'const llvm::DebugLoc' requires a user-provided default constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329171
91177308-0d34-0410-b5e6-
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Benjamin Kramer [Wed, 4 Apr 2018 11:45:11 +0000 (11:45 +0000)]
Make helpers static. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329170
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Clement Courbet [Wed, 4 Apr 2018 11:37:06 +0000 (11:37 +0000)]
Re-land r329156 "Add llvm-exegesis tool."
Fixed to depend on and initialize the native target instead of X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329169
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Simon Pilgrim [Wed, 4 Apr 2018 11:14:12 +0000 (11:14 +0000)]
[X86][CostModel] Use generic SSE levels instead of particular CPUs for shuffle costs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329168
91177308-0d34-0410-b5e6-
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Nicolai Haehnle [Wed, 4 Apr 2018 10:58:54 +0000 (10:58 +0000)]
AMDGPU: Dimension-aware image intrinsics
Summary:
These new image intrinsics contain the texture type as part of
their name and have each component of the address/coordinate as
individual parameters.
This is a preparatory step for implementing the A16 feature, where
coordinates are passed as half-floats or -ints, but the Z compare
value and texel offsets are still full dwords, making it difficult
or impossible to distinguish between A16 on or off in the old-style
intrinsics.
Additionally, these intrinsics pass the 'texfailpolicy' and
'cachectrl' as i32 bit fields to reduce operand clutter and allow
for future extensibility.
v2:
- gather4 supports 2darray images
- fix a bug with 1D images on SI
Change-Id: I099f309e0a394082a5901ea196c3967afb867f04
Reviewers: arsenm, rampitec, b-sumner
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D44939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329166
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Nicolai Haehnle [Wed, 4 Apr 2018 10:58:15 +0000 (10:58 +0000)]
StructurizeCFG: Test for branch divergence correctly
Fixes cases like the new test @nonuniform. In that test, %cc itself
is a uniform value; however, when reading it after the end of the loop in
basic block %if, its value is effectively non-uniform, so the branch is
non-uniform.
This problem was encountered in
https://bugs.freedesktop.org/show_bug.cgi?id=103743; however, this change
in itself is not sufficient to fix that bug, as there is another issue
in the AMDGPU backend.
As discovered after committing an earlier version of this change, this
exposes a subtle interaction between this pass and DivergenceAnalysis:
since we remove and re-create branch instructions, we can no longer rely
on DivergenceAnalysis for branches in subregions that were already
processed by the pass.
Explicitly remove branch instructions from DivergenceAnalysis to
avoid dangling pointers as a matter of defensive programming, and
change how we detect non-uniform subregions.
Change-Id: I32bbffece4a32f686fab54964dae1a5dd72949d4
Differential Revision: https://reviews.llvm.org/D43743
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329165
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Nicolai Haehnle [Wed, 4 Apr 2018 10:57:58 +0000 (10:57 +0000)]
AMDGPU: Fix copying i1 value out of loop with non-uniform exit
Summary:
When an i1-value is defined inside of a loop and used outside of it, we
cannot simply use the SGPR bitmask from the loop's last iteration.
There are also useful and correct cases of an i1-value being copied between
basic blocks, e.g. when a condition is computed outside of a loop and used
inside it. The concept of dominators is not sufficient to capture what is
going on, so I propose the notion of "lane-dominators".
Fixes a bug encountered in Nier: Automata.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103743
Change-Id: If37b969ddc71d823ab3004aeafb9ea050e45bd9a
Reviewers: arsenm, rampitec
Subscribers: kzhuravl, wdng, mgorny, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D40547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329164
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John Brawn [Wed, 4 Apr 2018 10:12:53 +0000 (10:12 +0000)]
[AArch64] Add patterns matching (fabs (fsub x y)) to (fabd x y)
Differential Revision: https://reviews.llvm.org/D44573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329163
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Sam Parker [Wed, 4 Apr 2018 09:26:56 +0000 (09:26 +0000)]
[DAGCombine] Improve ReduceLoadWidth for SRL
Recommitting rL321259. Previosuly this caused an issue with PPCBE but
I didn't receieve a reproducer and didn't have the time to follow up.
If the issue appears again, please provide a reproducer so I can fix
it.
Original commit message:
If the SRL node is only used by an AND, we may be able to set the
ExtVT to the width of the mask, making the AND redundant. To support
this, another check has been added in isLegalNarrowLoad which queries
whether the load is valid.
Differential Revision: https://reviews.llvm.org/D41350
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329160
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Mikhail Maltsev [Wed, 4 Apr 2018 08:54:19 +0000 (08:54 +0000)]
[ARM] Do not convert some vmov instructions
Summary:
Patch https://reviews.llvm.org/D44467 implements conversion of invalid
vmov instructions into valid ones. It turned out that some valid
instructions also get converted, for example
vmov.i64 d2, #0xff00ff00ff00ff00 ->
vmov.i16 d2, #0xff00
Such behavior is incorrect because according to the ARM ARM section
F2.7.7 Modified immediate constants in T32 and A32 Advanced SIMD
instructions, "On assembly, the data type must be matched in the table
if possible."
This patch fixes the isNEONmovReplicate check so that the above
instruction is not modified any more.
Reviewers: rengolin, olista01
Reviewed By: rengolin
Subscribers: javed.absar, kristof.beyls, rogfer01, llvm-commits
Differential Revision: https://reviews.llvm.org/D44678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329158
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 4 Apr 2018 08:22:54 +0000 (08:22 +0000)]
Revert r329156 "Add llvm-exegesis tool."
Breaks a bunch of bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329157
91177308-0d34-0410-b5e6-
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Clement Courbet [Wed, 4 Apr 2018 08:13:32 +0000 (08:13 +0000)]
Add llvm-exegesis tool.
Summary:
[llvm-exegesis][RFC] Automatic Measurement of Instruction Latency/Uops
This is the code corresponding to the RFC "llvm-exegesis Automatic Measurement of Instruction Latency/Uops".
The RFC is available on the LLVM mailing lists as well as the following document
for easier reading:
https://docs.google.com/document/d/1QidaJMJUyQdRrFKD66vE1_N55whe0coQ3h1GpFzz27M/edit?usp=sharing
Subscribers: mgorny, gchatelet, orwant, llvm-commits
Differential Revision: https://reviews.llvm.org/D44519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329156
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 4 Apr 2018 07:00:24 +0000 (07:00 +0000)]
[X86] Use the same predicate for the load for PMOVSXBQ and PMOVZXBQ.
These both use a 16-bit load, but one used loadi16_anyext and the other used extloadi32i16. The only difference between them is that loadi16_anyext checked that the load was at least 2 byte aligned and non-volatile. But the alignment doesn't matter here. Just use extloadi32i16 for both.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329154
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 4 Apr 2018 07:00:19 +0000 (07:00 +0000)]
[X86] Use loadi16/loadi32 predicates in multiply patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329153
91177308-0d34-0410-b5e6-
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Craig Topper [Wed, 4 Apr 2018 07:00:16 +0000 (07:00 +0000)]
[X86] Remove more dead code left over from the handling of i8/i16 UMUL_LOHI/SMUL_LOHI that is no longer needed. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329152
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Max Kazantsev [Wed, 4 Apr 2018 05:46:47 +0000 (05:46 +0000)]
[SCEV] Prove implications for SCEVUnknown Phis
This patch teaches SCEV how to prove implications for SCEVUnknown nodes that are Phis.
If we need to prove `Pred` for `LHS, RHS`, and `LHS` is a Phi with possible incoming values
`L1, L2, ..., LN`, then if we prove `Pred` for `(L1, RHS), (L2, RHS), ..., (LN, RHS)` then we can also
prove it for `(LHS, RHS)`. If both `LHS` and `RHS` are Phis from the same block, it is sufficient
to prove the predicate for values that come from the same predecessor block.
The typical case that it handles is that we sometimes need to prove that `Phi(Len, Len - 1) >= 0`
given that `Len > 0`. The new logic was added to `isImpliedViaOperations` and only uses it and
non-recursive reasoning to prove the facts we need, so it should not hurt compile time a lot.
Differential Revision: https://reviews.llvm.org/D44001
Reviewed By: anna
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329150
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Craig Topper [Wed, 4 Apr 2018 04:38:55 +0000 (04:38 +0000)]
[X86] Remove dead code for handling i8/i16 UMUL_LOHI/SMUL_LOHI from X86ISelDAGToDAG.cpp. NFC
These are promoted to i16/i32 multiplies by a DAG combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329147
91177308-0d34-0410-b5e6-
96231b3b80d8