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Sanjay Patel [Mon, 26 Feb 2018 16:02:45 +0000 (16:02 +0000)]
[InstCombine] allow fdiv folds with less than fully 'fast' ops
Note: gcc appears to allow this fold with -freciprocal-math alone,
but clang/llvm require more than that with this patch. The wording
in the definitions seems fuzzy enough that it could go either way,
but we'll err on the conservative side of FMF interpretation.
This patch also changes the newly created fmul to have FMF propagated
by the last fdiv rather than intersecting the FMF of the fdivs. This
matches the behavior of other folds near here. The new fmul is only
used to produce an intermediate op for the final fdiv result, so it
shouldn't be any stricter than that result. The previous behavior
could result in dropping FMF via other folds in instcombine or CSE.
Differential Revision: https://reviews.llvm.org/D43398
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326098
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Simon Pilgrim [Mon, 26 Feb 2018 15:55:25 +0000 (15:55 +0000)]
[X86][AVX] Add AVX1 PSAD tests
Cleanup check-prefixes to share more AVX/AVX512 codegen checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326097
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Ilya Biryukov [Mon, 26 Feb 2018 15:54:59 +0000 (15:54 +0000)]
Revert r326092: [gtest] Add PrintTo overload for StringRef.
It seems to break the following buildbot:
http://lab.llvm.org:8011/builders/sanitizer-windows/builds/24729
Will resubmit after investigating and fixing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326096
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Francis Visoiu Mistrih [Mon, 26 Feb 2018 15:23:42 +0000 (15:23 +0000)]
[CodeGen] Don't omit any redundant information in -debug output
In r322867, we introduced IsStandalone when printing MIR in -debug
output. The default behaviour for that was:
1) If any of MBB, MI, or MO are -debug-printed separately, don't omit any
redundant information.
2) When -debug-printing a MF entirely, don't print any redundant
information.
3) When printing MIR, don't print any redundant information.
I'd like to change 2) to:
2) When -debug-printing a MF entirely, don't omit any redundant information.
Differential Revision: https://reviews.llvm.org/D43337
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326094
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Simon Pilgrim [Mon, 26 Feb 2018 15:21:58 +0000 (15:21 +0000)]
[X86][SSE] Regenerate PSAD tests
Fixes scary typo in a check that lost the end digit off a reg#...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326093
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Ilya Biryukov [Mon, 26 Feb 2018 15:19:26 +0000 (15:19 +0000)]
[gtest] Add PrintTo overload for StringRef.
Summary:
It was printed using code for generic containers before, resulting in
unreadable output.
Reviewers: sammccall, labath
Reviewed By: sammccall, labath
Subscribers: labath, zturner, llvm-commits
Differential Revision: https://reviews.llvm.org/D43330
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326092
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Jonas Devlieghere [Mon, 26 Feb 2018 15:16:42 +0000 (15:16 +0000)]
Re-land: "[Support] Replace HashString with djbHash."
This patch removes the HashString function from StringExtraces and
replaces its uses with calls to djbHash from DJB.h.
This change is *almost* NFC. While the algorithm is identical, the
djbHash implementation in StringExtras used 0 as its default seed while
the implementation in DJB uses 5381. The latter has been shown to result
in less collisions and improved avalanching and is used by the DWARF
accelerator tables.
Because some test were implicitly relying on the hash order, I've
reverted to using zero as a seed for the following two files:
lld/include/lld/Core/SymbolTable.h
llvm/lib/Support/StringMap.cpp
Differential revision: https://reviews.llvm.org/D43615
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326091
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Tim Renouf [Mon, 26 Feb 2018 14:46:43 +0000 (14:46 +0000)]
[AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader
Summary:
With OS type AMDPAL, the scratch descriptor is hardwired to be loaded
from offset 0 of the global information table, whose low pointer is
passed in s0. For a merge shader on gfx9+, it needs to be s8 instead, as
the hardware reserves s0-s7.
Reviewers: kzhuravl
Subscribers: arsenm, nhaehnle, dstuttard, llvm-commits, t-tye, yaxunl, wdng, kzhuravl
Differential Revision: https://reviews.llvm.org/D42203
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326088
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Tim Renouf [Mon, 26 Feb 2018 14:42:13 +0000 (14:42 +0000)]
[LiveIntervals] Handle moving up dead partial write
Summary:
In the test case, the machine scheduler moves a dead write to a subreg
up into the middle of a segment of the overall reg's live range, where
the segment had liveness only for other subregs in the reg.
handleMoveUp created an invalid live range, causing an assert a bit
later.
This commit fixes it to handle that situation. The segment is split in
two at the insertion point, and the part after the split, and any
subsequent segments up to the old position, are changed to be defined by
the moved def.
V2: Better test.
Subscribers: MatzeB, nhaehnle, llvm-commits
Differential Revision: https://reviews.llvm.org/D43478
Change-Id: Ibc42445ddca84e79ad1f616401015d22bc63832e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326087
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David Zarzycki [Mon, 26 Feb 2018 13:05:18 +0000 (13:05 +0000)]
Test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326085
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Jonas Devlieghere [Mon, 26 Feb 2018 12:05:18 +0000 (12:05 +0000)]
Revert "[Support] Replace HashString with djbHash."
It looks like some of our tests depend on the ordering of hashed values.
I'm reverting my changes while I try to reproduce and fix this locally.
Failing builds:
lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/18388
lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/6743
lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-windows10pro-fast/builds/15607
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326082
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Jonas Devlieghere [Mon, 26 Feb 2018 11:30:13 +0000 (11:30 +0000)]
[Support] Replace HashString with djbHash.
This removes the HashString function from StringExtraces and replaces
its uses with calls to djbHash from DJB.h
This is *almost* NFC. While the algorithm is identical, the djbHash
implementation in StringExtras used 0 as its seed while the
implementation in DJB uses 5381. The latter has been shown to result in
less collisions and improved avalanching.
https://reviews.llvm.org/D43615
(cherry picked from commit
77f7f965bc9499a9ae768a296ca5a1f7347d1d2c)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326081
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Benjamin Kramer [Mon, 26 Feb 2018 11:07:25 +0000 (11:07 +0000)]
[WebAssembly] Relax constexpr for old standard libraries.
This will still be constexpr when the standard library supports it, but
doesn't force constexpr. Old libraries will get a global constructor,
which is not too bad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326080
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Renato Golin [Mon, 26 Feb 2018 11:06:36 +0000 (11:06 +0000)]
[LV] Move isLegalMasked* functions from Legality to CostModel
All SIMD architectures can emulate masked load/store/gather/scatter
through element-wise condition check, scalar load/store, and
insert/extract. Therefore, bailing out of vectorization as legality
failure, when they return false, is incorrect. We should proceed to cost
model and determine profitability.
This patch is to address the vectorizer's architectural limitation
described above. As such, I tried to keep the cost model and
vectorize/don't-vectorize behavior nearly unchanged. Cost model tuning
should be done separately.
Please see
http://lists.llvm.org/pipermail/llvm-dev/2018-January/120164.html for
RFC and the discussions.
Closes D43208.
Patch by: Hideki Saito <hideki.saito@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326079
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Florian Hahn [Mon, 26 Feb 2018 10:46:25 +0000 (10:46 +0000)]
[LoopInterchange] Add test case for D43236.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326078
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Florian Hahn [Mon, 26 Feb 2018 10:45:25 +0000 (10:45 +0000)]
[LoopInterchange] Loops with empty dependency matrix are safe.
The dependency matrix is only empty if no conflicting load/store
instructions have been found. In that case, it is safe to interchange.
For the LLVM test-suite, after this change around 1900 loops are
interchanged, whereas it is 15 before this change. On cortex-a57,
this gives an improvement of -0.57% on the geomean execution
time of SPEC2006, SPEC2000 and the test-suite. There are a
few small perf regressions, but I think we can improve on those
by making the cost model better.
Reviewers: karthikthecool, mcrosier
Reviewed by: karthikthecool
Differential Revision: https://reviews.llvm.org/D43236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326077
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Andrew V. Tischenko [Mon, 26 Feb 2018 09:43:21 +0000 (09:43 +0000)]
The final step to close D41278 [MachineCombiner] Improve debug output (NFC).
Differential Revision: https://reviews.llvm.org/D41278
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326074
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Serguei Katkov [Mon, 26 Feb 2018 09:26:41 +0000 (09:26 +0000)]
[SCEV] Factor out getUsedLoops
The patch introduces the new function in ScalarEvolution to get
all loops used in specified SCEV.
This is a preparation for re-writing isKnownPredicate utility as
described in https://reviews.llvm.org/D42417.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43504
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326072
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Serguei Katkov [Mon, 26 Feb 2018 08:40:18 +0000 (08:40 +0000)]
[SCEV] Introduce SCEVPostIncRewriter
The patch introduces the SCEVPostIncRewriter rewriter which
is similar to SCEVInitRewriter but rewrites AddRec with post increment
value of this AddRec.
This is a preparation for re-writing isKnownPredicate utility as
described in https://reviews.llvm.org/D42417.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326071
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Jonas Paulsson [Mon, 26 Feb 2018 08:03:32 +0000 (08:03 +0000)]
[XCore] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: Robert Lytton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326069
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Craig Topper [Mon, 26 Feb 2018 07:48:17 +0000 (07:48 +0000)]
[X86] Add avx1 command line to madd.ll to show splitting and concatenating 256-bit operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326068
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Serguei Katkov [Mon, 26 Feb 2018 07:08:56 +0000 (07:08 +0000)]
[SCEV] Extends the SCEVInitRewriter
The patch introduces an additional parameter IgnoreOtherLoops to SCEVInitRewriter.
if it is equal to true then rewriter will not invalidate result in case
SCEV depends on other loops then specified during creation.
The patch does not change the default behavior.
This is a preparation for re-writing isKnownPredicate utility as
described in https://reviews.llvm.org/D42417.
Reviewers: sanjoy, mkazantsev, reames
Reviewed By: sanjoy
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D43498
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326067
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Craig Topper [Mon, 26 Feb 2018 04:43:24 +0000 (04:43 +0000)]
[X86] Don't use getZExtValue when we have no idea how large the input elements are.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326066
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Craig Topper [Mon, 26 Feb 2018 02:16:34 +0000 (02:16 +0000)]
[X86] Use SelectionDAG::SplitVectorOperand to simplify some code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326065
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Craig Topper [Mon, 26 Feb 2018 02:16:33 +0000 (02:16 +0000)]
[X86] Simplify the ReplaceNodeResults code for X86ISD::AVG.
This code seemed to try to widen to 128, 256, or 512 bit vectors, but we only create X86ISD::AVG with a power of 2 number of elements. This means the only nodes that need to be legalized are less than 128-bits and need to be widened up to 128 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326064
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Craig Topper [Mon, 26 Feb 2018 02:16:31 +0000 (02:16 +0000)]
[X86] Remove VT.isSimple() check from detectAVGPattern.
Which types are considered 'simple' is a function of the requirements of all targets that LLVM supports. That shouldn't directly affect what types we are able to handle. The remainder of this code checks that the number of elements is a power of 2 and takes care of splitting down to a legal size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326063
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Nicolai Haehnle [Sun, 25 Feb 2018 20:50:17 +0000 (20:50 +0000)]
TableGen: Remove VarInit::getFieldType
It is redundant with the implementation in TypedInit.
Change-Id: I8ab1fb5c77e4923f7eb3ffae5889f0f8af6093b4
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43678
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326061
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Nicolai Haehnle [Sun, 25 Feb 2018 20:50:11 +0000 (20:50 +0000)]
TableGen: Get rid of Init::getFieldInit
Summary:
FieldInit will just rely on the standardized resolving mechanism to give
us DefInits for folding, thus simplifying the code.
Unlike the removal of resolveListElementReference, this shouldn't have
performance implications, because DefInits do not recurse inside their
record.
Change-Id: Id4544c774c9d9ee92f293615af6ecff706453f21
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326060
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Nicolai Haehnle [Sun, 25 Feb 2018 20:50:04 +0000 (20:50 +0000)]
TableGen: Remove Init::resolveListElementReference
Summary:
Resolving a VarListElementInit should just resolve the list and then
take its element. This eliminates a lot of duplicated logic and
simplifies the next steps of refactoring resolveReferences.
This does potentially cause sub-elements of the entire list to be
resolved resulting in more work, but I didn't notice a measurable
change in performance, and a later patch adds a caching mechanism that
covers at least the common case of `var[i]` in a more generic way.
Change-Id: I7b59185b855c7368585c329c31e5be38c5749dac
Reviewers: arsenm, craig.topper, tra, MartinO
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D43562
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326059
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Mandeep Singh Grang [Sun, 25 Feb 2018 19:52:34 +0000 (19:52 +0000)]
[DebugInfo] Stable sort symbols to remove non-deterministic ordering
Summary: This fixes failure in DebugInfo/X86/multiple-aranges.ll uncovered by D39245.
Reviewers: rafael, echristo, probinson
Reviewed By: probinson
Subscribers: probinson, llvm-commits, JDevlieghere
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D39950
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326056
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Craig Topper [Sun, 25 Feb 2018 06:51:52 +0000 (06:51 +0000)]
[InstSimplify] Add test cases for removal of vector fabs on known positive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326050
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Craig Topper [Sun, 25 Feb 2018 06:51:51 +0000 (06:51 +0000)]
[InstSimplify] Remove unused parameter from test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326049
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Craig Topper [Sun, 25 Feb 2018 06:21:04 +0000 (06:21 +0000)]
[X86] Use SDNode instead of SDPatternOperator. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326048
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Simon Pilgrim [Sat, 24 Feb 2018 20:59:14 +0000 (20:59 +0000)]
[TargetLowering] SimplifyDemandedVectorElts - pass demanded elts through ADD/SUB ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326044
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Simon Pilgrim [Sat, 24 Feb 2018 19:28:34 +0000 (19:28 +0000)]
[TargetLowering] SimplifyDemandedVectorElts - pass demanded elts through TRUNCATE ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326043
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Craig Topper [Sat, 24 Feb 2018 18:58:08 +0000 (18:58 +0000)]
[X86] Add cvt tests to avx512vl-intrinsics-fast-isel.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326042
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Craig Topper [Sat, 24 Feb 2018 18:58:07 +0000 (18:58 +0000)]
[X86] Allow int_x86_sse2_cvtps2dq and int_x86_avx_cvt_ps2dq_256 to select EVEX encoded instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326041
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Craig Topper [Sat, 24 Feb 2018 18:58:02 +0000 (18:58 +0000)]
[X86] Remove GCCBuiltin from some intrinsics that are no longer used by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326040
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Adam Nemet [Sat, 24 Feb 2018 17:29:09 +0000 (17:29 +0000)]
Revert "StructurizeCFG: Test for branch divergence correctly"
This reverts commit r325881.
Breaks many bots
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326037
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Scott Linder [Sat, 24 Feb 2018 16:25:43 +0000 (16:25 +0000)]
[DebugInfo] Fix buildbot failure on non-X86 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326035
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Simon Pilgrim [Sat, 24 Feb 2018 14:06:39 +0000 (14:06 +0000)]
[X86][SSE] combineSubToSubus - support v8i64 handling from SSSE3
Our UMIN/UMAX, vector truncation and shuffle combining is good enough to efficiently handle v8i64 with the number of leading zeros that are necessary for PSUBUS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326034
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Simon Pilgrim [Sat, 24 Feb 2018 13:39:13 +0000 (13:39 +0000)]
[X86][SSE] combineSubToSubus - support v8i32 handling from SSSE3 (not SSE41)
Now that UMIN etc are Legal/Custom for SSE2+, we can efficiently match SUBUS v8i32 cases from SSSE3 which can perform efficient truncation with PSHUFB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326033
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Simon Pilgrim [Sat, 24 Feb 2018 12:44:12 +0000 (12:44 +0000)]
[X86][SSE] combineSubToSubus - begun generalizing to work with any type sizes with SplitBinaryOpsAndApply
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326030
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Simon Pilgrim [Sat, 24 Feb 2018 12:27:02 +0000 (12:27 +0000)]
Fix spelling in comment. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326029
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Jonas Paulsson [Sat, 24 Feb 2018 08:24:31 +0000 (08:24 +0000)]
[Sparc] Return true in enableMultipleCopyHints().
Enable multiple COPY hints to eliminate more COPYs during register allocation.
Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.
Review: James Y Knight
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326028
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Craig Topper [Sat, 24 Feb 2018 07:02:24 +0000 (07:02 +0000)]
[X86] Remove GCCBuiltin from some intrinsics that are no longer used by clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326026
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Craig Topper [Sat, 24 Feb 2018 03:15:54 +0000 (03:15 +0000)]
[X86] Use SelectionDAG::getNot instead of implementing manually. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326020
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Stanislav Mekhanoshin [Sat, 24 Feb 2018 01:32:32 +0000 (01:32 +0000)]
[AMDGPU] Shrinking V_SUBBREV_U32
V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when
we try to commute V_SUBB_U32 in order to shrink it we do not then
process V_SUBBREV_U32 and it stay VOP3. This is fixed.
Differential Revision: https://reviews.llvm.org/D43699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326011
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Pavel Labath [Sat, 24 Feb 2018 00:54:31 +0000 (00:54 +0000)]
Fix build breakage from r326003
- an ambiguous reference to Optional<T> in llvm-dwarfdump.cpp (fixed
with an explicit prefix).
- a missing base class initialization in Entry copy constructor (fixed
by using the implicitly default constructor, which is possible after
some changes which were done during review).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326006
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Alexander Shaposhnikov [Sat, 24 Feb 2018 00:41:01 +0000 (00:41 +0000)]
[llvm-objcopy] Fix typo in setSymTab
This diff fixes the name of the argument of
setSymTab and makes setSymTab/setStrTab private
(to make the public interface a bit cleaner).
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D43661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326005
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Heejin Ahn [Sat, 24 Feb 2018 00:40:50 +0000 (00:40 +0000)]
[WebAssembly] Add exception handling option and feature
Summary:
Add a llc command line option and WebAssembly architecture feature for
exception handling.
Reviewers: dschuff
Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D43683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326004
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Pavel Labath [Sat, 24 Feb 2018 00:35:21 +0000 (00:35 +0000)]
Implement equal_range for the DWARF v5 accelerator table
Summary:
This patch implements the name lookup functionality of the .debug_names
accelerator table and hooks it up to "llvm-dwarfdump -find". To make the
interface of the two kinds of accelerator tables more consistent, I've
created an abstract "DWARFAcceleratorTable::Entry" class, which provides
a consistent interface to access the common functionality of the table
entries (such as getting the die offset, die tag, etc.). I've also
modified the apple table to vend entries conforming to this interface.
Reviewers: JDevlieghere, aprantl, probinson, dblaikie
Subscribers: vleschuk, clayborg, echristo, llvm-commits
Differential Revision: https://reviews.llvm.org/D43067
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326003
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George Burgess IV [Sat, 24 Feb 2018 00:15:21 +0000 (00:15 +0000)]
[MemorySSA] Remove a redundant dyn_cast.
StartingAccess is a MemoryUseOrDef. No need to check again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326000
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Craig Topper [Sat, 24 Feb 2018 00:15:05 +0000 (00:15 +0000)]
[X86] Remove checks for '(scalar_to_vector (i8 (trunc GR32:)))' from scalar masked move patterns.
This portion can be matched by other patterns. We don't need it to make the larger pattern valid. It's sufficient to have a v1i1 mask input without caring where it came from.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325999
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Stanislav Mekhanoshin [Fri, 23 Feb 2018 23:53:27 +0000 (23:53 +0000)]
[AMDGPU] Fixed madak.ll test on VI, added GFX10. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325995
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Yonghong Song [Fri, 23 Feb 2018 23:49:35 +0000 (23:49 +0000)]
bpf: New disassembler testcases for 32-bit subregister support
This patch test disassembler output for load/store instructions when
-mattr=+alu32 specified for which we want to use "w" register format.
Also, this patch extended the existing insn-unit.s and insn-unit-32.s to
make sure disassemblers for all other instructions are not affected.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325993
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Yonghong Song [Fri, 23 Feb 2018 23:49:33 +0000 (23:49 +0000)]
bpf: New codegen testcases for 32-bit subregister support
This patch adds some unit tests for 32-bit subregister support.
We want to make sure ALU32, subregister load/store and new peephole
optimization are truely enabled once -mattr=+alu32 specified.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325992
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Yonghong Song [Fri, 23 Feb 2018 23:49:32 +0000 (23:49 +0000)]
bpf: New optimization pass for eliminating unnecessary i32 promotions
This pass performs peephole optimizations to cleanup ugly code sequences at
MachineInstruction layer.
Currently, the only optimization in this pass is to eliminate type
promotion
sequences for zero extending 32-bit subregisters to 64-bit registers.
If the compiler could prove the zero extended source come from 32-bit
subregistere then it is safe to erase those promotion sequece, because the
upper half of the underlying 64-bit registers were zeroed implicitly
already.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325991
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Yonghong Song [Fri, 23 Feb 2018 23:49:31 +0000 (23:49 +0000)]
bpf: New decoder namespace for 32-bit subregister load/store
When -mattr=+alu32 passed to the disassembler, use decoder namespace for
32-bit subregister.
This is to disassemble load and store instructions in preferred B format
as described in previous commit:
w = *(u8 *) (r + off) // BPF_LDX | BPF_B
w = *(u16 *)(r + off) // BPF_LDX | BPF_H
w = *(u32 *)(r + off) // BPF_LDX | BPF_W
*(u8 *) (r + off) = w // BPF_STX | BPF_B
*(u16 *)(r + off) = w // BPF_STX | BPF_H
*(u32 *)(r + off) = w // BPF_STX | BPF_W
NOTE: all other instructions should still use the default decoder
namespace.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325990
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Yonghong Song [Fri, 23 Feb 2018 23:49:30 +0000 (23:49 +0000)]
bpf: Enable 32-bit subregister support for -mattr=+alu32
After all those preparation patches, now we could enable 32-bit subregister
support once -mattr=+alu32 specified.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325989
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Yonghong Song [Fri, 23 Feb 2018 23:49:29 +0000 (23:49 +0000)]
bpf: Support 32-bit subregister in various InstrInfo hooks
This patch support 32-bit subregister in three InstrInfo hooks, i.e.
copyPhysReg, loadRegFromStackSlot and storeRegToStackSlot,
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325988
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Yonghong Song [Fri, 23 Feb 2018 23:49:28 +0000 (23:49 +0000)]
bpf: New instruction patterns for 32-bit subregister load and store
The instruction mapping between eBPF/arm64/x86_64 are:
eBPF arm64 x86_64
LD1 BPF_LDX | BPF_B ldrb movzbl
LD2 BPF_LDX | BPF_H ldrh movzwl
LD4 BPF_LDX | BPF_W ldr movl
movzbl/movzwl/movl on x86_64 accept 32-bit sub-register, for example %eax,
the same for ldrb/ldrh on arm64 which accept 32-bit "w" register. And
actually these instructions only accept sub-registers. There is no point
to have LD1/2/4 (unsigned) for 64-bit register, because on these arches,
upper 32-bits are guaranteed to be zeroed by hardware or VM, so load into
the smallest available register class is the best choice for maintaining
type information.
For eBPF we should adopt the same philosophy, to change current
format (A):
r = *(u8 *) (r + off) // BPF_LDX | BPF_B
r = *(u16 *)(r + off) // BPF_LDX | BPF_H
r = *(u32 *)(r + off) // BPF_LDX | BPF_W
*(u8 *) (r + off) = r // BPF_STX | BPF_B
*(u16 *)(r + off) = r // BPF_STX | BPF_H
*(u32 *)(r + off) = r // BPF_STX | BPF_W
into B:
w = *(u8 *) (r + off) // BPF_LDX | BPF_B
w = *(u16 *)(r + off) // BPF_LDX | BPF_H
w = *(u32 *)(r + off) // BPF_LDX | BPF_W
*(u8 *) (r + off) = w // BPF_STX | BPF_B
*(u16 *)(r + off) = w // BPF_STX | BPF_H
*(u32 *)(r + off) = w // BPF_STX | BPF_W
There is no change on encoding nor how should they be interpreted,
everything is as it is, load the specified length, write into low bits of
the register then zeroing all remaining high bits.
The only change is their associated register class and how compiler view
them.
Format A still need to be kept, because eBPF LLVM backend doesn't support
sub-registers at default, but once 32-bit subregister is enabled, it should
use format B.
This patch implemented this together with all those necessary extended load
and truncated store patterns.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325987
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Yonghong Song [Fri, 23 Feb 2018 23:49:26 +0000 (23:49 +0000)]
bpf: Support i32 in getScalarShiftAmountTy method
getScalarShiftAmount method should be implemented for eBPF backend to make
sure shift amount could still get correct type once 32-bit subregisters
support are enabled.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325986
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Yonghong Song [Fri, 23 Feb 2018 23:49:25 +0000 (23:49 +0000)]
bpf: Support condition comparison on i32
We need to support condition comparison on i32. All these comparisons are
supposed to be combined into BPF_J* instructions which only support i64.
For ISD::BR_CC we need to promote it to i64 first, then do custom lowering.
For ISD::SET_CC, just expand to SELECT_CC like what's been done for i64.
For ISD::SELECT_CC, we also want to do custom lower for i32. However, after
32-bit subregister support enabled, it is possible the comparison operands
are i32 while the selected value are i64, or the comparison operands are
i64 while the selected value are i32. We need to define extra instruction
pattern and support them in custom instruction inserter.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325985
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Yonghong Song [Fri, 23 Feb 2018 23:49:24 +0000 (23:49 +0000)]
bpf: Handle i32 for ALU operations without ISA support
There is no eBPF ISA support for BSWAP, ROTR, ROTL, SREM, SDIVREM, MULHU,
ADDC, ADDE etc on i32.
They could be emulated by other basic BPF_ALU operations, we'd set their
lowering action the same as i64.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325984
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Yonghong Song [Fri, 23 Feb 2018 23:49:23 +0000 (23:49 +0000)]
bpf: New calling convention for 32-bit subregisters
This patch add new calling conventions to allow GPR32RegClass as valid
register class for arguments and return types.
New calling convention will only be choosen when -mattr=+alu32 specified.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325983
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Yonghong Song [Fri, 23 Feb 2018 23:49:22 +0000 (23:49 +0000)]
bpf: New target attribute "alu32" for 32-bit subregister support
This new attribute aims to control the enablement of 32-bit subregister
support on eBPF backend.
Name the interface as "alu32" is because we in particular want to enable
the generation of BPF_ALU32 instructions by enable subregister support.
This attribute could be used in the following format with llc:
llc -mtriple=bpf -mattr=[+|-]alu32
It is disabled at default.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325982
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Yonghong Song [Fri, 23 Feb 2018 23:49:21 +0000 (23:49 +0000)]
bpf: Define instruction patterns for extensions and truncations between i32 to i64
For transformations between i32 and i64, if it is explicit signed extension:
- first cast the operand to i64
- then use SLL + SRA to finish the extension.
if it is explicit zero extension:
- first cast the operand to i64
- then use SLL + SRL to finish the extension.
if it is explicit any extension:
- just refer to 64-bit register.
if it is explicit truncation:
- just refer to 32-bit subregister.
NOTE: Some of the zero extension sequences might be unnecessary, they will be
removed by an peephole pass on MachineInstruction layer.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325981
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Yonghong Song [Fri, 23 Feb 2018 23:49:19 +0000 (23:49 +0000)]
bpf: Tighten the immediate predication for 32-bit alu instructions
These 32-bit ALU insn patterns which takes immediate as one operand were
initially added to enable AsmParser support, and the AsmMatcher uses "ins"
and "outs" fields to deduct the operand constraint.
However, the instruction selector doesn't work the same as AsmMatcher. The
selector will use the "pattern" field for which we are not setting the
predication for immediate operands correctly.
Without this patch, i32 would eventually means all i32 operands are valid,
both imm and gpr, while these patterns should allow imm only.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325980
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Yonghong Song [Fri, 23 Feb 2018 23:49:18 +0000 (23:49 +0000)]
bpf: Use markSuperRegs to mark reserved registers
markSuperRegs is the canonical helper function used to mark reserved
registers. It could mark any overlapping sub-registers automatically.
Reviewed-by: Yonghong Song <yhs@fb.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325979
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Scott Linder [Fri, 23 Feb 2018 23:13:18 +0000 (23:13 +0000)]
[DebugInfo] Add remaining files to r325970
Add files which I missed in the original check-in
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325973
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Nemanja Ivanovic [Fri, 23 Feb 2018 23:08:34 +0000 (23:08 +0000)]
[PowerPC] Disable shrink-wrapping when getting PC address through the LR
The instruction sequence used to get the address of the PC into a GPR requires
that we clobber the link register. Doing so without having first saved it in
the prologue leaves the function unable to return. Currently, this sequence is
emitted into the entry block. To ensure the prologue is inserted before this
sequence, disable shrink-wrapping.
This fixes PR33547.
Differential Revision: https://reviews.llvm.org/D43677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325972
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George Burgess IV [Fri, 23 Feb 2018 23:07:18 +0000 (23:07 +0000)]
[MemorySSA] Fix a cache invalidation bug with removed accesses
I suspect there's a deeper issue here, but we probably shouldn't be
using INVALID_MEMORYSSA_ID as liveOnEntry's ID anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325971
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Scott Linder [Fri, 23 Feb 2018 23:01:06 +0000 (23:01 +0000)]
[DebugInfo] Support DWARF v5 source code embedding extension
In DWARF v5 the Line Number Program Header is extensible, allowing values with
new content types. In this extension a content type is added,
DW_LNCT_LLVM_source, which contains the embedded source code of the file.
Add new optional attribute for !DIFile IR metadata called source which contains
source text. Use this to output the source to the DWARF line table of code
objects. Analogously extend METADATA_FILE in Bitcode and .file directive in ASM
to support optional source.
Teach llvm-dwarfdump and llvm-objdump about the new values. Update the output
format of llvm-dwarfdump to make room for the new attribute on file_names
entries, and support embedded sources for the -source option in llvm-objdump.
Differential Revision: https://reviews.llvm.org/D42765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325970
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Sanjay Patel [Fri, 23 Feb 2018 22:38:10 +0000 (22:38 +0000)]
[InstCombine] simplify code for fabs(X) * fabs(X) -> X * X; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325968
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Eric Christopher [Fri, 23 Feb 2018 22:32:05 +0000 (22:32 +0000)]
Sink the verification code around the assert where it's handled and wrap in NDEBUG.
This has the advantage of making release only builds more warning
free and there's no need to make this routine a class function if
it isn't using class members anyhow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325967
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Sanjay Patel [Fri, 23 Feb 2018 22:20:13 +0000 (22:20 +0000)]
[InstSimplify] sqrt(X) * sqrt(X) --> X
This was misplaced in InstCombine. We can loosen the FMF as a follow-up step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325965
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Sriraman Tallam [Fri, 23 Feb 2018 21:32:06 +0000 (21:32 +0000)]
Intrinsics calls should avoid the PLT when "RtLibUseGOT" metadata is present.
Differential Revision: https://reviews.llvm.org/D42216
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325962
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Sanjay Patel [Fri, 23 Feb 2018 21:16:12 +0000 (21:16 +0000)]
[InstCombine] allow fmul-sqrt folds with less than full -ffast-math
Also, add a Builder method for intrinsics to reduce code duplication for clients.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325960
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Eric Christopher [Fri, 23 Feb 2018 21:14:47 +0000 (21:14 +0000)]
Simplify a DEBUG statement to remove a set but not used variable in release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325959
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Craig Topper [Fri, 23 Feb 2018 20:48:44 +0000 (20:48 +0000)]
[X86] Add assembler/disassembler support for blendm with zero masking and broacast.
Fixes PR31617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325957
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Stefan Pintilie [Fri, 23 Feb 2018 20:37:10 +0000 (20:37 +0000)]
[Power9] Add missing instructions to the Power 9 scheduler
This is the first in a series of patches that will define more
instructions using InstRW so that we can move away from ItinRW
and ultimately have a complete Power 9 scheduler.
Differential Revision: https://reviews.llvm.org/D43635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325956
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Krzysztof Parzyszek [Fri, 23 Feb 2018 20:33:26 +0000 (20:33 +0000)]
[Hexagon] Recognize non-immediate constants in HexagonConstPropagation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325954
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Simon Pilgrim [Fri, 23 Feb 2018 20:16:18 +0000 (20:16 +0000)]
Fixed unused variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325950
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Craig Topper [Fri, 23 Feb 2018 20:13:42 +0000 (20:13 +0000)]
[X86] Add DAG combine to remove (and X, 1) from in front of a v1i1 scalar to vector.
These can be created by type legalization promoting the inputs to select to match scalar boolean contents.
We were trying to pattern match them away during isel, but its better to just remove them from the DAG.
I've cleaned up some patterns to not check for this 'and' anymore. But I suspect this has also opened up opportunities for pattern removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325949
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Benjamin Kramer [Fri, 23 Feb 2018 20:13:03 +0000 (20:13 +0000)]
[WebAssembly] Fix macro metaprogram to not duplicate code as much.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325947
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Eric Christopher [Fri, 23 Feb 2018 20:12:24 +0000 (20:12 +0000)]
Because of CVE-2018-6574, some compiler options and linker options are restricted to prevent arbitrary code execution.
https://github.com/golang/go/issues/23672
By this change, building a Go code with LLVM Go bindings causes a compilation error as follows.
go build llvm.org/llvm/bindings/go/llvm: invalid flag in #cgo LDFLAGS: -Wl,-headerpad_max_install_names
llvm-go tool generates cgo LDFLAGS directive from `llvm-config --ldflags` and it contains -Wl,option options. But -Wl,option is banned by default. To avoid this problem, we need to set $CGO_LDFLAGS_ALLOW environment variable to notify a compiler that the flags should be allowed.
$ export CGO_LDFLAGS_ALLOW='-Wl,(-search_paths_first|-headerpad_max_install_names)'
By default for go 1.10 and go 1.9.5 these options should appear in the accepted set of options, however, if you're running into the error it's useful to have this documented.
Patch by Ryuichi Hayashida
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325946
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Simon Pilgrim [Fri, 23 Feb 2018 19:58:44 +0000 (19:58 +0000)]
[X86][SSE] Generalize x > C-1 ? x+-C : 0 --> subus x, C combine for non-uniform constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325944
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Benjamin Kramer [Fri, 23 Feb 2018 19:32:56 +0000 (19:32 +0000)]
Shrink various scheduling tables by using narrower types.
16 bits ought to be enough for everyone. This shrinks clang by ~1MB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325941
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Evandro Menezes [Fri, 23 Feb 2018 19:27:43 +0000 (19:27 +0000)]
[PATCH] [AArch64] Add new target feature to fuse conditional select
This feature enables the fusion of the comparison and the conditional select
instructions together.
Differential revision: https://reviews.llvm.org/D42392
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325939
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Geoff Berry [Fri, 23 Feb 2018 19:11:33 +0000 (19:11 +0000)]
Fix compiler warning introduced in r325931. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325938
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Matt Davis [Fri, 23 Feb 2018 19:03:04 +0000 (19:03 +0000)]
[Test] Fix the test to output to /dev/null instead of redirecting.
The redirection was confusing the windows build machine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325937
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Simon Pilgrim [Fri, 23 Feb 2018 18:57:26 +0000 (18:57 +0000)]
[X86][SSE] Add x > C-1 ? x+-C : 0 --> subus x, C test caaes for non-uniform constants
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325936
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George Burgess IV [Fri, 23 Feb 2018 18:56:42 +0000 (18:56 +0000)]
[MemorySSA] Use fewer magic numbers. NFC
INVALID_MEMORYACCESS_ID == 0.
This patch also makes this initialization consistent with the rest of
the "invalid" ones in this file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325935
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George Burgess IV [Fri, 23 Feb 2018 18:50:39 +0000 (18:50 +0000)]
[MemorySSA] Reduce padding in MemoryDefs. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325934
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Craig Topper [Fri, 23 Feb 2018 18:43:36 +0000 (18:43 +0000)]
[X86] Custom split v32i16/v64i8 bitcasts when AVX512F is available, but BWI is not.
The test changes you can see are related to the changes in ReplaceNodeResults. Though shuffle-vs-trunc-512.ll does have a test that exercises the code in LowerBITCAST. Looks like the test output didn't change because DAG combining is able to clean up the resulting type legalization. Adding the custom hook just makes type legalization work less hard.
Differential Revision: https://reviews.llvm.org/D43447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325933
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Geoff Berry [Fri, 23 Feb 2018 18:25:08 +0000 (18:25 +0000)]
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers. This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.
Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).
Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.
Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.
Clear the IsRenamable bit when changing an operand's register value.
Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.
Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.
Reviewers: qcolombet, MatzeB
Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits
Differential Revision: https://reviews.llvm.org/D43042
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325931
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Matt Davis [Fri, 23 Feb 2018 17:38:27 +0000 (17:38 +0000)]
[Debug] Add dbg.value intrinsics for PHIs created during LCSSA.
Summary:
This patch is an enhancement to propagate dbg.value information when Phis are created on behalf of LCSSA.
I noticed a case where a value carried across a loop was reported as <optimized out>.
Specifically this case:
```
int bar(int x, int y) {
return x + y;
}
int foo(int size) {
int val = 0;
for (int i = 0; i < size; ++i) {
val = bar(val, i); // Both val and i are correct
}
return val; // <optimized out>
}
```
In the above case, after all of the interesting computation completes our value
is reported as "optimized out." This change will add a dbg.value to correct this.
This patch also moves the dbg.value insertion routine from LoopRotation.cpp
into Local.cpp, so that we can share it in both places (LoopRotation and LCSSA).
Reviewers: mzolotukhin, aprantl, vsk, davide
Reviewed By: aprantl, vsk
Subscribers: dberlin, llvm-commits
Differential Revision: https://reviews.llvm.org/D42551
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325926
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John Brawn [Fri, 23 Feb 2018 17:17:31 +0000 (17:17 +0000)]
[BPI] Detect branches in loops that make themselves not taken
If we have a loop like this:
int n = 0;
while (...) {
if (++n >= MAX) {
n = 0;
}
}
then the body of the 'if' statement will only be executed once every MAX
iterations. Detect this by looking for branches in loops where taking the branch
makes the branch condition evaluate to 'not taken' in the next iteration of the
loop, and reduce the probability of such branches.
This slightly improves EEMBC benchmarks on cortex-m4/cortex-m33 due to making
better choices in if-conversion, but has no effect on any other cpu/benchmark
that I could detect.
Differential Revision: https://reviews.llvm.org/D35804
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325925
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Sanjay Patel [Fri, 23 Feb 2018 17:14:28 +0000 (17:14 +0000)]
[InstCombine] refactor fmul with negated op folds; NFCI
The existing code was inefficiently looking for 'nsz' variants.
That's unnecessary because we canonicalize those to the expected
form with -0.0.
We may also want to adjust or remove the fold that sinks negation.
We don't do that for fdiv (or integer ops?). That should be uniform?
It may also lead to missed optimization as in PR21914:
https://bugs.llvm.org/show_bug.cgi?id=21914
...or we just have to fix other passes to avoid that problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325924
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