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Craig Topper [Mon, 13 Nov 2017 08:07:33 +0000 (08:07 +0000)]
[X86] Use sse_load_f32/f64 to improve load folding of scalar vfscalefss/sd, vrcp14ss/sd, rsqrt14ss/sd instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318022
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Craig Topper [Mon, 13 Nov 2017 08:07:31 +0000 (08:07 +0000)]
[X86] Regenerate test. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318021
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Matt Arsenault [Mon, 13 Nov 2017 07:09:20 +0000 (07:09 +0000)]
MI: Print ranges on MMO
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318020
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Craig Topper [Mon, 13 Nov 2017 06:46:48 +0000 (06:46 +0000)]
[X86] Use sse_load_f32/f64 to improve load folding for scalar VFPCLASS intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318019
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Craig Topper [Mon, 13 Nov 2017 06:46:46 +0000 (06:46 +0000)]
[X86] Add tests for missed opportunities to fold a 128-bit vector load into vfpclassss and vpfpclasssd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318018
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Matt Arsenault [Mon, 13 Nov 2017 05:33:35 +0000 (05:33 +0000)]
AMDGPU: Preserve nuw in shl add ptr combine
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318017
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Craig Topper [Mon, 13 Nov 2017 05:25:24 +0000 (05:25 +0000)]
[X86] Fix SQRTSS/SQRTSD/RCPSS/RCPSD intrinsics to use sse_load_f32/sse_load_f64 to increase load folding opportunities.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318016
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Craig Topper [Mon, 13 Nov 2017 05:25:23 +0000 (05:25 +0000)]
[X86] Add tests for full vector loads to fold-load-unops.ll.
We should be able to fold a full vector load into a scalar intrinsic. Since it's legal to narrow a load.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318015
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Craig Topper [Mon, 13 Nov 2017 05:25:21 +0000 (05:25 +0000)]
[X86] Regenerate fold-load-unops.ll and add and avx512f command line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318014
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Matt Arsenault [Mon, 13 Nov 2017 05:11:54 +0000 (05:11 +0000)]
AMDGPU: Fix multi-use shl/add combine
This was using a custom function that didn't handle the
addressing modes properly for private. Use
isLegalAddressingMode to avoid duplicating this.
Additionally, skip the combine if there is only one use
since the standard combine will handle it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318013
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Craig Topper [Mon, 13 Nov 2017 02:19:13 +0000 (02:19 +0000)]
[X86] Attempt to fix signed and unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318010
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Craig Topper [Mon, 13 Nov 2017 02:03:01 +0000 (02:03 +0000)]
[X86] Use sse_load_f32/f64 in patterns for the memory forms of VRNDSCALESS/SD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318009
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Craig Topper [Mon, 13 Nov 2017 02:03:00 +0000 (02:03 +0000)]
[X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round intrinsics.
The VRNDSCALE instructions implement a superset of the (V)ROUND instructions. They are equivalent if the upper 4-bits of the immediate are 0.
This patch lowers the legacy intrinsics to the VRNDSCALE ISD node and masks the upper bits of the immediate to 0. This allows us to take advantage of the larger register encoding space.
We should maybe consider converting VRNDSCALE back to VROUND in the EVEX to VEX pass if the extended registers are not being used.
I notice some load folding opportunities being missed for the VRNDSCALESS/SD instructions that I'll try to fix in future patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318008
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Craig Topper [Mon, 13 Nov 2017 02:02:58 +0000 (02:02 +0000)]
[X86] Split VRNDSCALE/VREDUCE/VGETMANT/VRANGE ISD nodes into versions with and without the rounding operand. NFCI
I want to reuse the VRNDSCALE node for the legacy SSE rounding intrinsics so that those intrinsics can use EVEX instructions. All of these nodes share tablegen multiclasses so I split them all so that they all remain similar in their implementations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318007
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Matt Arsenault [Mon, 13 Nov 2017 01:47:52 +0000 (01:47 +0000)]
Fix some misc. -enable-var-scope violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318006
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Matt Arsenault [Mon, 13 Nov 2017 00:22:09 +0000 (00:22 +0000)]
AMDGPU: Select d16 loads into low component of register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318005
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Matt Arsenault [Sun, 12 Nov 2017 23:53:44 +0000 (23:53 +0000)]
AMDGPU: Fix -enable-var-scope violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318004
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Matt Arsenault [Sun, 12 Nov 2017 23:40:12 +0000 (23:40 +0000)]
AMDGPU: Fix missing gfx9 atomic inc/dec tests
The global instructions weren't tested. Plus there
were also some -enable-var-scope violations and
broken check prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318003
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Craig Topper [Sun, 12 Nov 2017 18:51:09 +0000 (18:51 +0000)]
[X86] Add an X86ISD::RANGES opcode to use for the scalar intrinsics.
This fixes a bug where we selected packed instructions for scalar intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317999
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Craig Topper [Sun, 12 Nov 2017 18:51:08 +0000 (18:51 +0000)]
[X86] Add test cases and command lines demonstrating how we accidentally select vrangeps/vrangepd from vrangess/vrangesd instrinsics when the rounding mode is CUR_DIRECTION
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317998
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Craig Topper [Sun, 12 Nov 2017 18:51:06 +0000 (18:51 +0000)]
[X86] Remove some no longer needed intrinsic lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317997
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Mandeep Singh Grang [Sun, 12 Nov 2017 03:47:50 +0000 (03:47 +0000)]
[llvm] Remove redundant return [NFC]
Reviewers: davidxl, olista01, Eugene.Zelenko
Reviewed By: Eugene.Zelenko
Subscribers: sdardis, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D39917
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317995
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Craig Topper [Sun, 12 Nov 2017 02:28:21 +0000 (02:28 +0000)]
[InstCombine] Teach visitICmpInst to not break integer absolute value idioms
Summary:
This patch adds an early out to visitICmpInst if we are looking at a compare as part of an integer absolute value idiom. Similar is already done for min/max.
In the particular case I observed in a benchmark we had an absolute value of a load from an indexed global. We simplified the compare using foldCmpLoadFromIndexedGlobal into a magic bit vector, a shift, and an and. But the load result was still used for the select and the negate part of the absolute valute idiom. So we overcomplicated the code and lost the ability to recognize it as an absolute value.
I've chosen a simpler case for the test here.
Reviewers: spatel, davide, majnemer
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39766
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317994
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Craig Topper [Sat, 11 Nov 2017 21:44:51 +0000 (21:44 +0000)]
[X86] Use vrndscaleps/pd for 128/256 ffloor/ftrunc/fceil/fnearbyint/frint when avx512vl is enabled.
This matches what we do for scalar and 512-bit types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317991
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Craig Topper [Sat, 11 Nov 2017 21:44:50 +0000 (21:44 +0000)]
[X86] Remove avx512-round.ll. The 512-bit rounding tests are now in vec_floor.ll with 128/256 sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317990
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Craig Topper [Sat, 11 Nov 2017 21:44:49 +0000 (21:44 +0000)]
[X86] Add avx512vl command line to vec_floor.ll. Add 512-bit test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317989
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Craig Topper [Sat, 11 Nov 2017 21:44:48 +0000 (21:44 +0000)]
[X86] Add avx512f command line to rounding-ops.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317988
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Craig Topper [Sat, 11 Nov 2017 21:44:47 +0000 (21:44 +0000)]
[X86] Regenerate rounding-ops.ll with update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317987
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Simon Pilgrim [Sat, 11 Nov 2017 18:16:55 +0000 (18:16 +0000)]
[X86] Attempt to match multiple binary reduction ops at once. NFCI
matchBinOpReduction currently matches against a single opcode, but we already have a case where we repeat calls to try to match against AND/OR and I'll be shortly adding another case for SMAX/SMIN/UMAX/UMIN (D39729).
This NFCI patch alters matchBinOpReduction to try and pattern match against any of the provided list of candidate bin ops at once to save time.
Differential Revision: https://reviews.llvm.org/D39726
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317985
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Craig Topper [Sat, 11 Nov 2017 08:24:15 +0000 (08:24 +0000)]
[X86] Add scalar register class versions of VRNDSCALE instructions and rename the existing versions to _Int.
This is consistent with out normal implementation of scalar instructions.
While there disable load folding for the patterns with IMPLICIT_DEF unless optimizing for size which is also our standard practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317977
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Craig Topper [Sat, 11 Nov 2017 08:24:13 +0000 (08:24 +0000)]
[X86] Regenerate avx512-round.ll test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317976
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Craig Topper [Sat, 11 Nov 2017 08:24:12 +0000 (08:24 +0000)]
[X86] Inline some SDNode operand multiclass operands that don't vary. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317975
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Craig Topper [Sat, 11 Nov 2017 06:57:44 +0000 (06:57 +0000)]
[X86] Set the execution domain for VFPCLASS to SSEPackedSingle/Double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317974
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Craig Topper [Sat, 11 Nov 2017 06:19:12 +0000 (06:19 +0000)]
[X86] Set the execution domain for vptest instruction to the integer domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317973
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Daniel Sanders [Sat, 11 Nov 2017 03:23:44 +0000 (03:23 +0000)]
[globalisel][tablegen] Import signextload and zeroextload.
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to
correct situations where SelectionDAG and GlobalISel disagree on
representation. For example, it would rewrite:
(sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16>
to:
(sext:i32 (load:i16 $ptr)<<unindexedload>>)
I'd have preferred to replace the fragments and have the expansion happen
naturally as part of PatFrag expansion but the type inferencing system can't
cope with loads of types narrower than those mentioned in register classes.
This is because the SDTCisInt's on the sext constrain both the result and
operand to the 'legal' integer types (where legal is defined as 'a register
class can contain the type') which immediately rules the narrower types out.
Several targets (those with only one legal integer type) would then go on to
crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types
for the result of the extend.
Also, improve isObviouslySafeToFold() slightly to automatically return true for
neighbouring instructions. There can't be any re-ordering problems if
re-ordering isn't happenning. We'll need to improve it further to handle
sign/zero-extending loads when the extend and load aren't immediate neighbours
though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317971
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Craig Topper [Sat, 11 Nov 2017 02:26:05 +0000 (02:26 +0000)]
[X86] Correct the execution domain on ROUND/VROUND instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317968
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Craig Topper [Sat, 11 Nov 2017 02:26:02 +0000 (02:26 +0000)]
[X86] Remove the default for one of the arguments to some tablegen multiclasses. NFC
No one ever uses this default and probably shouldn't since it sets the execution domain to generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317967
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NAKAMURA Takumi [Sat, 11 Nov 2017 02:05:47 +0000 (02:05 +0000)]
llvm/Support/TargetParser.h: Fix -fmodules build in rL317900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317966
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Tony Tye [Sat, 11 Nov 2017 00:50:32 +0000 (00:50 +0000)]
[AMDGPU] Correct targets that support XNACK
Differential Revision: https://reviews.llvm.org/D39887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317955
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Craig Topper [Fri, 10 Nov 2017 23:36:56 +0000 (23:36 +0000)]
[SelectionDAG] Make getUniformBase in SelectionDAGBuilder fail if any of the middle GEP indices are non-constant.
This is a fix for a bug in r317947. We were supposed to check that all the indices are are constant 0, but instead we're only make sure that indices that are constant are 0. Non-constant indices are being ignored.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317950
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Zachary Turner [Fri, 10 Nov 2017 23:13:14 +0000 (23:13 +0000)]
Update test_debuginfo.pl script to point to new tree location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317949
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Craig Topper [Fri, 10 Nov 2017 22:50:50 +0000 (22:50 +0000)]
[SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter handling to accept GEPs with more than 2 operands if the middle operands are all 0s
Currently we can only get a uniform base from a simple GEP with 2 operands. This causes us to miss address folding opportunities for simple global array accesses as the test case shows.
This patch adds support for larger GEPs if the other indices are 0 since those don't require any additional computations to be inserted.
We may also want to handle constant splats of zero here, but I'm leaving that for future work when I have a real world example.
Differential Revision: https://reviews.llvm.org/D39911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317947
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Evgeniy Stepanov [Fri, 10 Nov 2017 22:27:48 +0000 (22:27 +0000)]
[asan] Use dynamic shadow on 32-bit Android.
Summary:
The following kernel change has moved ET_DYN base to 0x4000000 on arm32:
https://marc.info/?l=linux-kernel&m=
149825162606848&w=2
Switch to dynamic shadow base to avoid such conflicts in the future.
Reserve shadow memory in an ifunc resolver, but don't use it in the instrumentation
until PR35221 is fixed. This will eventually let use save one load per function.
Reviewers: kcc
Subscribers: aemerson, srhines, kubamracek, kristof.beyls, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D39393
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317943
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Martin Storsjo [Fri, 10 Nov 2017 22:27:41 +0000 (22:27 +0000)]
[llvm-cvtres] Add support for ARM64
Also change some default cases into llvm_unreachable in
WindowsResourceCOFFWriter, to make it easier to find if they
are triggerd from within e.g. lld, which supported ARM64 earlier
than llvm-cvtres did.
Differential Revision: https://reviews.llvm.org/D39892
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317942
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Mitch Phillips [Fri, 10 Nov 2017 21:00:22 +0000 (21:00 +0000)]
[cfi-verify] Made FileAnalysis operate on a GraphResult rather than build one and validate it.
Refactors the behaviour of building graphs out of FileAnalysis, allowing for analysis of the GraphResult by the callee without having to rebuild the graph. Means when we want to analyse the constructed graph (planned for later revisions), we don't do repeated work.
Also makes CFI verification in FileAnalysis now return an enum that allows us to differentiate why something failed, not just that it did/didn't fail.
Reviewers: vlad.tsyrklevich
Subscribers: kcc, pcc, llvm-commits
Differential Revision: https://reviews.llvm.org/D39764
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317927
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Amaury Sechet [Fri, 10 Nov 2017 20:59:53 +0000 (20:59 +0000)]
[DAGcombine] Do not replace truncate node by itself when doing constant folding, this trigger needless extra rounds of combine for nothing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317926
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Zachary Turner [Fri, 10 Nov 2017 20:57:57 +0000 (20:57 +0000)]
[debuginfo-tests] Make debuginfo-tests work in a standard configuration.
Previously, debuginfo-tests was expected to be checked out into
clang/test and then the tests would automatically run as part of
check-clang. This is not a standard workflow for handling
external projects, and it brings with it some serious drawbacks
such as the inability to depend on things other than clang, which
we will need going forward.
The goal of this patch is to migrate towards a more standard
workflow. To ease the transition for build bot maintainers,
this patch tries not to break the existing workflow, but instead
simply deprecate it to give maintainers a chance to update
the build infrastructure.
Differential Revision: https://reviews.llvm.org/D39605
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317925
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Tony Tye [Fri, 10 Nov 2017 20:51:43 +0000 (20:51 +0000)]
[AMDGPU] AMDGPUUsage.rst minor corrections
Differential Revision: https://reviews.llvm.org/D39887
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317924
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Davide Italiano [Fri, 10 Nov 2017 20:46:21 +0000 (20:46 +0000)]
[SimplifyCFG] Use auto * when the type is obvious. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317923
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Krzysztof Parzyszek [Fri, 10 Nov 2017 20:09:46 +0000 (20:09 +0000)]
Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFC
The Windows builder did not reconstruct the HexagonGenDAGISel.inc file
after the TableGen binary has changed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317921
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Konstantin Zhuravlyov [Fri, 10 Nov 2017 20:01:58 +0000 (20:01 +0000)]
AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td
Differential Revision: https://reviews.llvm.org/D39880
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317920
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Daniel Neilson [Fri, 10 Nov 2017 19:38:12 +0000 (19:38 +0000)]
Expand IRBuilder interface for atomic memcpy to require pointer alignments. (NFC)
Summary:
The specification of the @llvm.memcpy.element.unordered.atomic intrinsic requires
that the pointer arguments have alignments of at least the element size. The existing
IRBuilder interface to create a call to this intrinsic does not allow for providing
the alignment of these pointer args. Having an interface that makes it easy to
construct invalid intrinsic calls doesn't seem sensible, so this patch simply
adds the requirement that one provide the argument alignments when using IRBuilder
to create atomic memcpy calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317918
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Krzysztof Parzyszek [Fri, 10 Nov 2017 19:27:18 +0000 (19:27 +0000)]
Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC"
This reverts r317904: broke Windows build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317916
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Craig Topper [Fri, 10 Nov 2017 19:26:04 +0000 (19:26 +0000)]
[X86] Merge the template method selectAddrOfGatherScatterNode into selectVectorAddr. NFCI
Just need to initialize a couple variables differently based on the node type. No need for a whole separate template method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317915
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Adrian Prantl [Fri, 10 Nov 2017 19:22:02 +0000 (19:22 +0000)]
Add back target triple to test which I accidentally removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317912
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Sanjoy Das [Fri, 10 Nov 2017 19:13:35 +0000 (19:13 +0000)]
[CVP] Remove some {s|u}add.with.overflow checks.
Summary:
This adds logic to CVP to remove some overflow checks. It uses LVI to remove
operations with at least one constant. Specifically, this can remove many
overflow intrinsics immediately following an overflow check in the source code,
such as:
if (x < INT_MAX)
... x + 1 ...
Patch by Joel Galenson!
Reviewers: sanjoy, regehr
Reviewed By: sanjoy
Subscribers: fhahn, pirama, srhines, llvm-commits
Differential Revision: https://reviews.llvm.org/D39483
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317911
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Mandeep Singh Grang [Fri, 10 Nov 2017 19:09:28 +0000 (19:09 +0000)]
[RISCV] Silence an unused variable warning in release builds [NFC]
Summary:
Also minor cleanups:
1. Avoided multiple calls to Fixup.getKind()
2. Avoided multiple calls to getFixupKindInfo()
3. Removed a redundant return.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: rbar, johnrusso, llvm-commits
Differential Revision: https://reviews.llvm.org/D39881
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317908
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Craig Topper [Fri, 10 Nov 2017 18:48:18 +0000 (18:48 +0000)]
[X86] Add test case to demonstrate failure to fold the address computation of a simple gather from a global array. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317905
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Krzysztof Parzyszek [Fri, 10 Nov 2017 18:39:45 +0000 (18:39 +0000)]
[Hexagon] Create HexagonISelDAGToDAG.h, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317904
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Krzysztof Parzyszek [Fri, 10 Nov 2017 18:36:04 +0000 (18:36 +0000)]
Allow separation of declarations and definitions in <Target>ISelDAGToDAG.inc
This patch adds the ability to include the member function declarations
in the instruction selector class separately from the member bodies.
Defining GET_DAGISEL_DECL macro to any value will only include the member
declarations. To include bodies, define GET_DAGISEL_BODY macro to be the
selector class name. Example:
class FooDAGToDAGISel : public SelectionDAGISel {
// Pull in declarations only.
#define GET_DAGISEL_DECL
#include "FooISelDAGToDAG.inc"
};
// Include the function bodies (with names qualified with the provided
// class name).
#define GET_DAGISEL_BODY FooDAGToDAGISel
#include "FooISelDAGToDAG.inc"
When neither of the two macros are defined, the function bodies are emitted
inline (in the same way as before this patch).
Differential Revision: https://reviews.llvm.org/D39596
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317903
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Lang Hames [Fri, 10 Nov 2017 17:41:28 +0000 (17:41 +0000)]
[ADT] Rewrite mapped_iterator in terms of iterator_adaptor_base.
Summary:
This eliminates the boilerplate implementation of the iterator interface in
mapped_iterator.
This patch also adds unit tests that verify that the mapped function is applied
by operator* and operator->, and that references returned by the map function
are returned via operator*.
Reviewers: dblaikie, chandlerc
Subscribers: llvm-commits, mgorny
Differential Revision: https://reviews.llvm.org/D39855
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317902
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Craig Topper [Fri, 10 Nov 2017 17:10:57 +0000 (17:10 +0000)]
[X86] Add a def file to CPU vendor, type, and subtype encodings used by Host.cpp
Summary:
I want to leverage this to clean up some of the code in clang. This will allow us to simplify D39521 which was trying to do some of the same.
If we accurately keep the code in Host.cpp synced with new CPUs added to compile-rt/libgcc we should be able to use this file as a proxy for what's implemented in the libraries.
The entries for the CPUs recognized by the libraries use separate macros that define additional parameters like the name for __builtin_cpu_is and an alias string for the couple cases where __builtin_cpu_is accepts two different names.
All of the macros contain an ARCHNAME that is usually the same as the __builtin_cpu_is string, but sometimes isn't. This represents the name recognized by X86.td and -march.
I'm following the precedent set by ARM and AArch64 and adding this information to lib/Support/TargetParser.cpp
Reviewers: erichkeane, echristo, asbirlea
Reviewed By: echristo
Subscribers: llvm-commits, aemerson, kristof.beyls
Differential Revision: https://reviews.llvm.org/D39782
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317900
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Bob Haarman [Fri, 10 Nov 2017 17:08:21 +0000 (17:08 +0000)]
LTO: don't fatal when value for cache key already exists
Summary:
LTO/Caching.cpp uses file rename to atomically set the value for a
cache key. On Windows, this fails when the destination file already
exists. Previously, LLVM would report_fatal_error in such
cases. However, because the old and the new value for the cache key
are supposed to be equivalent, it actually doesn't matter which one we
keep. This change makes it so that failing the rename when an openable
file with the desired name already exists causes us to report success
instead of fataling.
Reviewers: pcc, hans
Subscribers: mehdi_amini, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39874
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317899
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Adrian Prantl [Fri, 10 Nov 2017 16:36:04 +0000 (16:36 +0000)]
Move test into X86 subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317896
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Jatin Bhateja [Fri, 10 Nov 2017 16:26:04 +0000 (16:26 +0000)]
[WebAssembly] Fix stack offsets of return values from call lowering.
Summary: Fixes PR35220
Reviewers: vadimcn, alexcrichton
Reviewed By: alexcrichton
Subscribers: pepyakin, alexcrichton, jfb, dschuff, sbc100, jgravelle-google, llvm-commits, aheejin
Differential Revision: https://reviews.llvm.org/D39866
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317895
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Florian Hahn [Fri, 10 Nov 2017 16:25:16 +0000 (16:25 +0000)]
[AArch64][SVE] Asm: More concise test format
Change the test format for SVE assembler/disassembler tests to be less verbose and have both tests in the same file.
The tests check the following:
* All instructions are assembled correctly into the right encoding.
* All instructions are disassembled correctly (into the preferred assembly format)
* Without -mattr=+sve the instructions are not assembled.
* Without -mattr=+sve the instructions are not disassembled.
This patch also adds several negative tests for SVE add/sub.
Patch by Sander De Smalen.
Reviewed by: rengolin, fhahn
Differential Revision: https://reviews.llvm.org/D39792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317894
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Simon Pilgrim [Fri, 10 Nov 2017 15:49:41 +0000 (15:49 +0000)]
[X86] Add scheduling tests for DAA/DAS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317892
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Igor Laevsky [Fri, 10 Nov 2017 15:08:14 +0000 (15:08 +0000)]
[llvm-opt-fuzzer] Add missed library dependence. Fir for rL317883
Differential Revision: https://reviews.llvm.org/D39555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317889
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Simon Pilgrim [Fri, 10 Nov 2017 13:43:04 +0000 (13:43 +0000)]
[X86] Test non-i64 shld/shll tests on x86_64 targets as well as i686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317888
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Igor Laevsky [Fri, 10 Nov 2017 13:19:14 +0000 (13:19 +0000)]
[llvm-opt-fuzzer] Fix unused variable warning after rL317883
Differential Revision: https://reviews.llvm.org/D39555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317887
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Simon Pilgrim [Fri, 10 Nov 2017 12:32:34 +0000 (12:32 +0000)]
[X86] Add scheduling tests
- CBW etc sign extensions
- CLC/CLD/CMC flag modifiers
- CPUID
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317885
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Alexander Timofeev [Fri, 10 Nov 2017 12:21:10 +0000 (12:21 +0000)]
[AMDGPU] Prevent Machine Copy Propagation from replacing live copy with the dead one
Differential revision: https://reviews.llvm.org/D38754
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317884
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Igor Laevsky [Fri, 10 Nov 2017 12:19:08 +0000 (12:19 +0000)]
[llvm-opt-fuzzer] Introduce llvm-opt-fuzzer for fuzzing optimization passes
This change adds generic fuzzing tools capable of running libFuzzer tests on
any optimization pass or combination of them.
Differential Revision: https://reviews.llvm.org/D39555
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317883
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Simon Pilgrim [Fri, 10 Nov 2017 12:04:39 +0000 (12:04 +0000)]
[X86] Added TODO list for missing generic x86 instruction scheduling tests.
Not sure if we want to add the more exotic system instructions (IRET etc.) as well?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317882
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Karl-Johan Karlsson [Fri, 10 Nov 2017 09:48:40 +0000 (09:48 +0000)]
[RegisterCoalescer] Move debug value after rematerialize trivial def
Summary:
The associated debug value is updated when the virtual source register
of a copy is completely eliminated and replaced with a rematerialize
value in the defed register of the copy. As the debug value now is
associated with another register it also need to be moved, otherwise
the debug value isn't valid.
Reviewers: aprantl
Reviewed By: aprantl
Subscribers: MatzeB, llvm-commits, qcolombet
Differential Revision: https://reviews.llvm.org/D38024
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317880
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Jonas Paulsson [Fri, 10 Nov 2017 08:46:26 +0000 (08:46 +0000)]
[RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints.
* The method getRegAllocationHints() is now of bool type instead of void. If
true is returned, regalloc (AllocationOrder) will *only* try to allocate the
hints, as opposed to merely trying them before non-hinted registers.
* TargetRegisterInfo::getRegAllocationHints() is implemented for SystemZ with
an increase in number of LOCRs.
In this case, it is desired to force the hints even though there is a slight
increase in spilling, because if a non-hinted register would be allocated,
the LOCRMux pseudo would have to be expanded with a jump sequence. The LOCR
(Load On Condition) SystemZ instruction must have both operands in either the
low or high part of the 64 bit register.
Reviewers: Quentin Colombet and Ulrich Weigand
https://reviews.llvm.org/D36795
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317879
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Craig Topper [Fri, 10 Nov 2017 08:22:37 +0000 (08:22 +0000)]
[X86] Add support for combining FMADDSUB(A, B, FNEG(C))->FMSUBADD(A, B, C)
Support the opposite direction as well. Also add a TODO for not being able to combine FMSUB/FNMADD/FNMSUB with FNEG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317878
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Craig Topper [Fri, 10 Nov 2017 06:07:37 +0000 (06:07 +0000)]
[X86] Remove GCCBuiltin from intrinsics that are no longer used by clang.
I've also added TODOs for intrinsic removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317876
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Yaxun Liu [Fri, 10 Nov 2017 02:03:28 +0000 (02:03 +0000)]
[AMDGPU] Fix pointer info for lowering load/store for r600 for amdgiz environment
r600 uses dummy pointer info for lowering load/store. Since dummy pointer info
assumes address space 0, this causes isel failure when temporary load/store SDNodes
are generated for amdgiz environment.
Since the offest is not constant, FixedStack pseudo source value cannot be used
to create the pointer info. This patch creates pointer info using llvm undef value.
At least this provides correct address space so that isel can be done correctly.
Differential Revision: https://reviews.llvm.org/D39698
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317862
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Yaxun Liu [Fri, 10 Nov 2017 01:53:24 +0000 (01:53 +0000)]
[AMDGPU] Fix pointer info for pseudo source for r600
The pointer info for pseudo source for r600 is not correct when
alloca addr space is not 0, which causes invalid SDNode for r600---amdgiz.
This patch fixes that.
Differential Revision: https://reviews.llvm.org/D39670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317861
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Tony Tye [Fri, 10 Nov 2017 01:00:54 +0000 (01:00 +0000)]
[AMDGPU] Update code object description
- Use ELF header flags to identify processor.
- Remove isa note record.
- Add target feature section.
- Make metadata for NumVGPRs, NumSGPRs and MaxFlatWorkGroupSize required.
- Add FixedWorkGroupSize to CodeProps metadata.
- Add ReqdWorkGroupSize* to kernel descriptor and move MaxFlatWorkGroupSize to be adjacent.
- Move IsXNACKEnabled in the kernel descriptor to be at the end of the unused flags.
- Remove IsDynamicCallStack from the metadata and kernel descriptor.
- Remove legacy debugger metadata.
- Remove old XNACK enabled processor names.
Differential Revision: https://reviews.llvm.org/D39828
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317855
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Volodymyr Sapsai [Fri, 10 Nov 2017 00:47:47 +0000 (00:47 +0000)]
[ThinLTO] Fix missing call graph edges for calls with bitcasts.
This change doesn't fix the root cause of the miscompile PR34966 as the root
cause is in the linker ld64. This change makes call graph more complete
allowing to have better module imports/exports.
rdar://problem/
35344706
Reviewers: tejohnson
Reviewed By: tejohnson
Subscribers: mehdi_amini, inglorion, eraman, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D39356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317853
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Bob Haarman [Fri, 10 Nov 2017 00:17:31 +0000 (00:17 +0000)]
[support] allocate exact size required for mapping in Support/Windws/Path.inc
Summary:
zturner suggested that mapped_file_region::init() on Windows seems to
create mappings that are larger than they need to be: Offset+Size
instead of Size. Indeed, that appears to be the case. I confirmed that
tests pass with mappings of just Size bytes, and fail with Size-1
bytes, suggesting that Size is indeed the correct value.
Reviewers: amccarth, zturner
Reviewed By: zturner
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D39876
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317850
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Easwaran Raman [Thu, 9 Nov 2017 23:17:52 +0000 (23:17 +0000)]
[SimplifyCFG] Fix a test case.
This was first committed in r317845, but had the order of branch weights
wrong and didn't properly check the output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317848
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Easwaran Raman [Thu, 9 Nov 2017 22:52:20 +0000 (22:52 +0000)]
Add a wrapper function to set branch weights metadata.
Summary:
This wrapper checks if there is at least one non-zero weight before
setting the metadata.
Reviewers: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39872
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317845
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Sanjay Patel [Thu, 9 Nov 2017 22:41:39 +0000 (22:41 +0000)]
[Reassociate] regenerate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317841
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Kostya Serebryany [Thu, 9 Nov 2017 21:35:28 +0000 (21:35 +0000)]
[libFuzzer] update links in the docs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317837
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Kostya Serebryany [Thu, 9 Nov 2017 21:32:02 +0000 (21:32 +0000)]
[libFuzzer] update the docs, document how to resume the merge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317836
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Zachary Turner [Thu, 9 Nov 2017 20:38:16 +0000 (20:38 +0000)]
Add a Cross-compilation toolchain file for MSVC.
With this patch, you can now cross-compile for Windows
on non-Windows hosts.
Differential Revision: https://reviews.llvm.org/D39814
This allows cross-compiling for windows on other platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317830
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Paul Robinson [Thu, 9 Nov 2017 20:01:31 +0000 (20:01 +0000)]
Fix out-of-order stepping behavior in programs with hoisted constants.
When the Constant Hoisting pass moves expensive constants into a
common block, it would assign a debug location equal to the last use
of that constant. While this is certainly intuitive, it places the
constant in an out-of-order location, according to the debug location
information. This produces out-of-order stepping when debugging
programs affected by this pass.
This patch creates in-order stepping behavior by merging the debug
locations for hoisted constants, and the new insertion point.
Patch by Matthew Voss!
Differential Revision: https://reviews.llvm.org/D38088
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317827
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Alex Bradbury [Thu, 9 Nov 2017 20:01:25 +0000 (20:01 +0000)]
[utils] Fix RISC-V support in update_llc_test_checks.py
scrub_asm_riscv now takes two arguments rather than one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317826
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Adrian Prantl [Thu, 9 Nov 2017 19:50:20 +0000 (19:50 +0000)]
Preserve debug info when DAG-combinging (zext (truncate x)) -> (and x, mask).
rdar://problem/
27139077
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317825
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Zachary Turner [Thu, 9 Nov 2017 19:31:52 +0000 (19:31 +0000)]
[Support] Make llvm::Error and Expected faster.
Whenever LLVM_ENABLE_ABI_BREAKING_CHECKS is enabled, which
is usually the case for example when asserts are enabled,
Error's destructor does some additional checking to make sure
that that it does not represent an error condition and that it
was checked.
However, this is -- by definition -- not the likely codepath.
Some profiling shows that at least with some compilers, simply
calling assertIsChecked -- in a release build with full
optimizations -- can account for up to 15% of the entire
runtime of the program, even though this function should almost
literally be a no-op.
The problem is that the assertIsChecked function can be considered
too big to inline depending on the compiler's inliner. Since it's
unlikely to ever need to failure path though, we can move it out
of line and force it to not be inlined, so that the fast path
can be inlined.
In my test (using lld to link clang with CMAKE_BUILD_TYPE=Release
and LLVM_ENABLE_ASSERTIONS=ON), this reduces link time from 27
seconds to 23.5 seconds, which is a solid 15% gain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317824
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Alexey Bataev [Thu, 9 Nov 2017 19:07:16 +0000 (19:07 +0000)]
[SLP] Fix PR23510: Try to find best possible vectorizable stores.
Summary:
The analysis of the store sequence goes in straight order - from the
first store to the last. Bu the best opportunity for vectorization will
happen if we're going to use reverse order - from last store to the
first. It may be best because usually users have some initialization
part + further processing and this first initialization may confuse
SLP vectorizer.
Reviewers: RKSimon, hfinkel, mkuper, spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D39606
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317821
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Sanjay Patel [Thu, 9 Nov 2017 18:26:49 +0000 (18:26 +0000)]
[Reassociate] auto-generate test checks; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317819
91177308-0d34-0410-b5e6-
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Sanjay Patel [Thu, 9 Nov 2017 18:14:24 +0000 (18:14 +0000)]
[Reassociate] don't name values "tmp"; NFCI
The toxic stew of created values named 'tmp' and tests that already have
values named 'tmp' and CHECK lines looking for values named 'tmp' causes
bad things to happen in our test line auto-generation scripts because it
wants to use 'TMP' as a prefix for unnamed values. Use less 'tmp' to
avoid that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317818
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Mandeep Singh Grang [Thu, 9 Nov 2017 18:05:17 +0000 (18:05 +0000)]
[GlobalMerge] Stable sort GlobalSets to fix non-deterministic sort order
Summary: This fixes failure in CodeGen/AArch64/global-merge-group-by-use.ll uncovered by D39245.
Reviewers: ab, asl
Reviewed By: ab
Subscribers: aemerson, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D39635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317817
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Nuno Lopes [Thu, 9 Nov 2017 17:35:36 +0000 (17:35 +0000)]
revert r317812 [BasicAA] fix build break by converting the previously introduced assert into an if stmt
The code has a bug, but some tests regress.
I'll discuss this further on the mailing list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317815
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Nuno Lopes [Thu, 9 Nov 2017 17:06:42 +0000 (17:06 +0000)]
[BasicAA] fix build break by converting the previously introduced assert into an if stmt
Apparently V1Size == -1 doest imply V2Size == -1, which is a bit surprising to me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317812
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Sanjay Patel [Thu, 9 Nov 2017 16:46:04 +0000 (16:46 +0000)]
revert r317809 - [Reassociate] regenerate test checks; NFC
The reassociate pass generates named values such as "%tmp2" which trips up the script's regex's
because the script uses a 'TMP' prefix for unnamed values (%2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317810
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