OSDN Git Service
Louis Gerbarg [Mon, 12 May 2014 22:13:07 +0000 (22:13 +0000)]
Fix ARM bswap16.ll test on Windows
Windows on ARM only supports thumb mode execution, so we have to
explicitly pick some non-Windows OS to test ARM mode codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208638
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Mon, 12 May 2014 22:01:27 +0000 (22:01 +0000)]
Try to fix an SDAG dependence issue with sret
r208453 added support for having sret on the second parameter. In that
change, the code for copying sret into a virtual register was hoisted
into the loop that lowers formal parameters. This caused a "Wrong
topological sorting" assertion failure during scheduling when a
parameter is passed in memory. This change undoes that by creating a
second loop that deals with sret.
I'm worried that this fix is incomplete. I don't fully understand the
dependence issues. However, with this change we produce the same DAGs
we used to produce, so if they are broken, they are just as broken as
they have always been.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208637
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Mon, 12 May 2014 21:50:44 +0000 (21:50 +0000)]
DebugInfo: Attach DW_AT_inline to inlined subprograms at DIE-construction time rather than as a post-processing step.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208636
91177308-0d34-0410-b5e6-
96231b3b80d8
Lang Hames [Mon, 12 May 2014 21:39:59 +0000 (21:39 +0000)]
[RuntimeDyld] Add support for MachO __jump_table and __pointers sections, and
SECTDIFF relocations on 32-bit x86.
This fixes several of the MCJIT regression test failures that show up on 32-bit
builds.
<rdar://problem/
16886294>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208635
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Mon, 12 May 2014 21:33:03 +0000 (21:33 +0000)]
DebugInfo: Make gmlt debug info more gmlt-like by removing variables.
For some impending improvements to debug info, LLVM will start assuming
that when the CU specifies llvm::DIBuilder::LineTablesOnly, the IR for
functions described by that CU will not include variables, types, etc.
(might be worth having some test coverage for GMLT + non-GMLT CUs,
especially with non-GMLT functions inlined into GMLT CU functions)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208634
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Mon, 12 May 2014 20:45:00 +0000 (20:45 +0000)]
Suggested improvement by Rafael Espindola to use isa<> in a few places
instead of dyn_cast<>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208628
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 12 May 2014 20:42:57 +0000 (20:42 +0000)]
Use cast<> for unchecked use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208627
91177308-0d34-0410-b5e6-
96231b3b80d8
Sebastian Pop [Mon, 12 May 2014 20:11:01 +0000 (20:11 +0000)]
use nullptr instead of NULL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208622
91177308-0d34-0410-b5e6-
96231b3b80d8
Adam Nemet [Mon, 12 May 2014 19:57:31 +0000 (19:57 +0000)]
[Test] Trim unnecessary .c and .cpp from config.suffix in lit.local.cfg
Tested by comparing make check VERBOSE=1 before and after to make sure
no tests are missed. (VERBOSE=1 prints the list of tests.)
Only one test :( remains where .cpp is required:
tools/llvm-cov/range_based_for.cpp:// RUN: llvm-cov range_based_for.cpp | FileCheck %s --check-prefix=STDOUT
The topic was discussed in this thread:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-
20140428/214905.html
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208621
91177308-0d34-0410-b5e6-
96231b3b80d8
Louis Gerbarg [Mon, 12 May 2014 19:53:52 +0000 (19:53 +0000)]
Add support bswap16 to/from memory compiling to rev16 on ARM/Thumb
The current patterns for REV16 misses mostn __builtin_bswap16() due to
legalization promoting the operands to from load/stores toi32s and then
truncing/extending them. This patch adds new patterns that catch the resultant
DAGs and codegens them to rev16 instructions. Tests included.
rdar://
15353652
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208620
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 12 May 2014 19:26:38 +0000 (19:26 +0000)]
Use cast<> for unchecked use
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208618
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 12 May 2014 19:23:21 +0000 (19:23 +0000)]
Use range for
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208617
91177308-0d34-0410-b5e6-
96231b3b80d8
Sebastian Pop [Mon, 12 May 2014 19:01:53 +0000 (19:01 +0000)]
do not assert when delinearization fails
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208615
91177308-0d34-0410-b5e6-
96231b3b80d8
Sebastian Pop [Mon, 12 May 2014 19:01:49 +0000 (19:01 +0000)]
use isZero()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208614
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Mon, 12 May 2014 18:23:35 +0000 (18:23 +0000)]
DwarfDebug: Avoid an extra map lookup while constructing abstract scope DIEs and reduce nesting/conditionals.
One test case had to be updated as it still had the extra indirection
for the variable list - removing the extra indirection got it back to
passing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208608
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Mon, 12 May 2014 18:04:06 +0000 (18:04 +0000)]
TableGen: use PrintMethods to print more aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Mon, 12 May 2014 18:03:42 +0000 (18:03 +0000)]
AArch64/ARM64: use InstAliases for NEON logical (imm) instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208606
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Mon, 12 May 2014 18:03:36 +0000 (18:03 +0000)]
AArch64/ARM64: implement "mov $Rd, $Imm" aliases in TableGen.
This is a slightly different approach to AArch64 (the base instruction
definitions aren't quite right for that to work), but achieves the
same thing and reduces C++ hackery in AsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208605
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 12 May 2014 17:49:57 +0000 (17:49 +0000)]
R600: Add mul24 intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208604
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Mon, 12 May 2014 17:14:48 +0000 (17:14 +0000)]
Make SimplifyDemandedBits understand BUILD_PAIR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208598
91177308-0d34-0410-b5e6-
96231b3b80d8
Matheus Almeida [Mon, 12 May 2014 16:59:34 +0000 (16:59 +0000)]
[mips] Move disassembler test (test_2r_msa64) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208594
91177308-0d34-0410-b5e6-
96231b3b80d8
Matheus Almeida [Mon, 12 May 2014 16:31:45 +0000 (16:31 +0000)]
[mips] Move disassembler test (Mips MSA test_vec) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208592
91177308-0d34-0410-b5e6-
96231b3b80d8
Matheus Almeida [Mon, 12 May 2014 16:26:53 +0000 (16:26 +0000)]
[mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208590
91177308-0d34-0410-b5e6-
96231b3b80d8
Matheus Almeida [Mon, 12 May 2014 16:23:45 +0000 (16:23 +0000)]
[mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208589
91177308-0d34-0410-b5e6-
96231b3b80d8
Matheus Almeida [Mon, 12 May 2014 16:20:46 +0000 (16:20 +0000)]
[mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208588
91177308-0d34-0410-b5e6-
96231b3b80d8
Matheus Almeida [Mon, 12 May 2014 16:16:59 +0000 (16:16 +0000)]
[mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208587
91177308-0d34-0410-b5e6-
96231b3b80d8
Matheus Almeida [Mon, 12 May 2014 16:10:00 +0000 (16:10 +0000)]
[mips] Move disassembler test (Mips MSA test_bit) into correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208586
91177308-0d34-0410-b5e6-
96231b3b80d8
Matheus Almeida [Mon, 12 May 2014 16:03:20 +0000 (16:03 +0000)]
[mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf) into
correct folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208584
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 15:43:41 +0000 (15:43 +0000)]
Revert: r208582 - [mips][mips64r6] Add sel.s and sel.d
Accidentally committed an unreviewed patch. Reverted it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208583
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 15:39:10 +0000 (15:39 +0000)]
[mips][mips64r6] Add sel.s and sel.d
Summary:
Also use named constants for common opcode fields.
Depends on D3669
Reviewers: jkolek, vmedic, zoran.jovanovic
Differential Revision: http://reviews.llvm.org/D3670
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208582
91177308-0d34-0410-b5e6-
96231b3b80d8
James Molloy [Mon, 12 May 2014 15:30:31 +0000 (15:30 +0000)]
[ARM64-BE] Correct grammar mistake pointed out by Tobias.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208580
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 15:24:16 +0000 (15:24 +0000)]
[mips][mips64r6] Add d?div, d?mod, d?divu, d?modu
Summary: Depends on D3668
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3669
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208579
91177308-0d34-0410-b5e6-
96231b3b80d8
James Molloy [Mon, 12 May 2014 15:13:39 +0000 (15:13 +0000)]
[ARM64-BE] Add sphinx documentation for the ARM64 NEON implementation.
There are some interesting decisions based on non-obvious rationale in
the ARM64-BE NEON implementation - decent documentation is definitely required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208577
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 15:12:45 +0000 (15:12 +0000)]
[mips][mips64r6] Added mul/mulu/muh/muhu
Summary: The 'mul' line of the test is temporarily commented out because it currently matches the MIPS32 mul instead of the MIPS32r6 mul. This line will be uncommented when we disable the MIPS32 mul on MIPS32r6.
Reviewers: jkolek, zoran.jovanovic, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3668
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208576
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 14:43:25 +0000 (14:43 +0000)]
Move EmitDwarfAdvanceLineAddr and EmitDwarfAdvanceFrameAddr to the obj streamer.
This lets us delete the MCAsmStreamer implementation. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208570
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 14:40:12 +0000 (14:40 +0000)]
Pass a MCObjectStreamer instead of a MCStreamer when possible.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208569
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 14:28:48 +0000 (14:28 +0000)]
Pass a MCObjectStreamer instead of a MCStreamer when possible.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208567
91177308-0d34-0410-b5e6-
96231b3b80d8
Aaron Ballman [Mon, 12 May 2014 14:22:58 +0000 (14:22 +0000)]
Silencing an MSVC warning about not all control paths returning a value (even though the switch is fully covered). No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208565
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Mon, 12 May 2014 14:13:21 +0000 (14:13 +0000)]
ARM64: remove dead validation code from the AsmParser.
If this code triggers, any immediate has already been validated so it can't
possibly trigger a diagnostic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208564
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Mon, 12 May 2014 14:13:17 +0000 (14:13 +0000)]
ARM64: merge "extend" and "shift" addressing-mode enums.
In terms of assembly, these have too much overlap to be neatly modelled as
disjoint classes: in many cases "lsl" is an acceptable alternative to either
"uxtw" or "uxtx".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208563
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 14:02:44 +0000 (14:02 +0000)]
Move EH/Debug frame handling to the object streamer.
Now that the asm streamer doesn't use it, the MCStreamer doesn't need to know
about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208562
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:47:05 +0000 (13:47 +0000)]
Remove always true argument and unused field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208561
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:40:49 +0000 (13:40 +0000)]
Remove always true argument and field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208559
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:34:25 +0000 (13:34 +0000)]
Remove always true argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208558
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:30:10 +0000 (13:30 +0000)]
Remove an always true argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208557
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:20:37 +0000 (13:20 +0000)]
Remove write only field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208555
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:18:13 +0000 (13:18 +0000)]
Remove now empty method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208554
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:12:22 +0000 (13:12 +0000)]
Remove the always true UseCFI member.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208553
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Mon, 12 May 2014 13:12:08 +0000 (13:12 +0000)]
X86: Make sure that we have SSE4.1 before we generate insertps nodes.
PR19721.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208552
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:07:11 +0000 (13:07 +0000)]
Remove the useCFI constructor argument to MCAsmStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208551
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 13:04:32 +0000 (13:04 +0000)]
[mips] Marked up instructions added in MIPS32 and tested that IAS for -mcpu=mips2 does not accept them
Summary:
To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are explicitly tested.
Depends on D3695
Reviewers: vmedic
Differential Revision: http://reviews.llvm.org/D3696
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208549
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Mon, 12 May 2014 13:01:42 +0000 (13:01 +0000)]
Remove MCUseCFI from TargetMachine.
It was always true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208547
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 12:52:44 +0000 (12:52 +0000)]
[mips] Marked up instructions added in MIPS-V and tested that IAS for -mcpu=mips[1234] does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-V that was available in MIPS32R2
Most of these instructions are correctly rejected but with the wrong error
message. These have been placed in a separate test for now. It happens
because many of the MIPS V instructions have not been implemented.
Depends on D3694
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3695
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208546
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 12:41:59 +0000 (12:41 +0000)]
[mips] Fold FeatureBitCount into FeatureMips32 and FeatureMips64
Summary:
DCL[ZO] are now correctly marked as being MIPS64 instructions. This has no
effect on the CodeGen tests since expansion of i64 prevented their use
anyway.
The check for MIPS16 to prevent the use of CLZ no longer prevents DCLZ as
well. This is not a functional change since DCLZ is still prohibited by
being a MIPS64 instruction (MIPS16 is only compatible with MIPS32).
No functional change
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3694
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208544
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 12:28:15 +0000 (12:28 +0000)]
[mips] Fold FeatureSEInReg into FeatureMips32r2
Summary: No functional change
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208543
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 12:15:41 +0000 (12:15 +0000)]
[mips] Fold FeatureSwap into FeatureMips32r2 and FeatureMips64r2
Summary:
dsbh and dshd are not available on Mips32r2. No codegen test changes
required since expansion of i64 prevented the use of these instructions
anyway.
Depends on D3690
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3692
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208542
91177308-0d34-0410-b5e6-
96231b3b80d8
Daniel Sanders [Mon, 12 May 2014 11:56:16 +0000 (11:56 +0000)]
[mips] Replace FeatureFPIdx with FeatureMips4_32r2
Summary:
No functional change.
The minor change to the MIPS16 code is in preparation for a patch that will handle 32-bit FPIdx instructions separately to 64-bit (because they were added in different revisions)
Depends on D3677
Reviewers: rkotler, vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3690
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208541
91177308-0d34-0410-b5e6-
96231b3b80d8
Bradley Smith [Mon, 12 May 2014 11:49:16 +0000 (11:49 +0000)]
[ARM64] Add proper bounds checking/diagnostics to logical shifts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208540
91177308-0d34-0410-b5e6-
96231b3b80d8
Christian Pirker [Mon, 12 May 2014 11:19:20 +0000 (11:19 +0000)]
ARM: Implement big endian bit-conversion for NEON type
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208538
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Mon, 12 May 2014 10:16:46 +0000 (10:16 +0000)]
X86ISelLowering.cpp:LowerINTRINSIC_W_CHAIN(): Prune impossible "default:" [-Wcovered-switch-default]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208533
91177308-0d34-0410-b5e6-
96231b3b80d8
Serge Pavlov [Mon, 12 May 2014 10:11:27 +0000 (10:11 +0000)]
Fix type of shuffle obtained from reordering with binary operation
In transformation:
BinOp(shuffle(v1,undef), shuffle(v2,undef)) -> shuffle(BinOp(v1, v2),undef)
type of the undef argument must be same as type of BinOp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208531
91177308-0d34-0410-b5e6-
96231b3b80d8
Bradley Smith [Mon, 12 May 2014 09:44:57 +0000 (09:44 +0000)]
[ARM64] Add diagnostics for bitfield extract/insert instructions
Unfortunately, since ARM64 models all these instructions as aliases,
the checks need to be done at the time the alias is seen rather than
during instruction validation as AArch64 does it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208529
91177308-0d34-0410-b5e6-
96231b3b80d8
Bradley Smith [Mon, 12 May 2014 09:41:43 +0000 (09:41 +0000)]
[ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208528
91177308-0d34-0410-b5e6-
96231b3b80d8
Bradley Smith [Mon, 12 May 2014 09:38:16 +0000 (09:38 +0000)]
[ARM64] Move register/register MOV handling into tablegen and improve diagnostics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208527
91177308-0d34-0410-b5e6-
96231b3b80d8
Elena Demikhovsky [Mon, 12 May 2014 07:45:41 +0000 (07:45 +0000)]
Fixed compilation issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208524
91177308-0d34-0410-b5e6-
96231b3b80d8
Elena Demikhovsky [Mon, 12 May 2014 07:18:51 +0000 (07:18 +0000)]
AVX-512: changes in intrinsics
1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed.
2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012).
3) I added gather/scatter prefetch intrinsics.
4) I fixed MRMm encoding for masked instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208522
91177308-0d34-0410-b5e6-
96231b3b80d8
Saleem Abdulrasool [Mon, 12 May 2014 06:08:18 +0000 (06:08 +0000)]
CodeGen: add parenthesis around complex expression
Add missing parenthesis suggested by GCC. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208519
91177308-0d34-0410-b5e6-
96231b3b80d8
Serge Pavlov [Mon, 12 May 2014 05:44:53 +0000 (05:44 +0000)]
Fix reordering of shuffles and binary operations
Do not apply transformation:
BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2))
if operands v1 and v2 are of different size.
This change fixes PR19717, which was caused by r208488.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208518
91177308-0d34-0410-b5e6-
96231b3b80d8
NAKAMURA Takumi [Mon, 12 May 2014 03:32:56 +0000 (03:32 +0000)]
Reformat blank lines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208515
91177308-0d34-0410-b5e6-
96231b3b80d8
Matt Arsenault [Sun, 11 May 2014 21:24:41 +0000 (21:24 +0000)]
Fix return before else
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208510
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Sun, 11 May 2014 19:29:11 +0000 (19:29 +0000)]
[PowerPC] Add global named register support
Support for the intrinsics that read from and write to global named registers
is added for r1, r2 and r13 (depending on the subtarget).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208509
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Sun, 11 May 2014 19:29:07 +0000 (19:29 +0000)]
Pass the value type to TLI::getRegisterByName
We must validate the value type in TLI::getRegisterByName, because if we
don't and the wrong type was used with the IR intrinsic, then we'll assert
(because we won't be able to find a valid register class with which to
construct the requested copy operation). For PPC64, additionally, the type
information is necessary to decide between the 64-bit register and the 32-bit
subregister.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208508
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Sun, 11 May 2014 19:28:55 +0000 (19:28 +0000)]
Add 'override' to getRegisterByName in *ISelLowering.h
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208507
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Sun, 11 May 2014 18:12:17 +0000 (18:12 +0000)]
DebugInfo: Include lexical scopes in inlined subroutines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208506
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Sun, 11 May 2014 17:25:50 +0000 (17:25 +0000)]
DebugInfo: Simplify/correct test for correct constant emission when dealing with derived types.
This test was using the inliner and other optimizations to test a case
that's actually a bug anyway. Bug and possible fix/discussion described
here ( http://reviews.llvm.org/D3714 ).
But the functionality that was implemented along with this test is still
desired, so simplify the test to verify a more obvious/less wrong case
that the functionality addressed: looking through const sugar to the
underlying type when emitting a constant (so the constant is emitted as
signed/unsigned as appropriate depending on the signedness of the
underlying type).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208504
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Sun, 11 May 2014 17:04:05 +0000 (17:04 +0000)]
DwarfUnit: Make explicit a limitation/bug in enumeration constant emission.
Filed as PR19712, LLVM fails to detect the right type of an enum
constant when a frontend does not provide an underlying type for the
enumeration type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208502
91177308-0d34-0410-b5e6-
96231b3b80d8
Hal Finkel [Sun, 11 May 2014 16:23:29 +0000 (16:23 +0000)]
[PowerPC] On PPC32, 128-bit shifts might be runtime calls
The counter-loops formation pass needs to know what operations might be
function calls (because they can't appear in counter-based loops). On PPC32,
128-bit shifts might be runtime calls (even though you can't use __int128 on
PPC32, it seems that SROA might form them).
Fixes PR19709.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208501
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Sun, 11 May 2014 16:08:41 +0000 (16:08 +0000)]
DwarfUnit: Pick a winner between isTypeSigned and isUnsignedDIType.
And the winner by a nose is isUnsignedDIType, for no particular reason.
These two functions were just complements of each other and used in very
related code, so refactor callers to just use one of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208500
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Sun, 11 May 2014 15:56:59 +0000 (15:56 +0000)]
DwarfUnit: Factor out calling isUnsignedDIType into a utility function so each caller of emitConstantValue doesn't have to call it separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208496
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Sun, 11 May 2014 15:47:39 +0000 (15:47 +0000)]
DwarfUnit: Share common constant value emission between APInts of small (<= 64 bit) and MCOperand immediates.
Doesn't seem a good reason to duplicate this code (it was more literally
duplicated prior to r208494, and while the dataN code /does/ actually
fire in this case, it doesn't seem necessary (and the DWARF standard
recommends using udata/sdata pervasively instead of dataN, so as to
indicate signedness of the values))
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208495
91177308-0d34-0410-b5e6-
96231b3b80d8
David Blaikie [Sun, 11 May 2014 15:06:20 +0000 (15:06 +0000)]
DebugInfo: Simplify constant value emission.
This code looks to have become dead at some time in the past. I tried to
reproduce cases where LLVM would emit constants with dataN, but could
not. Upon inspection it seems the code doesn't do that anymore - the
only time a size is provided by isTypeSigned is when the type is signed,
and in those cases we use sdata. dataN is only used for unsigned types
and isTypeSigned doesn't provide a value for sizeInBits in that case.
Remove the dead cases/size plumbing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208494
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Sun, 11 May 2014 10:28:58 +0000 (10:28 +0000)]
SLPVectorizer: Instead of just performing CSE on dead blocks ignore them completely.
Turns out that there is a very cheap way of testing whether a block is dead,
just look it up in the DomTree. We have to do this anyways so just ignore
unreachable blocks before sorting by domination. This restores a proper
ordering for std::stable_sort when dead code is present.
Covered by existing tests & buildbots running in STL debug mode (MSVC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208492
91177308-0d34-0410-b5e6-
96231b3b80d8
Simon Atanasyan [Sun, 11 May 2014 08:48:09 +0000 (08:48 +0000)]
[llvm-readobj] Print values of FLAGS and MIPS_FLAGS dynamic table tags
in a human readable form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208489
91177308-0d34-0410-b5e6-
96231b3b80d8
Serge Pavlov [Sun, 11 May 2014 08:46:12 +0000 (08:46 +0000)]
Reorder shuffle and binary operation.
This patch enables transformations:
BinOp(shuffle(v1), shuffle(v2)) -> shuffle(BinOp(v1, v2))
BinOp(shuffle(v1), const1) -> shuffle(BinOp, const2)
They allow to eliminate extra shuffles in some cases.
Differential Revision: http://reviews.llvm.org/D3525
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208488
91177308-0d34-0410-b5e6-
96231b3b80d8
Filipe Cabecinhas [Sun, 11 May 2014 08:12:56 +0000 (08:12 +0000)]
Fixed a bug when lowering build_vector (PR19694)
When lowering build_vector to an insertps, we would still lower it, even
if the source vectors weren't v4x32. This would break on avx if the source
was a v8x32. We now check the type of the source vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208487
91177308-0d34-0410-b5e6-
96231b3b80d8
Vincent Lejeune [Sat, 10 May 2014 19:18:39 +0000 (19:18 +0000)]
R600/SI: Fold fabs/fneg into src input modifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480
91177308-0d34-0410-b5e6-
96231b3b80d8
Vincent Lejeune [Sat, 10 May 2014 19:18:33 +0000 (19:18 +0000)]
R600/SI: Prettier display of input modifiers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208479
91177308-0d34-0410-b5e6-
96231b3b80d8
Vincent Lejeune [Sat, 10 May 2014 19:18:25 +0000 (19:18 +0000)]
R600/SI: Use pseudo instruction for fabs/clamp/fneg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208478
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Sat, 10 May 2014 17:47:18 +0000 (17:47 +0000)]
SCEV: Use range-based for loop and fold variable into assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208476
91177308-0d34-0410-b5e6-
96231b3b80d8
Tim Northover [Sat, 10 May 2014 07:37:50 +0000 (07:37 +0000)]
ARM64: fix SELECT_CC lowering in absence of NaNs.
We were swapping the true & false results while testing for FMAX/FMIN,
but not putting them back to the original state if the later checks
failed.
Should fix PR19700.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208469
91177308-0d34-0410-b5e6-
96231b3b80d8
Kevin Enderby [Fri, 9 May 2014 23:57:49 +0000 (23:57 +0000)]
Fix llvm-nm to print the full 64-bit address for symbols in 64-bit object files.
The implementation might be better to have a method is64Bit() in the class
SymbolicFile instead of having the static routine isSymbolList64Bit() in
llvm-nm.cpp . But this is very much in the sprit of isObject() and
getNMTypeChar() in llvm-nm.cpp that has a series of if else statements
based on the specific class of the SymbolicFile. I can update this if
folks would like.
Also the tests were updated to be explicit about checking the address for
64-bits or 32-bits from object files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208463
91177308-0d34-0410-b5e6-
96231b3b80d8
Benjamin Kramer [Fri, 9 May 2014 23:28:49 +0000 (23:28 +0000)]
SLPVectorizer: When sorting by domination for CSE don't assert on unreachable code.
There is no total ordering if the CFG is disconnected. We don't care if we
catch all CSE opportunities in dead code either so just exclude ignore them in
the assert.
PR19646
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208461
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Fri, 9 May 2014 22:56:42 +0000 (22:56 +0000)]
Revert "[ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'"
This reverts commit r200561.
This calling convention was an attempt to match the MSVC C++ ABI for
methods that return structures by value. This solution didn't scale,
because it would have required splitting every CC available on Windows
into two: one for methods and one for free functions.
Now that we can put sret on the second arg (r208453), and Clang does
that (r208458), revert this hack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208459
91177308-0d34-0410-b5e6-
96231b3b80d8
Sebastian Pop [Fri, 9 May 2014 22:45:07 +0000 (22:45 +0000)]
move findArrayDimensions to ScalarEvolution
we do not use the information from SCEVAddRecExpr to compute the shape of the array,
so a better place for this function is in ScalarEvolution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208456
91177308-0d34-0410-b5e6-
96231b3b80d8
Sebastian Pop [Fri, 9 May 2014 22:45:02 +0000 (22:45 +0000)]
fix typo in debug message
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208455
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Fri, 9 May 2014 22:32:13 +0000 (22:32 +0000)]
Allow sret on the second parameter as well as the first
MSVC always places the implicit sret parameter after the implicit this
parameter of instance methods. We used to handle this for
x86_thiscallcc by allocating the sret parameter on the stack and leaving
the this pointer in ecx, but that doesn't handle alternative calling
conventions like cdecl, stdcall, fastcall, or the win64 convention.
Instead, change the verifier to allow sret on the second parameter.
This also requires changing the Mips and X86 backends to return the
argument with the sret parameter, instead of assuming that the sret
parameter comes first.
The Sparc backend also returns sret parameters in a register, but I
wasn't able to update it to handle secondary sret parameters. It
currently calls report_fatal_error if you feed it an sret in the second
parameter.
Reviewers: rafael.espindola, majnemer
Differential Revision: http://reviews.llvm.org/D3617
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208453
91177308-0d34-0410-b5e6-
96231b3b80d8
Reid Kleckner [Fri, 9 May 2014 21:52:48 +0000 (21:52 +0000)]
Fix ARM intrinsics-overflow.ll test on Windows
Windows on ARM only supports thumb mode execution, so we have to
explicitly pick some non-Windows OS to test ARM mode codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208448
91177308-0d34-0410-b5e6-
96231b3b80d8
Rafael Espindola [Fri, 9 May 2014 21:49:17 +0000 (21:49 +0000)]
Don't crash on redefinitions.
One error we were not deleting the alias or putting it in the Module. The
end result is that there was an use left of the aliasee when the module was
deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208447
91177308-0d34-0410-b5e6-
96231b3b80d8
Jonathan Roelofs [Fri, 9 May 2014 18:06:22 +0000 (18:06 +0000)]
Fix broken build
ARM64 backend was missing a required_library entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208437
91177308-0d34-0410-b5e6-
96231b3b80d8
Louis Gerbarg [Fri, 9 May 2014 17:02:49 +0000 (17:02 +0000)]
Add custom lowering for add/sub with overflow intrinsics to ARM
This patch adds support to ARM for custom lowering of the
llvm.{u|s}add.with.overflow.i32 intrinsics for i32/i64. This is particularly useful
for handling idiomatic saturating math functions as generated by
InstCombineCompare.
Test cases included.
rdar://
14853450
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208435
91177308-0d34-0410-b5e6-
96231b3b80d8