OSDN Git Service
Adam Nemet [Thu, 23 Feb 2017 23:11:21 +0000 (23:11 +0000)]
[OptDiag] Remove hotness parameter from legacy remark ctors
Anything using hotness should be using ORE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296038
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Adam Nemet [Thu, 23 Feb 2017 23:11:11 +0000 (23:11 +0000)]
[OptDiag] Hide legacy remark ctors
These are only used when emitting remarks without ORE directly using the free
functions emitOptimizationRemark*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296037
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Bryant Wong [Thu, 23 Feb 2017 23:00:46 +0000 (23:00 +0000)]
[ADT] Fix zip iterator interface.
This commit provides `zip_{first,shortest}` with the standard member types and
methods expected of iterators (e.g., `difference_type`), in order for zip to be
used with other adaptors, such as `make_filter_range`.
Support for reverse iteration has also been added.
Differential Revision: https://reviews.llvm.org/D30246
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296036
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Sanjoy Das [Thu, 23 Feb 2017 22:50:52 +0000 (22:50 +0000)]
[IR] Add a Instruction::dropPoisonGeneratingFlags helper
Summary:
The helper will be used in a later change. This change itself is NFC
since the only user of this new function is its unit test.
Reviewers: majnemer, efriedma
Reviewed By: efriedma
Subscribers: efriedma, mcrosier, llvm-commits
Differential Revision: https://reviews.llvm.org/D30184
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296035
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Artem Belevich [Thu, 23 Feb 2017 22:38:24 +0000 (22:38 +0000)]
[NVPTX] Added support for .f16x2 instructions.
This patch enables support for .f16x2 operations.
Added new register type Float16x2.
Added support for .f16x2 instructions.
Added handling of vectorized loads/stores of v2f16 values.
Differential Revision: https://reviews.llvm.org/D30057
Differential Revision: https://reviews.llvm.org/D30310
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296032
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Tim Northover [Thu, 23 Feb 2017 22:35:00 +0000 (22:35 +0000)]
ARM: make sure FastISel bails on f64 operations for Cortex-M4.
FastISel wasn't checking the isFPOnlySP subtarget feature before emitting
double-precision operations, so it got completely invalid CodeGen for doubles
on Cortex-M4F.
The normal ISel testing wasn't spectacular either so I added a second RUN line
to improve that while I was in the area.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296031
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Hans Wennborg [Thu, 23 Feb 2017 22:29:00 +0000 (22:29 +0000)]
Revert r282872 "CVP. Turn marking adds as no wrap on by default"
While not CVP's fault, this caused miscompiles (PR31181). Reverting
until those are resolved.
(This also reverts the follow-ups r288154 and r288161 which removed the
flag.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296030
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Vedant Kumar [Thu, 23 Feb 2017 22:20:32 +0000 (22:20 +0000)]
[llvm-cov] Strip redundant path components from filenames (fix PR31982)
Instead of stripping the longest common prefix off of the filenames in a
report, strip out the longest chain of redundant path components. This
fixes the case in PR31982, where there are two files with the same
prefix, and stripping out the LCP makes things less intelligible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296029
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Dehao Chen [Thu, 23 Feb 2017 22:15:18 +0000 (22:15 +0000)]
Add call branch annotation for ICP promoted direct call in SamplePGO mode.
Summary: SamplePGO uses branch_weight annotation to represent callsite hotness. When ICP promotes an indirect call to direct call, we need to make sure the direct call is annotated with branch_weight in SamplePGO mode, so that downstream function inliner can use hot callsite heuristic.
Reviewers: davidxl, eraman, xur
Reviewed By: davidxl, xur
Subscribers: mehdi_amini, llvm-commits
Differential Revision: https://reviews.llvm.org/D30282
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296028
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Krzysztof Parzyszek [Thu, 23 Feb 2017 22:11:52 +0000 (22:11 +0000)]
[Hexagon] Handle saturations in Hexagon bit tracker
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296026
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Krzysztof Parzyszek [Thu, 23 Feb 2017 22:08:50 +0000 (22:08 +0000)]
[Hexagon] Allow setting register in BitVal without storing into map
In the bit tracker, references to other bit values in which the register
is 0 are prohibited. This means that generating self-referential register
cells like { w:32 [0-15]:s[0-15] [16-31]:s[15] } is impossible. In order
to get a self-referential cell, it had to be stored into a map and then
reloaded from it. To avoid this step, add a function that will set the
register to a given value without going through the map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296025
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Stanislav Mekhanoshin [Thu, 23 Feb 2017 21:51:28 +0000 (21:51 +0000)]
[AMDGPU] Shut the warning "getRegUnitWeight hides overload...". NFC.
Clang issues warning about hidden overload. That was intended, so
add "using AMDGPUGenRegisterInfo::getRegUnitWeight;" to mute it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296021
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Adam Nemet [Thu, 23 Feb 2017 21:32:53 +0000 (21:32 +0000)]
[ORE] Remove ORE.emit{{.+}} functions
Last use was killed in my previous patch. The preferred way is now to
construct the remark, pipe things to it and pass it to ORE.emit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296019
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Kyle Butt [Thu, 23 Feb 2017 21:22:24 +0000 (21:22 +0000)]
CodeGen: MachineBlockPlacement: Rename member to more general name. NFC.
Rename ComputedTrellisEdges to ComputedEdges to allow for other methods of
pre-computing edges.
Differential Revision: https://reviews.llvm.org/D30308
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296018
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Adam Nemet [Thu, 23 Feb 2017 21:17:36 +0000 (21:17 +0000)]
[LAA] Remove unused LoopAccessReport
The need for this removed when I converted everything to use the opt-remark
classes directly with the streaming interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296017
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Adam Nemet [Thu, 23 Feb 2017 21:17:31 +0000 (21:17 +0000)]
[LV] Remove unused VectorizationReport
The need for this removed when I converted everything to use the opt-remark
classes directly with the streaming interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296016
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Evgeniy Stepanov [Thu, 23 Feb 2017 21:06:35 +0000 (21:06 +0000)]
Disable TLS for stack protector on Android API<17.
The TLS slot did not exist back then.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296014
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Ahmed Bougacha [Thu, 23 Feb 2017 21:05:42 +0000 (21:05 +0000)]
[GlobalISel] Emit opt remarks on isel fallbacks.
Having more fine-grained information on the specific construct that
caused us to fallback is valuable for large-scale data collection.
We still have the fallback warning, that's also used for FastISel.
We still need to remove the fallback warning, and teach FastISel to also
emit remarks (it currently has a combination of the warning, stats, and
debug prints: the remarks could unify all three).
The abort-on-fallback path could also be better handled using remarks:
one could imagine a "-Rpass-error", analoguous to "-Werror", which would
promote missed/failed remarks to errors. It's not clear whether that
would be useful for other remarks though, so we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296013
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Ahmed Bougacha [Thu, 23 Feb 2017 21:05:33 +0000 (21:05 +0000)]
[CodeGen] Teach opt remarks how to print MI instructions.
This will be used with GISel opt remarks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296012
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Ahmed Bougacha [Thu, 23 Feb 2017 21:05:29 +0000 (21:05 +0000)]
[CodeGen] Print MI without a newline when skipping debugloc. NFC.
This matches the behavior for skip-operands. While there, document it.
This is a follow-up to r296007.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296011
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Ahmed Bougacha [Thu, 23 Feb 2017 21:05:23 +0000 (21:05 +0000)]
[CodeGen] Use const MBBs in the opt remark diagnostics. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296010
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Stanislav Mekhanoshin [Thu, 23 Feb 2017 20:19:44 +0000 (20:19 +0000)]
Correct register pressure calculation in presence of subregs
If a subreg is used in an instruction it counts as a whole superreg
for the purpose of register pressure calculation. This patch corrects
improper register pressure calculation by examining operand's lane mask.
Differential Revision: https://reviews.llvm.org/D29835
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296009
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Ahmed Bougacha [Thu, 23 Feb 2017 19:17:34 +0000 (19:17 +0000)]
[ORE] Use const CodeRegions in the remark diagnostics. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296008
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Ahmed Bougacha [Thu, 23 Feb 2017 19:17:31 +0000 (19:17 +0000)]
[CodeGen] Add a way to SkipDebugLoc in MachineInstr::print(). NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296007
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Ahmed Bougacha [Thu, 23 Feb 2017 19:17:24 +0000 (19:17 +0000)]
[GlobalISel] Simplify Select type cleanup using a ScopeExit. NFC.
This lets us use more natural early-returns when selection fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296006
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Adrian Prantl [Thu, 23 Feb 2017 19:13:48 +0000 (19:13 +0000)]
Revert "Teach the IR verifier to reject conflicting debug info for function arguments."
This reverts commit r295749 while investigating PR32042.
It looks like this check uncovered a problem in the frontend that
needs to be fixed before the check can be enabled again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296005
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Sanjay Patel [Thu, 23 Feb 2017 19:02:33 +0000 (19:02 +0000)]
[DAG] add convenience function to get -1 constant; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296004
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Chad Rosier [Thu, 23 Feb 2017 18:49:03 +0000 (18:49 +0000)]
[Reassociate] Add negated value of negative constant to the Duplicates list.
In OptimizeAdd, we scan the operand list to see if there are any common factors
between operands that can be factored out to reduce the number of multiplies
(e.g., 'A*A+A*B*C+D' -> 'A*(A+B*C)+D'). For each operand of the operand list, we
only consider unique factors (which is tracked by the Duplicate set). Now if we
find a factor that is a negative constant, we add the negated value as a factor
as well, because we can percolate the negate out. However, we mistakenly don't
add this negated constant to the Duplicates set.
Consider the expression A*2*-2 + B. Obviously, nothing to factor.
For the added value A*2*-2 we over count 2 as a factor without this change,
which causes the assert reported in PR30256. The problem is that this code is
assuming that all the multiply operands of the add are already reassociated.
This change avoids the issue by making OptimizeAdd tolerate multiplies which
haven't been completely optimized; this sort of works, but we're doing wasted
work: we'll end up revisiting the add later anyway.
Another possible approach would be to enforce RPO iteration order more strongly.
If we have RedoInsts, we process them immediately in RPO order, rather than
waiting until we've finished processing the whole function. Intuitively, it
seems like the natural approach: reassociation works on expression trees, so
the optimization only works in one direction. That said, I'm not sure how
practical that is given the current Reassociate; the "optimal" form for an
expression depends on its use list (see all the uses of "user_back()"), so
Reassociate is really an iterative optimization of sorts, so any changes here
would probably get messy.
PR30256
Differential Revision: https://reviews.llvm.org/D30228
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@296003
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Dehao Chen [Thu, 23 Feb 2017 18:27:45 +0000 (18:27 +0000)]
Use base discriminator in sample pgo profile matching.
Summary: The discriminator has been encoded, and only the base discriminator should be used during profile matching.
Reviewers: dblaikie, davidxl
Reviewed By: dblaikie, davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30218
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295999
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Krzysztof Parzyszek [Thu, 23 Feb 2017 17:47:34 +0000 (17:47 +0000)]
[Hexagon] Avoid IMPLICIT_DEFs as new-value producers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295997
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Adam Nemet [Thu, 23 Feb 2017 17:30:01 +0000 (17:30 +0000)]
[LazyMachineBFI] Reimplement with getAnalysisIfAvailable
Since LoopInfo is not available in machine passes as universally as in IR
passes, using the same approach for OptimizationRemarkEmitter as we did for IR
will run LoopInfo and DominatorTree unnecessarily. (LoopInfo is not used
lazily by ORE.)
To fix this, I am modifying the approach I took in D29836. LazyMachineBFI now
uses its client passes including MachineBFI itself that are available or
otherwise compute them on the fly.
So for example GreedyRegAlloc, since it's already using MBFI, will reuse that
instance. On the other hand, AsmPrinter in Justin's patch will generate DT,
LI and finally BFI on the fly.
(I am of course wondering now if the simplicity of this approach is even
preferable in IR. I will do some experiments.)
Testing is provided by an updated version of D29837 which requires Justin's
patch to bring ORE to the AsmPrinter.
Differential Revision: https://reviews.llvm.org/D30128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295996
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Filipe Cabecinhas [Thu, 23 Feb 2017 17:10:28 +0000 (17:10 +0000)]
[AddressSanitizer] Add PS4 offset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295994
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Sanjay Patel [Thu, 23 Feb 2017 16:39:51 +0000 (16:39 +0000)]
[InstCombine] use loop instead of recursion to peek through FPExt; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295992
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Sanjay Patel [Thu, 23 Feb 2017 16:26:03 +0000 (16:26 +0000)]
[InstCombine] use 'match' to reduce code; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295991
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Jan Vesely [Thu, 23 Feb 2017 16:12:21 +0000 (16:12 +0000)]
AMDGPU/SI: Fix trunc i16 pattern
Hit on ASICs that support 16bit instructions.
Differential Revision: https://reviews.llvm.org/D30281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295990
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Simon Pilgrim [Thu, 23 Feb 2017 16:07:04 +0000 (16:07 +0000)]
Strip trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295989
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Krzysztof Parzyszek [Thu, 23 Feb 2017 15:02:09 +0000 (15:02 +0000)]
[Hexagon] Patterns for CTPOP, BSWAP and BITREVERSE
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295981
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Tobias Grosser [Thu, 23 Feb 2017 14:27:07 +0000 (14:27 +0000)]
[docs] Add information about how to checkout polly to getting started page
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295974
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Diana Picus [Thu, 23 Feb 2017 14:18:41 +0000 (14:18 +0000)]
[ARM] GlobalISel: Lower call returns
Introduce a common ValueHandler for call returns and formal arguments, and
inherit two different versions for handling the differences (at the moment the
only difference is the way physical registers are marked as used).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295973
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Alexey Bataev [Thu, 23 Feb 2017 13:37:09 +0000 (13:37 +0000)]
[SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong
result
Summary:
If the same value is used several times as an extra value, SLP
vectorizer takes it into account only once instead of actual number of
using.
For example:
```
int val = 1;
for (int y = 0; y < 8; y++) {
for (int x = 0; x < 8; x++) {
val = val + input[y * 8 + x] + 3;
}
}
```
We have 2 extra rguments: `1` - initial value of horizontal reduction
and `3`, which is added 8*8 times to the reduction. Before the patch we
added `1` to the reduction value and added once `3`, though it must be
added 64 times.
Reviewers: mkuper, mzolotukhin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295972
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Diana Picus [Thu, 23 Feb 2017 13:25:43 +0000 (13:25 +0000)]
[ARM] GlobalISel: Lower call parameters in regs
Add support for lowering calls with parameters than can fit into regs. Use the
same ValueHandler that we used for function returns, but rename it to match its
new, extended purpose.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295971
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Ayman Musa [Thu, 23 Feb 2017 13:15:44 +0000 (13:15 +0000)]
[X86][AVX] Disable VCVTSS2SD & VCVTSD2SS memory folding and fix the register class of their first input when creating node in fast-isel.
(Quick fix to buildbot failure after rL295940 commit).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295970
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Simon Dardis [Thu, 23 Feb 2017 12:40:58 +0000 (12:40 +0000)]
[mips][ias] Further relax operands of certain assembly instructions
This patch adjusts the most relaxed predicate of immediate operands to accept
immediate forms such as ~(0xf0000000|0x000f00000). Previously these forms
would be accepted by GAS and rejected by IAS.
This partially resolves PR/30383.
Thanks to Sean Bruno for reporting the issue!
Reviewers: slthakur, seanbruno
Differential Revision: https://reviews.llvm.org/D29218
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295965
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Kristof Beyls [Thu, 23 Feb 2017 12:24:55 +0000 (12:24 +0000)]
Fix assertion failure in ARMConstantIslandPass.
The ARMConstantIslandPass didn't have support for handling accesses to
constant island objects through ARM::t2LDRBpci instructions. This adds
support for that.
This fixes PR31997.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295964
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Simon Pilgrim [Thu, 23 Feb 2017 12:00:34 +0000 (12:00 +0000)]
Fix signed/unsigned comparison warning on MSVC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295962
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Alexey Bataev [Thu, 23 Feb 2017 11:09:35 +0000 (11:09 +0000)]
Revert "[SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong"
This reverts commit
7c5141e577d9efd1c8e3087566a38ce6b3a41a84.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295957
91177308-0d34-0410-b5e6-
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Alexey Bataev [Thu, 23 Feb 2017 10:57:15 +0000 (10:57 +0000)]
[SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong
result
Summary:
If the same value is used several times as an extra value, SLP
vectorizer takes it into account only once instead of actual number of
using.
For example:
```
int val = 1;
for (int y = 0; y < 8; y++) {
for (int x = 0; x < 8; x++) {
val = val + input[y * 8 + x] + 3;
}
}
```
We have 2 extra rguments: `1` - initial value of horizontal reduction
and `3`, which is added 8*8 times to the reduction. Before the patch we
added `1` to the reduction value and added once `3`, though it must be
added 64 times.
Reviewers: mkuper, mzolotukhin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295956
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Thu, 23 Feb 2017 09:59:29 +0000 (09:59 +0000)]
Revert "[SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong"
This reverts commit
d83c81ee6a8dea662808ac22b396d1bb0595c89d.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295951
91177308-0d34-0410-b5e6-
96231b3b80d8
Alexey Bataev [Thu, 23 Feb 2017 09:40:38 +0000 (09:40 +0000)]
[SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong
result
Summary:
If the same value is used several times as an extra value, SLP
vectorizer takes it into account only once instead of actual number of
using.
For example:
```
int val = 1;
for (int y = 0; y < 8; y++) {
for (int x = 0; x < 8; x++) {
val = val + input[y * 8 + x] + 3;
}
}
```
We have 2 extra rguments: `1` - initial value of horizontal reduction
and `3`, which is added 8*8 times to the reduction. Before the patch we
added `1` to the reduction value and added once `3`, though it must be
added 64 times.
Reviewers: mkuper, mzolotukhin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295949
91177308-0d34-0410-b5e6-
96231b3b80d8
Ayman Musa [Thu, 23 Feb 2017 08:13:36 +0000 (08:13 +0000)]
[X86][AVX512] Remove VCVTSS2SDZ & VCVTSD2SSZ from memory folding tables as they introduce new read dependency when folding.
(Quick fix to buildbot fail).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295946
91177308-0d34-0410-b5e6-
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Ayman Musa [Thu, 23 Feb 2017 07:24:21 +0000 (07:24 +0000)]
[X86][AVX512] Change VCVTSS2SD and VCVTSD2SS node types to keep consistency between VEX/EVEX versions.
AVX versions of the converts work on f32/f64 types, while AVX512 version work on vectors.
Differential Revision: https://reviews.llvm.org/D29988
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295940
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Matt Arsenault [Thu, 23 Feb 2017 03:58:53 +0000 (03:58 +0000)]
LoadStoreVectorizer: Split even sized illegal chains properly
Implement isLegalToVectorizeLoadChain for AMDGPU to avoid
producing private address spaces accesses that will need to be
split up later. This was doing the wrong thing in the case
where the queried chain was an even number of elements.
A possible <4 x i32> store was being split into
store <2 x i32>
store i32
store i32
rather than
store <2 x i32>
store <2 x i32>
when legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295933
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Craig Topper [Thu, 23 Feb 2017 03:22:14 +0000 (03:22 +0000)]
[X86][IR] In AutoUpgrade, check explicitly for xop.vpcmov and xop.vpcmov.256 instead of anything starting with xop.vpcmov
There were some older intrinsics that only existed for less than a month in 2012 that still exist in some out of tree test files that start with this string, but aren't able to be handled by the current upgrade code and fire an assert. Now we'll go back to treating them as not intrinsics at all and just passing them through to output.
Fixes PR32041, sort of.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295930
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Matt Arsenault [Thu, 23 Feb 2017 03:16:44 +0000 (03:16 +0000)]
TargetOptions: Fix not accounting for NoSignedZerosFPMath in ==
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295928
91177308-0d34-0410-b5e6-
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Matthias Braun [Thu, 23 Feb 2017 01:09:01 +0000 (01:09 +0000)]
Test if we can use raw strings on all platforms compiling LLVM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295917
91177308-0d34-0410-b5e6-
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Eli Friedman [Thu, 23 Feb 2017 00:48:18 +0000 (00:48 +0000)]
Explicitly state the behavior of inbounds with a null pointer.
See https://llvm.org/bugs/show_bug.cgi?id=31439; this reflects LLVM's
behavior in practice, and should be compatible with C/C++ rules.
Differential Revision: https://reviews.llvm.org/D28026
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295916
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Matt Arsenault [Thu, 23 Feb 2017 00:44:03 +0000 (00:44 +0000)]
AMDGPU: Replace disabled exp inputs with undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295914
91177308-0d34-0410-b5e6-
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Matt Arsenault [Thu, 23 Feb 2017 00:23:43 +0000 (00:23 +0000)]
AMDGPU: Add another BFE pattern
This is the pattern that falls out of the instruction's
definition if offset == 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295912
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Matt Arsenault [Wed, 22 Feb 2017 23:53:37 +0000 (23:53 +0000)]
AMDGPU: Use clamp with f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295908
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Michael Kuperstein [Wed, 22 Feb 2017 23:35:13 +0000 (23:35 +0000)]
Revert r295868 because it breaks a different SLP lit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295906
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Matt Arsenault [Wed, 22 Feb 2017 23:27:53 +0000 (23:27 +0000)]
AMDGPU: Fold FP clamp as modifier bit
The manual is unclear on the details of this. It's not
clear to me if denormals are not allowed with clamp,
or if that is only omod. Not allowing denorms for
fp16 or fp64 isn't useful so I also question if that
is really a restriction. Same with whether this is valid
without IEEE mode enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295905
91177308-0d34-0410-b5e6-
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Wei Ding [Wed, 22 Feb 2017 23:22:19 +0000 (23:22 +0000)]
AMDGPU : Update TrapCode based on Trap Handler ABI.
Differential Revision: http://reviews.llvm.org/D30232
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295904
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Justin Bogner [Wed, 22 Feb 2017 23:12:36 +0000 (23:12 +0000)]
[libFuzzer] Update traces hooks test after r293741
This test now passes on darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295902
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Justin Bogner [Wed, 22 Feb 2017 23:05:17 +0000 (23:05 +0000)]
[libFuzzer] Mark a test that infinite loops as unsupported
We need to investigate this, but for now it just causes too much
headache when trying to run these tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295900
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Matt Arsenault [Wed, 22 Feb 2017 23:04:58 +0000 (23:04 +0000)]
AMDGPU: Add replacement bfe intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295899
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Sanjay Patel [Wed, 22 Feb 2017 23:01:12 +0000 (23:01 +0000)]
[InstCombine] don't try SimplifyDemandedInstructionBits from add/sub because it's slow and unlikely to succeed
Notably, no regression tests change when we remove these calls, and these are expensive calls.
The motivation comes from the general acknowledgement that the compiler is getting slower:
http://lists.llvm.org/pipermail/llvm-dev/2017-January/109188.html
http://lists.llvm.org/pipermail/llvm-dev/2016-December/108279.html
And specifically the test case attached to PR32037:
https://bugs.llvm.org//show_bug.cgi?id=32037
Profiling the middle-end (opt) part of the compile:
$ ./opt -O2 row_common.bc -o /dev/null
...visitAdd and visitSub are near the top of the instcombine list, and the calls to SimplifyDemandedInstructionBits()
are high within each of those. Those calls account for 1%+ of the opt time in either debug or release profiles. And
that's the rough win I see from this patch when testing opt built release from r295864 on an iMac with Haswell 4GHz
(model 4790K).
It seems unlikely that we'd be able to eliminate add/sub or change their operands given that add/sub normally affect
all bits, and the PR32037 example shows no IR difference after this change using -O2.
Also worth noting - the code comment in visitAdd:
// This handles stuff like (X & 254)+1 -> (X&254)|1
...isn't true. That transform is handled later with a call to haveNoCommonBitsSet().
Differential Revision: https://reviews.llvm.org/D30270
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295898
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Dylan McKay [Wed, 22 Feb 2017 22:41:13 +0000 (22:41 +0000)]
[AVR] Disable integrated assembler for a few tests
Fixes the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295895
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Eugene Zelenko [Wed, 22 Feb 2017 22:32:51 +0000 (22:32 +0000)]
[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295893
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Krzysztof Parzyszek [Wed, 22 Feb 2017 22:28:47 +0000 (22:28 +0000)]
[Hexagon] Implement @llvm.readcyclecounter()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295892
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Matt Arsenault [Wed, 22 Feb 2017 22:23:32 +0000 (22:23 +0000)]
AMDGPU: Don't add emergency stack slot if all spills are SGPR->VGPR
This should avoid reporting any stack needs to be allocated in the
case where no stack is truly used. An unused stack slot is still
left around in other cases where there are real stack objects
but no spilling occurs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295891
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Daniel Berlin [Wed, 22 Feb 2017 22:20:58 +0000 (22:20 +0000)]
PredicateInfo: Support switch statements
Summary:
Depends on D29606 and D29682
Makes us pass GVN's edge.ll (we also will pass a few other testcases
they just need cleaning up).
Thoughts on the Predicate* hiearchy of classes especially welcome :)
(it's not clear to me how best to organize it, and currently, the getBlock* seems ... uglier than maybe wasting a field somewhere or something).
Reviewers: davide
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29747
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295889
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Daniel Berlin [Wed, 22 Feb 2017 22:20:53 +0000 (22:20 +0000)]
Add pair conversion functions to BasicBlockEdge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295888
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Daniel Berlin [Wed, 22 Feb 2017 22:19:55 +0000 (22:19 +0000)]
Move updating functions to MemorySSAUpdater.
Add updater to passes that now need it.
Move around code in MemorySSA to expose needed functions.
Summary: Mostly cleanup
Reviewers: george.burgess.iv
Subscribers: llvm-commits, Prazek
Differential Revision: https://reviews.llvm.org/D30221
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295887
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Matthew Simpson [Wed, 22 Feb 2017 21:56:02 +0000 (21:56 +0000)]
[LV] Update floating-point induction test checks (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295885
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Wei Mi [Wed, 22 Feb 2017 21:47:08 +0000 (21:47 +0000)]
[LSR] Canonicalize formula and put recursive Reg related with current loop in ScaledReg.
After rL294814, LSR formula can have multiple SCEVAddRecExprs inside of its BaseRegs.
Previous canonicalization will swap the first SCEVAddRecExpr in BaseRegs with ScaledReg.
But now we want to swap the SCEVAddRecExpr Reg related with current loop with ScaledReg.
Otherwise, we may generate code like this: RegA + lsr.iv + RegB, where loop invariant
parts RegA and RegB are not grouped together and cannot be promoted outside of loop.
With this patch, it will ensure lsr.iv to be generated later in the expr:
RegA + RegB + lsr.iv, so that RegA + RegB can be promoted outside of loop.
Differential Revision: https://reviews.llvm.org/D26781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295884
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Krzysztof Parzyszek [Wed, 22 Feb 2017 21:42:15 +0000 (21:42 +0000)]
[RDF] Support for partial structural aliases in RegisterAggr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295883
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Zachary Turner [Wed, 22 Feb 2017 21:24:06 +0000 (21:24 +0000)]
[Support] Re-add the special OSX flags on mmap.
The problem appears to be that these flags can only be used
when mapping a file for read-only, not for readwrite. So
we do that here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295880
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Krzysztof Parzyszek [Wed, 22 Feb 2017 21:23:09 +0000 (21:23 +0000)]
[Hexagon] Add intrinsics for masked vector stores
Patch by Harsha Jagasia.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295879
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Matt Arsenault [Wed, 22 Feb 2017 21:16:41 +0000 (21:16 +0000)]
AMDGPU: Don't look at chain users when adjusting writemask
Fixes not adjusting using new intrinsics with chains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295878
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Matt Arsenault [Wed, 22 Feb 2017 21:05:25 +0000 (21:05 +0000)]
AMDGPU: Always allocate emergency stack slot at offset 0
This allows us to ensure that 0 is never a valid pointer
to a user object, and ensures that the offset is always legal
without needing a register to access it. This comes at the cost
of usable offsets and wasted stack space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295877
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Derek Schuff [Wed, 22 Feb 2017 21:01:17 +0000 (21:01 +0000)]
[WebAssembly] Update llvm-readobj tests for switch to version 0x1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295875
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Matt Arsenault [Wed, 22 Feb 2017 20:37:12 +0000 (20:37 +0000)]
AMDGPU: Change exp with compr bit printing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295873
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Wei Ding [Wed, 22 Feb 2017 20:29:22 +0000 (20:29 +0000)]
Revert "AMDGPU : Update TrapCode based on Trap Handler ABI."
This reverts commit r295867.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295871
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Dan Gohman [Wed, 22 Feb 2017 20:24:16 +0000 (20:24 +0000)]
[WebAssembly] Update llvm-objdump tests for the new wasm version number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295869
91177308-0d34-0410-b5e6-
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Alexey Bataev [Wed, 22 Feb 2017 20:06:40 +0000 (20:06 +0000)]
[SLP] Fix for PR32036: Vectorized horizontal reduction returning wrong result
Summary:
If the same value is used several times as an extra value, SLP
vectorizer takes it into account only once instead of actual number of
using.
For example:
```
int val = 1;
for (int y = 0; y < 8; y++) {
for (int x = 0; x < 8; x++) {
val = val + input[y * 8 + x] + 3;
}
}
```
We have 2 extra rguments: `1` - initial value of horizontal reduction
and `3`, which is added 8*8 times to the reduction. Before the patch we
added `1` to the reduction value and added once `3`, though it must be
added 64 times.
Reviewers: mkuper, mzolotukhin
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30262
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295868
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Wei Ding [Wed, 22 Feb 2017 20:05:06 +0000 (20:05 +0000)]
AMDGPU : Update TrapCode based on Trap Handler ABI.
Differential Revision: http://reviews.llvm.org/D30232
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295867
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Rafael Espindola [Wed, 22 Feb 2017 19:42:14 +0000 (19:42 +0000)]
Move llvm_unreachable out of switch.
This should make gcc happy and still produce a clang warning if we add
another value to the enum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295865
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Matthias Braun [Wed, 22 Feb 2017 19:16:33 +0000 (19:16 +0000)]
Bring back 2>&1 redirection for this test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295864
91177308-0d34-0410-b5e6-
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Geoff Berry [Wed, 22 Feb 2017 19:10:45 +0000 (19:10 +0000)]
[AArch64] Extend AArch64RedundantCopyElimination to do simple copy propagation.
Summary:
Extend AArch64RedundantCopyElimination to catch cases where the register
that is known to be zero is COPY'd in the predecessor block. Before
this change, this pass would catch cases like:
CBZW %W0, <BB#1>
BB#1:
%W0 = COPY %WZR // removed
After this change, cases like the one below are also caught:
%W0 = COPY %W1
CBZW %W1, <BB#1>
BB#1:
%W0 = COPY %WZR // removed
This change results in a 4% increase in static copies removed by this
pass when compiling the llvm test-suite. It also fixes regressions
caused by doing post-RA copy propagation (a separate change to be put up
for review shortly).
Reviewers: junbuml, mcrosier, t.p.northover, qcolombet, MatzeB
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: https://reviews.llvm.org/D30113
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295863
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Matthew Simpson [Wed, 22 Feb 2017 19:09:38 +0000 (19:09 +0000)]
[LV] Add scalar floating-point induction test (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295862
91177308-0d34-0410-b5e6-
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Davide Italiano [Wed, 22 Feb 2017 18:53:38 +0000 (18:53 +0000)]
[ModuleSummaryAnalysis] Don't crash when referencing unnamed globals.
Instead, just be conservative as these are unfrequent enough. Thanks
to Peter Collingbourne for the discussion about this on IRC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295861
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Dan Gohman [Wed, 22 Feb 2017 18:50:20 +0000 (18:50 +0000)]
[WebAssembly] Implement the wasm binary container header.
Also, update the version number to 0x1, which is what engines are now
expecting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295860
91177308-0d34-0410-b5e6-
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Matthias Braun [Wed, 22 Feb 2017 18:47:41 +0000 (18:47 +0000)]
MIRTests: Remove unnecessary 2>&1 redirection
llc mir output goes to stdout nowadays, so the 2>&1 is not necessary
anymore for most tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295859
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Karl-Johan Karlsson [Wed, 22 Feb 2017 18:37:36 +0000 (18:37 +0000)]
[LoopVectorize] Added address space check when analysing interleaved accesses
Prevent memory objects of different address spaces to be part of
the same load/store groups when analysing interleaved accesses.
This is fixing pr31900.
Reviewers: HaoLiu, mssimpso, mkuper
Reviewed By: mssimpso, mkuper
Subscribers: llvm-commits, efriedma, mzolotukhin
Differential Revision: https://reviews.llvm.org/D29717
This reverts r295042 (re-applies r295038) with an additional fix for the
buildbot problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295858
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Dan Gohman [Wed, 22 Feb 2017 18:34:16 +0000 (18:34 +0000)]
[WebAssembly] Define a table of function signatures for runtime library calls.
LLVM CodeGen emits references to external symbols that are never declared in
LLVM IR level, so they have no declared signature. However, WebAssembly requires
all functions be declared with signatures. This patch adds a table for providing
signatures for known runtime libcalls that will be used in subsequent patches to
emit declarations for such functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295857
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Krzysztof Parzyszek [Wed, 22 Feb 2017 18:29:16 +0000 (18:29 +0000)]
[RDF] Skip undef uses when calculating kill flags
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295856
91177308-0d34-0410-b5e6-
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Krzysztof Parzyszek [Wed, 22 Feb 2017 18:27:36 +0000 (18:27 +0000)]
[RDF] Only access block live-ins when tracking liveness
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295855
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Michal Gorny [Wed, 22 Feb 2017 18:09:15 +0000 (18:09 +0000)]
[Support] Provide linux/magic.h fallback for older kernels
The function for distinguishing local and remote files added in r295768
unconditionally uses linux/magic.h header to provide necessary
filesystem magic numbers. However, in kernel headers predating 2.6.18
the magic numbers are spread throughout multiple include files.
Furthermore, LLVM did not require kernel headers being installed so far.
To increase the portability across different versions of Linux kernel
and different Linux systems, add CMake header checks for linux/magic.h
and -- if it is missing -- the linux/nfs_fs.h and linux/smb.h headers
which contained the numbers previously.
Furthermore, since the numbers are static and the feature does not seem
critical enough to make LLVM require kernel headers at all, add fallback
constants for the case when none of the necessary headers is available.
Differential Revision: https://reviews.llvm.org/D30261
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295854
91177308-0d34-0410-b5e6-
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Alexey Bataev [Wed, 22 Feb 2017 17:47:28 +0000 (17:47 +0000)]
[SLP] Test with extra argument used several times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295853
91177308-0d34-0410-b5e6-
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Dehao Chen [Wed, 22 Feb 2017 17:27:21 +0000 (17:27 +0000)]
Fix an obvious bug in SampleProfileReaderGCC.
Summary: The CallTargetProfile should be added to FProfile to be consistent with other profile readers.
Reviewers: dnovillo, davidxl
Reviewed By: davidxl
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D30233
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295852
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