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Gurchetan Singh [Fri, 28 Jul 2017 03:47:51 +0000 (20:47 -0700)]
st/dri: change dri_extensions to dri_helpers
These files provide helper structs and functions for dri2.c and drisw.c,
and name change better conveys that.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Jason Ekstrand [Thu, 3 Aug 2017 16:48:55 +0000 (09:48 -0700)]
i965/miptree: Set supports_fast_clear = false in make_shareable
The make_shareable function deletes the aux buffer and then whacks
aux_usage to ISL_AUX_USAGE_NONE but not unsetting supports_fast_clear.
Since we only look at supports_fast_clear to decide whether or not to do
fast clears, this was causing assertion failures.
Reported-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101925
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Jason Ekstrand [Wed, 2 Aug 2017 18:50:12 +0000 (11:50 -0700)]
i965/miptree: Rework create flags
The only one of the three remaining flags that has anything whatsoever
to do with layout is TILING_NONE. This commit renames them to
MIPTREE_CREATE_*, documents the meaning of each flag, and makes the
create functions take an actual enum type so GDB will print them nicely.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 2 Aug 2017 18:28:02 +0000 (11:28 -0700)]
i965/miptree: Delete MIPTREE_LAYOUT_TILING_(Y|ANY)
The only force tiling flag we really care about is LAYOUT_TILING_NONE.
The others don't actually do anything but add confusion.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 2 Aug 2017 18:22:34 +0000 (11:22 -0700)]
i965/miptree: Delete an unused function declaration
The implementation of brw_miptree_layout was removed in
bf24c3539e4b69.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 2 Aug 2017 18:07:36 +0000 (11:07 -0700)]
i965/miptree: Call alloc_aux in create_for_bo
Originally, I had moved it to the caller to make some things easier when
adding the CCS modifier. However, this broke DRI2 because
intel_process_dri2_buffer calls intel_miptree_create_for_bo but never
calls intel_miptree_alloc_aux. Also, in hindsight, it should be pretty
easy to make the CCS modifier stuff work even if create_for_bo allocates
the CCS when DISABLE_AUX is not set.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 2 Aug 2017 17:54:44 +0000 (10:54 -0700)]
i965/miptree: Delete MIPTREE_LAYOUT_FOR_SCANOUT
The flag hasn't affected actual surface layout for some time. The only
purpose it served was to set bo->cache_coherent = false on the BO used
to create the miptree. This is fairly silly because we can just set
that directly from the caller where it makes much more sense.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 2 Aug 2017 17:48:58 +0000 (10:48 -0700)]
i965/miptree: Delete some unused layout flags
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 2 Aug 2017 17:41:18 +0000 (10:41 -0700)]
i965/miptree: Refactor is_mcs_supported
We rename it to intel_miptree_supports_mcs and make the function
signature match intel_miptree_supports_ccs/hiz. We also move the sample
count check into the function so it returns false for single-sampled
surfaces.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 2 Aug 2017 17:37:36 +0000 (10:37 -0700)]
i965/miptree Remove layout_flags parameter form is_mcs_supported
The one caller of is_mcs_supported passes 0 in as the layout_flags
unconditionally.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 2 Aug 2017 19:18:25 +0000 (12:18 -0700)]
intel/isl: Don't align the height of the last array slice
We were calculating the total height of 2D surfaces by multiplying the
row pitch by the number of slices. This means that we actually request
slightly more space than actually needed since the padding on the last
slice is unnecessary. For tiled surfaces this is not likely to make a
difference. For linear surfaces, on the other hand, this means we may
require additional memory. In particular, this makes the i965 driver
reject EGL imports of buffers which do not have this extra padding.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Mon, 31 Jul 2017 15:33:22 +0000 (08:33 -0700)]
intel/isl: Stop padding surfaces
The docs contain a bunch of commentary about the need to pad various
surfaces out to multiples of something or other. However, all of those
requirements are about avoiding GTT errors due to missing pages when the
data port or sampler accesses slightly out-of-bounds. However, because
the kernel already fills all the empty space in our GTT with the scratch
page, we never have to worry about faulting due to OOB reads. There are
two caveats to this:
1) There is some potential for issues with caches here if extra data
ends up in a cache we don't expect due to OOB reads. However,
because we always trash the entire cache whenever we need to move
anything between cache domains, this shouldn't be an issue.
2) There is a potential issue if a surface gets placed at the very top
of the GTT by the kernel. In this case, the hardware could
potentially end up trying to read past the top of the GTT. If it
nicely wraps around at the 48-bit (or 32-bit) boundary, then this
shouldn't be an issue thanks to the scratch page. If it doesn't,
then we need to come up with something to handle it.
Up until some of the GL move to ISL, having the padding code in there
just caused us to harmlessly use a bit more memory in Vulkan. However,
now that we're using ISL sizes to validate external dma-buf images,
these padding requirements are causing us to reject otherwise valid
images due to the size of the BO being too small.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 4 Aug 2017 02:58:24 +0000 (19:58 -0700)]
anv/formats: Allow sampling on depth-only formats on gen7
We can't sample from depth-stencil formats but on gen7 but we can sample
from depth-only formats.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102024
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Cc: mesa-stable@lists.freedesktop.org
Emil Velikov [Mon, 7 Aug 2017 12:18:25 +0000 (13:18 +0100)]
docs: drop released RCs from the calendar
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 7 Aug 2017 12:14:38 +0000 (13:14 +0100)]
docs: update calendar, add news item and link release notes for 17.1.5
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Emil Velikov [Mon, 7 Aug 2017 12:09:08 +0000 (13:09 +0100)]
docs: add sha256 checksums for 17.1.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
2766ed0d45b2c3397de5cbdfa9cf7e03a0fdfb5d)
Emil Velikov [Mon, 7 Aug 2017 12:02:41 +0000 (13:02 +0100)]
docs: add release notes for 17.1.6
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
(cherry picked from commit
3d48433078cb9501c506d2a15834e8dda1a3caef)
Dave Airlie [Mon, 7 Aug 2017 06:39:41 +0000 (07:39 +0100)]
radv: fix MSAA on SI gpus.
This ports the workaround from radeonsi, that was missing in radv.
This fixes Talos rendering when MSAA is enabled on my Tahiti card.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes:
f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eleni Maria Stea [Fri, 4 Aug 2017 17:20:12 +0000 (20:20 +0300)]
docs: removed the '--with-sha1' requirement from shading.html
The configuration option --with-sha1 is no longer required for the
MESA_SHADER_READ_PATH, MESA_SHADER_DUMP_PATH environment variables
to take effect.
1- removed the "--with-sha1" sentence from docs/shading.html
2- added an extra note: that the corresponding dumped and replacement
shaders must have the same filenames for the feature to take effect.
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Dave Airlie [Fri, 4 Aug 2017 05:54:15 +0000 (06:54 +0100)]
radv: add separate fmask tile swizzle counter.
This mirrors what Marek has done for radeonsi, and uses
a separate counter to handle the fmask surface for MSAA
MRTs.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 3 Aug 2017 23:17:34 +0000 (00:17 +0100)]
radv: fix f16->f32 denorm handling for SI/CIK. (v2)
This just copies the code from the -pro shaders,
and fixes the tests on CIK.
With this CIK passes the same set of conformance
tests as VI.
Fixes:
83e58b03 (radv: flush f32->f16 conversion denormals to zero. (v2))
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Wladimir J. van der Laan [Fri, 28 Jul 2017 14:05:16 +0000 (16:05 +0200)]
etnaviv: Add support for R8_UNORM textures
R8_UNORM textures can be emulated by means of L8 and a swizzle.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Mon, 24 Jul 2017 08:28:17 +0000 (10:28 +0200)]
etnaviv: Implement ICACHE
This patch adds support for large shaders on GC3000. For example the "terrain"
glmark benchmark with a large fragment shader will work after this.
If the GPU supports ICACHE, shaders larger than the available state area will
be uploaded to a bo of their own and instructed to be loaded from memory on
demand. Small shaders will be uploaded in the usual way. This mimics the
behavior of the blob.
On GPUs that don't support ICACHE, this patch should make no difference.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Mon, 24 Jul 2017 08:28:16 +0000 (10:28 +0200)]
etnaviv: Unified uniforms support
GC3000 has changed from a separate store for VS and PS uniforms
to a single, unified one. There is backwards compatibilty functionalty,
however this does not work correctly together with ICACHE.
This patch adds explicit support, although in the simplest way possible:
the PS/VS uniforms split is still fixed and hardcoded. It should
make no difference on hardware that does not have unified uniform
memory.
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Wladimir J. van der Laan [Mon, 24 Jul 2017 08:28:15 +0000 (10:28 +0200)]
etnaviv: Update headers from rnndb
Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Ilia Mirkin [Sun, 6 Aug 2017 17:00:18 +0000 (13:00 -0400)]
fix GL_ARB_spirv_extensions name
Trivial. There is no _gl_ in there.
Bas Nieuwenhuizen [Sat, 5 Aug 2017 23:58:21 +0000 (01:58 +0200)]
radv: Use the correct channel for alpha in resolve srgb conversion.
The argument here is a bitmask, so the old code selected .xy, which
got silently truncated to .x when constructing the vec4 from components,
instead of using .w.
Fixes:
588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 5 Aug 2017 23:56:17 +0000 (01:56 +0200)]
radv: Only convert linear->srgb in compute resolves.
It justs works with the fragment shader resolve, so no need to do
a custom conversion. In fact with SRGB dest, it actually gives
wrong results.
Fixes:
69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 5 Aug 2017 23:47:09 +0000 (01:47 +0200)]
radv: Don't use SRGB format for image stores during resolve.
These seem to store very bogus results. Luckily there is some code
that converts srgb->linear already, so just making the descriptor
format UNORM should work.
Fixes:
588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Sun, 6 Aug 2017 02:51:12 +0000 (12:51 +1000)]
docs: add EXT_memory_object and EXT_memory_object_fd to relnotes
Andres Rodriguez [Wed, 12 Jul 2017 22:45:32 +0000 (18:45 -0400)]
radeonsi: enable support for EXT_memory_object
v2: fix an indentation error
v3: don't enable for r600
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:31 +0000 (18:45 -0400)]
radv: generate the same driver UUID as radeonsi
These need to match for interop compatibility queries.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:30 +0000 (18:45 -0400)]
radv: generate same device UUID as radeonsi
This is required for interop use cases. The same device must report
identical UUIDs through the GL and Vulkan APIs so that users can
identify when it is safe to perform a memory object import.
v2: use ac helpers to calculate the uuid
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:27 +0000 (18:45 -0400)]
mesa: hook up queries for NUM_TILING_TYPES and TILING_TYPES
These are just basic implementations.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Thu, 13 Jul 2017 02:04:15 +0000 (22:04 -0400)]
radeonsi: hook up device/driver UUID queries
v2: move from r600_common to radeonsi
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:25 +0000 (18:45 -0400)]
ac/gpu: add driver/device UUID query helpers
We need vulkan and gl to produce the same UUIDs. Therefore we should
keep the mechanism to compute these in a common location to guarantee
they are updated in lockstep.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:24 +0000 (18:45 -0400)]
mesa: hook up UUID queries for driver and device
v2: respective changes for new gallium interface
v3: fix UUID size asserts
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:23 +0000 (18:45 -0400)]
gallium: introduce device/driver UUID queries
v2: remove unnecessary returns
v3 (Timothy Arceri): updated trace
v4 (Timothy Arceri): actually dump the params in trace
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:22 +0000 (18:45 -0400)]
mesa: implement glGetUnsignedByte{v|i_v}
These are used by EXT_external_objects to present UUIDs for the device
and the driver.
v2 (Timothy Arceri):
- remove extra break
- use _mesa_problem() rather the _mesa_error() for unimplemented
support for value types
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:21 +0000 (18:45 -0400)]
mesa/st: expose EXT_memory_object and EXT_memory_object_fd
v2: use PIPE_CAP_MEMOBJ to guard the extension
v3 (Timothy Arceri):
- expose extensions via the cap_mappings array
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Timothy Arceri [Wed, 26 Jul 2017 06:50:44 +0000 (16:50 +1000)]
mesa: hook up (Named)BufferStorageMem api
Include no_error variants as well.
v2 (Timothy Arceri):
- reduced code churn by squashing some changes into
previous commits
v3 (Timothy Arceri):
- drop unused function declaration
v4 (Timothy Arceri):
- fix Driver function assert()
- add missing GL errors
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:18 +0000 (18:45 -0400)]
mesa/st: implement memory objects as a backend for buffer objects
Use a memory object instead of user memory.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Tue, 18 Jul 2017 03:06:18 +0000 (23:06 -0400)]
radeonsi: add basic memory object support
v2: also consider gfx9 metadata
v3: ref/unref memobj->buf
v4: add refcount comment
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:15 +0000 (18:45 -0400)]
radeonsi: factor out metadata import
Plumbing for importing memobj backed textures.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Dave Airlie [Wed, 12 Jul 2017 22:45:14 +0000 (18:45 -0400)]
mesa/st: implement memory objects as a backend for texture storage
Instead of allocating memory to back a texture, use the provided memory
object.
v2: split off extension exposure logic
v3: de-duplicate code with st_AllocTextureStorage
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:13 +0000 (18:45 -0400)]
mesa/st: factor out st_AllocTextureStorage into a helper
Plumbing for using memory objects as texture storage.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:12 +0000 (18:45 -0400)]
mesa: hook up memory object multisamples tex(ture)storage api
V2 (Timothy):
- error check memory == 0 before lookup
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:11 +0000 (18:45 -0400)]
mesa: hook up memoryobject tex(ture)storage api
V2 (Timothy Arceri):
- formating fixes
V3 (Timothy):
- error check memory == 0 before lookup
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Wed, 12 Jul 2017 22:45:10 +0000 (18:45 -0400)]
mesa/st: start adding memory object support
v2: pass dedicated flag
v3 (Timothy Arceri):
- remove unrequired _mesa_init_memory_object_functions()
call in the state tracker.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Dave Airlie [Wed, 12 Jul 2017 22:45:09 +0000 (18:45 -0400)]
gallium: introduce memory object
v2: fix comment regarding fd ownership, define pipe_memory_object
v3: remove stray return
v4 (Timothy Arceri): update trace
v5 (Timothy Arceri): actually dump the params in trace
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v3)
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:08 +0000 (18:45 -0400)]
mesa: add support for memory object parameters
V2 (Timothy Arceri):
- fix copy and paste error with error message
V3 (Timothy Arceri):
- drop the Protected field for now as its unused
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:07 +0000 (18:45 -0400)]
mesa: add support for memory object creation/import/delete
Used by EXT_external_objects and EXT_external_objects_fd
V2 (Timothy Arceri):
- Throw GL_OUT_OF_MEMORY error if CreateMemoryObjectsEXT()
fails.
- C99 tidy ups
- remove void cast (Constantine Kharlamov)
V3 (Timothy Arceri):
- rename mo -> memObj
- check that the object is not NULL before initializing
- add missing "EXT" in function error message
V4 (Timothy Arceri):
- remove checks for (memory objecy id == 0) and catch in
_mesa_lookup_memory_object() instead.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Rodriguez [Wed, 12 Jul 2017 22:45:06 +0000 (18:45 -0400)]
mapi: add EXT_external_objects and EXT_external_objects_fd
Includes implementation stubs.
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Aaron Watry [Sat, 22 Jul 2017 02:17:50 +0000 (21:17 -0500)]
clover/device: Move device_version into core and add device_clc_version
The device version is the maximum CL version that the device supports.
device_version and device_clc_version are not necessarily the same for
devices that support CL 1.0, but have a 1.1 compiler and the necessary
extensions.
Eventually, this will be based on the features/extensions of the actual
device, but for now move it a bit closer to its eventual destination.
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Jan Vesey <jan.vesely@rutgers.edu>
Dave Airlie [Fri, 4 Aug 2017 01:13:55 +0000 (02:13 +0100)]
radv: avoid GPU hangs if someone does a resolve with non-multisample src (v2)
This is a bug in the app, but I'd rather avoid hanging the GPU,
esp if someone is running in validation and it takes out their
development environment.
v2: get it right, reverse the polarity.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Emil Velikov [Tue, 1 Aug 2017 23:59:26 +0000 (00:59 +0100)]
loader: drop the [gs]et_swap_interval callbacks
Having two callbacks to manage a single int seems like an overkill.
Use a cached copy and update that when needed.
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
---
Might want to look if the dimensions dance in .query_surface ...
speaking of which close to nobody implements that ...
Emil Velikov [Thu, 3 Aug 2017 13:34:53 +0000 (14:34 +0100)]
egl/x11: don't leak xfixes_query in the error path
If we get a xfixes v1.x we'll error out, without freeing the
xfixes_query reply.
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Emil Velikov [Fri, 4 Aug 2017 16:49:08 +0000 (17:49 +0100)]
loader: rework xmlconfig dependency
Currently xmlconfig is conditionally used, only when --enable-dri is
available.
As the library has moved to src/util and has wider wisebase, this guard
is no longer correct. Strictly speaking - it wasn't since the
introduction of xmlconfig into st/nine a while ago.
Unconditionally enable xmlconfig and drop the linking. As said before
there's other users of the library, so depending on the configure
options we will get multiple definitions of said symbols.
NOTE: To avoid breaking other combinations, this commit adds the
xmlconfig link to the required places - throughout gallium and the DRI
loaders.
Cc: Aaron Watry <awatry@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Chris Wilson [Fri, 21 Jul 2017 15:36:52 +0000 (16:36 +0100)]
i965: Reduce passing 2x32b of reloc_domains to 2 bits
The kernel only cares about whether the object is to be written to or
not, only reduces (reloc.read_domains, reloc.write_domain) down to just
!!reloc.write_domain. When we use NO_RELOC, the kernel doesn't even read
those relocs and instead userspace has to pass that information in the
execobject.flags. We can simplify our reloc api by also removing the
unused read/write domains and only pass the resultant flags.
The caveat to the above are when we need to make the kernel aware that
certain objects need to take into account different work arounds.
Previously, this was done using the magic (INSTRUCTION, INSTRUCTION)
reloc domains. NO_RELOC requires this to be passed in the execobject
flags as well, and now we push that up the callstack.
The API is more compact, more expressive of what happens underneath, but
unfortunately requires more knowledge of the system at the point of use.
Conversely it also means that knowledge is specific and not generally
applied and so not overused.
text data bss dec hex filename
8502991 356912 424944
9284847 8dacef lib/i965_dri.so (before)
8500455 356912 424944
9282311 8da307 lib/i965_dri.so (after)
v2: (by Ken) Rebase.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Thu, 3 Aug 2017 07:03:15 +0000 (00:03 -0700)]
i965: Convert reloc.target_handle into an index for I915_EXEC_HANDLE_LUT
Based on a patch by Chris Wilson (who also wrote this commit message).
Passing the index of the target buffer via the reloc.target_handle is
marginally more efficient for the kernel (it can avoid some allocations,
and can use a direct lookup rather than a hash or search). It is also
useful for ourselves as we can use the index into our exec_bos for other
tasks.
v2: Only enable HANDLE_LUT if we can use BATCH_FIRST and thereby avoid
a post-processing loop to fixup the relocations.
v3: Move kernel probing from context creation to screen init.
Use batch->use_exec_lut as it more descriptive of what's going on (Daniel)
v4: Kernel features already exists, use it for BATCH_FIRST
Rename locals to preserve current flavouring
v5: Squash in "always insert batch bo first"
v6: (by Ken) Split out BATCH_FIRST from HANDLE_LUT.
Kenneth Graunke [Thu, 3 Aug 2017 07:01:14 +0000 (00:01 -0700)]
i965: Use a C99 initializer for new validation list entries.
More succinct - we can skip a bunch of = 0 lines.
Extracted from a patch by Chris Wilson.
Kenneth Graunke [Thu, 3 Aug 2017 06:58:07 +0000 (23:58 -0700)]
i965: Simplify some bo != batch->bo special cases.
Extracted from a patch by Chris Wilson.
Now that the batch is always at the front of the validation list,
we don't need to special case it - the usual "go find an existing BO"
code will work just fine.
Kenneth Graunke [Thu, 3 Aug 2017 06:40:50 +0000 (23:40 -0700)]
i965: Use I915_EXEC_BATCH_FIRST when available.
This will make it easier to use I915_EXEC_HANDLE_LUT.
Based on a patch by Chris Wilson.
Chris Wilson [Fri, 21 Jul 2017 15:36:49 +0000 (16:36 +0100)]
i965: Move add_exec_bo()
To avoid a forward declaration in the next patch, move the definition of
add_exec_bo() earlier.
v2: (by Ken) redo move.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Fri, 21 Jul 2017 15:36:48 +0000 (16:36 +0100)]
i965: Ignore reloc read/write domains
Since before the kernel supported I915_EXEC_NO_RELOC, long before our
minimum kernel requirement, the kernel unconditionally invalidated all
GPU TLBs before a batch and flushed all GPU caches after a batch. At
that moment, the only use for read/write domain was for activity
tracking, ensuring that future reads waited for the last writer and
future writes waited for all reads. This only requires a single bit in
the execbuf interface which can be supplied via the NO_RELOC interface,
making the use of relocation domains entirely redundant.
Trimming the excess writes into the array allows the compiler to be much
more frugal:
text data bss dec hex filename
8493790 357184 424944
9275918 8d8a0e i965_dri.baseline
8493758 357184 424944
9275886 8d89ee i965_dri.so
(This text improvement really does come from dropping domains, not from
the new use of C99 initializers.)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Fri, 21 Jul 2017 15:36:47 +0000 (16:36 +0100)]
i965: Use I915_EXEC_NO_RELOC
If we correctly fill the batch with the right relocation value, and that
matches the expected location of the object, we can then tell the kernel
it can forgo checking each individual relocation by only checking
whether the object moved.
v2: Rebase to apply ahead of I915_EXEC_HANDLE_LUT
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Thu, 3 Aug 2017 00:39:56 +0000 (17:39 -0700)]
i965: Initialize flags to 0 and |= in new flags.
This makes it a bit easier to add new unconditional flags.
Kenneth Graunke [Thu, 3 Aug 2017 00:06:18 +0000 (17:06 -0700)]
i965: Make add_exec_bo return the validation list index.
This will be useful for I915_EXEC_HANDLE_LUT and I915_EXEC_NO_RELOC.
Chris Wilson [Fri, 21 Jul 2017 15:36:46 +0000 (16:36 +0100)]
i965: Track last location of bo used for the batch
Borrow a trick from anv, and use the last known index for the bo to skip
a search of the batch->exec_bo when adding a new relocation. In defence
against the bo being used in multiple batches simultaneously, we check
that this slot exists and points back to us.
v2: Also update brw_batch_references()
v3: Reset bo->index on creation (Daniel)
v4: Improved explanation of bo->index (Kenneth)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Chris Wilson [Fri, 21 Jul 2017 15:36:45 +0000 (16:36 +0100)]
i965: Always use the pre-computed offset for the relocation entry
We must be careful to only compute the address once based on the
per-context information (rather than accessing the unlocked global
bo->offset64) so that the value in the batch does match the
reloc.presumed_offset we declare to the kernel. Otherwise, highly
unlikely, but we may see GPU hangs in multithreaded users.
The only real complication here is isl_surf_fill_state() which needs to
adjust the reloc.delta to both general a tile offset and to encode state
into the lower 12 bits.
(Rebased on ISL changes by Ken.)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 2 Aug 2017 23:52:39 +0000 (16:52 -0700)]
i965: Make brw_emit_reloc assert that the target BO is non-NULL.
You need an actual BO to emit a relocation to it.
Suggested by me, authored by Chris, split out of a larger patch.
Emil Velikov [Wed, 2 Aug 2017 18:39:05 +0000 (19:39 +0100)]
configure.ac: drop manual detection of expat header/library
Use the .pc file, as provided by version prior 2.1.0 onward and dropping
the manual header/library check.
Version 2.1.0 was released back in Mar 2012 and all major distributions
use it.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (IRC)
Emil Velikov [Wed, 2 Aug 2017 18:39:04 +0000 (19:39 +0100)]
configure.ac: unconditionally check for expat
Earlier commits moved the xmlconfig library to a wider userbase.
Thus having the check within --enable-dri is insufficient.
Upon closer look, nine needed it from it's early days -
948e6c52282
("nine: Add drirc options (v2)")
Fixes:
601093f95ddf ("xmlconfig: move into src/util")
Cc: Axel Davy <axel.davy@ens.fr>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com> (IRC)
Mauro Rossi [Thu, 3 Aug 2017 00:55:46 +0000 (02:55 +0200)]
android: radeonsi: add nir include paths
Android build changes to avoid the following building error:
target C: libmesa_pipe_radeonsi <= external/mesa/src/gallium/drivers/radeonsi/si_pipe.c
...
In file included from external/mesa/src/gallium/drivers/radeonsi/si_pipe.c:38:
external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found
^
1 error generated.
Fixes:
da62a31c5b "radeonsi: add nir include paths"
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Chris Wilson [Sat, 22 Jul 2017 09:28:14 +0000 (10:28 +0100)]
i965: Prefer using streaming reads from WC mmaps
For buffer objects, where we primarily expect to be writing to them and
so already have a WC mmap (for !llc access) reusing the existing mmap
and keeping the buffer out of the CPU cache seems preferable.
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Matt Turner <mattst88@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Nicolai Hähnle [Thu, 3 Aug 2017 13:07:55 +0000 (15:07 +0200)]
pipe-loader: fix swrast probing
Missed updating this caller of pipe_loader_find_module.
Fixes:
0d7d60b7ea ("pipe-loader: pass only the driver_name to pipe_loader_find_module")
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 3 Aug 2017 13:02:09 +0000 (15:02 +0200)]
pipe-loader: remove config from pipe_loader_create_screen
The config passed into the screen should be independent from the state
tracker, because at least in the case of radeonsi, the screen structure
can be shared between different state trackers.
Incidentally, this also fixes crashes that were recently introduced.
Fixes:
a35a9e7c ("gallium: add driconf options to pipe_screen_config")
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 3 Aug 2017 13:01:09 +0000 (15:01 +0200)]
gallium: get rid of pipe_screen_config::flags
They were set only by the DRI state tracker, which is problematic
when radeonsi is used with different state trackers in the same
process.
Also, we don't need them anymore.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 3 Aug 2017 12:53:41 +0000 (14:53 +0200)]
radeonsi: set drirc compiler options before calling common screen init
Also, access the options directly, allowing us to get rid of the
PIPE_SCREEN_xxx flags.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Juan A. Suarez Romero [Thu, 3 Aug 2017 10:44:59 +0000 (12:44 +0200)]
util: Makefile.am: add merge_driinfo.py in extra dist
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Juan A. Suarez Romero [Thu, 3 Aug 2017 10:22:24 +0000 (12:22 +0200)]
radeonsi: Makefile.sources: include driinfo_radeonsi.h
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Juan A. Suarez Romero [Thu, 3 Aug 2017 09:33:41 +0000 (11:33 +0200)]
anv: Makefile.vulkan.am: ICD json files are now generated with python
Commit
0ab04ba979b7 (anv: Use python to generate ICD json files) changed
the way ICD json files are created.
Remove the old .in files from extra dist, and add the python script.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Dave Airlie [Fri, 4 Aug 2017 06:12:03 +0000 (07:12 +0100)]
radv: also fix texture image descriptors for mipmap tile swizzle
This fixes the image descriptors for mipmapped tile swizzle
Fixes:
2b7e8556 (ac/surface: enable tile swizzle for mipmapped textures)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 4 Aug 2017 05:43:26 +0000 (06:43 +0100)]
radv: fix tile swizzle regression on mipmaps.
When Marek enabled mipmapped swizzle, radv didn't
have the code in place to handle it. This fixes the
regression.
I'll look more into GFX9 once I have a vega card (soon).
Fixes:
2b7e8556 (ac/surface: enable tile swizzle for mipmapped textures)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Michel Dänzer [Fri, 4 Aug 2017 03:02:38 +0000 (12:02 +0900)]
pipe-loader: Add driver build directory for si_driinfo.h include path
Fixes out-of-tree build failure:
.../src/gallium/targets/pipe-loader/pipe_radeonsi.c: In function ‘drm_configuration’:
.../src/gallium/targets/pipe-loader/pipe_radeonsi.c:38:33: fatal error: radeonsi/si_driinfo.h: No such file or directory
#include "radeonsi/si_driinfo.h"
^
compilation terminated.
Makefile:994: recipe for target 'pipe_radeonsi.lo' failed
make[4]: *** [pipe_radeonsi.lo] Error 1
Trivial.
Fixes:
0f8c5de8690e7c ("radeonsi: prepare for driver-specific driconf
options")
Jan Vesely [Thu, 3 Aug 2017 21:26:07 +0000 (17:26 -0400)]
clover: Fix build after llvm r309911
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Marek Olšák [Fri, 28 Jul 2017 23:35:46 +0000 (01:35 +0200)]
radeonsi: program tile swizzle for color and FMASK surfaces for GFX & SDMA
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 29 Jul 2017 15:39:06 +0000 (17:39 +0200)]
radeonsi: if FMASK is disabled, set CB_COLORi_FMASK = CB_COLORi_BASE properly
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Jul 2017 23:18:02 +0000 (01:18 +0200)]
gallium/radeon: reallocate textures with non-zero tile_swizzle on export
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Jul 2017 23:14:09 +0000 (01:14 +0200)]
winsys/amdgpu: enable computation of tile swizzle
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 29 Jul 2017 15:19:01 +0000 (17:19 +0200)]
ac/surface: align DCC size for surfaces that use tile swizzle
Note that dcc_alignment = pipe_interleave_bytes * num_pipes * num_banks,
which is greater than the previous open-coded alignment.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Mon, 31 Jul 2017 22:12:30 +0000 (00:12 +0200)]
ac/surface: limit tile swizzle to non-mipmaps on SI
Mipmapping with tile swizzle doesn't work.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 29 Jul 2017 01:15:27 +0000 (03:15 +0200)]
ac/surface: enable tile swizzle for mipmapped textures
The tile swizzle computation was done after the whole miptree was computed,
but that was too late, because at that point AddrSurfInfoOut contained
information about the smallest miplevel, which is never 2D-tiled.
The correct way is to do the computation before the second level is computed.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Jul 2017 21:53:19 +0000 (23:53 +0200)]
ac/surface: set structure size and handle errors for AddrComputeBaseSwizzle
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Jul 2017 21:08:10 +0000 (23:08 +0200)]
ac/surface: increment surf_index only when tile swizzle is allowed
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Jul 2017 21:05:38 +0000 (23:05 +0200)]
ac/surface: compute tile swizzle only when it's allowed
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Jul 2017 21:01:10 +0000 (23:01 +0200)]
ac/surface: add RADEON_SURF_SHAREABLE
Shareable textures won't use tile swizzle.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Jul 2017 19:44:47 +0000 (21:44 +0200)]
ac/surface: remove RADEON_SURF_HAS_TILE_MODE_INDEX
it's useless
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 28 Jul 2017 19:34:02 +0000 (21:34 +0200)]
ac/surface: move tile_swizzle to ac_surface and document it
Gfx9 will use it too.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Brian Paul [Wed, 2 Aug 2017 03:28:25 +0000 (21:28 -0600)]
st/mesa: fix handling of NumSamples=1 (v2)
In Mesa we use the convention that if gl_renderbuffer::NumSamples
or gl_texture_image::NumSamples is zero, it's a non-MSAA surface.
Otherwise, it's an MSAA surface. But in gallium nr_samples=1 is a
non-MSAA surface.
Before, if the user called glRenderbufferStorageMultisample() or
glTexImage2DMultisample() with samples=1 we skipped the search for the
next higher number of supported samples and asked the gallium driver to
create a surface with nr_samples=1. So we got a non-MSAA surface.
This failed to meet the expection of the user making those calls.
This patch changes the sample count checks in st_AllocTextureStorage()
and st_renderbuffer_alloc_storage() to test for samples > 0 instead of > 1.
And we now start querying for MSAA support at samples=2 since gallium has
no concept of a 1x MSAA surface.
A specific example of this problem is the Piglit arb_framebuffer_srgb-blit
test. It calls glRenderbufferStorageMultisample() with samples=1 to
request an MSAA renderbuffer with the minimum supported number of MSAA
samples. Instead of creating a 4x or 8x, etc. MSAA surface, we wound up
creating a non-MSAA surface.
Finally, add a comment on the gl_renderbuffer::NumSamples field.
There is one piglit regression with the VMware driver:
ext_framebuffer_multisample-blit-mismatched-formats fails because
now we're actually creating 4x MSAA surfaces (the requested sample
count is 1) and we're hitting some sort of bug in the blitter code. That
will have to be fixed separately. Other drivers may find regressions
too now that MSAA surfaces are really being created.
v2: start quering for MSAA support with samples=2 instead of 1.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>