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Simon Pilgrim [Wed, 9 Jan 2019 12:34:10 +0000 (12:34 +0000)]
[X86] Add extra test coverage for combining shuffles to PACKSS/PACKUS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350707
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Diogo N. Sampaio [Wed, 9 Jan 2019 11:24:15 +0000 (11:24 +0000)]
[AArch64] Move feature predctrl to predres
Follow up patch of rL350385, for adding predres
command line option. This patch renames the
feature as to keep it aligned with the option
passed by/to clang
Differential Revision: https://reviews.llvm.org/D56484
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350702
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Simon Pilgrim [Wed, 9 Jan 2019 11:18:49 +0000 (11:18 +0000)]
[X86] Fix gcc7 -Wunused-but-set-variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350701
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Alexander Kornienko [Wed, 9 Jan 2019 10:49:44 +0000 (10:49 +0000)]
Make the write_cmake_config.py script python3-compatible
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350700
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David Stenberg [Wed, 9 Jan 2019 09:58:59 +0000 (09:58 +0000)]
[DebugInfo] Omit location list entries with empty ranges
Summary:
This fixes PR39710. In that case we emitted a location list looking like
this:
.Ldebug_loc0:
.quad .Lfunc_begin0-.Lfunc_begin0
.quad .Lfunc_begin0-.Lfunc_begin0
.short 1 # Loc expr size
.byte 85 # DW_OP_reg5
.quad .Lfunc_begin0-.Lfunc_begin0
.quad .Lfunc_end0-.Lfunc_begin0
.short 1 # Loc expr size
.byte 85 # super-register DW_OP_reg5
.quad 0
.quad 0
As seen, the first entry's beginning and ending addresses evalute to 0,
which meant that the entry inadvertently became an "end of list" entry,
resulting in the location list ending sooner than expected.
To fix this, omit all entries with empty ranges. Location list entries
with empty ranges do not have any effect, as specified by DWARF, so we
might as well drop them:
"A location list entry (but not a base address selection or end of list
entry) whose beginning and ending addresses are equal has no effect
because the size of the range covered by such an entry is zero."
Reviewers: davide, aprantl, dblaikie
Reviewed By: aprantl
Subscribers: javed.absar, JDevlieghere, llvm-commits
Tags: #debug-info
Differential Revision: https://reviews.llvm.org/D55919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350698
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Matt Arsenault [Wed, 9 Jan 2019 07:51:52 +0000 (07:51 +0000)]
GlobalISel: Implement fewerElements for implicit_def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350697
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Matt Arsenault [Wed, 9 Jan 2019 07:34:14 +0000 (07:34 +0000)]
GlobalISel: Implement widenScalar for implicit_def
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350695
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Max Kazantsev [Wed, 9 Jan 2019 07:28:13 +0000 (07:28 +0000)]
[IPT] Drop cache less eagerly in GVN and LoopSafetyInfo
Current strategy of dropping `InstructionPrecedenceTracking` cache is to
invalidate the entire basic block whenever we change its contents. In fact,
`InstructionPrecedenceTracking` has 2 internal strictures: `OrderedInstructions`
that is needed to be invalidated whenever the contents changes, and the map
with first special instructions in block. This second map does not need an
update if we add/remove a non-special instuction because it cannot
affect the contents of this map.
This patch changes API of `InstructionPrecedenceTracking` so that it now
accounts for reasons under which we invalidate blocks. This should lead
to much less recalculations of the map and should save us some compile time
because in practice we don't typically add/remove special instructions.
Differential Revision: https://reviews.llvm.org/D54462
Reviewed By: efriedma
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350694
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Zi Xuan Wu [Wed, 9 Jan 2019 06:12:24 +0000 (06:12 +0000)]
Revert "[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel"
This reverts commit r350685.
See compile assert in compiler-rt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350693
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Hiroshi Inoue [Wed, 9 Jan 2019 05:11:10 +0000 (05:11 +0000)]
[NFC] fix trivial typos in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350690
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Peter Collingbourne [Wed, 9 Jan 2019 04:39:29 +0000 (04:39 +0000)]
gn build: Copy file permissions from input file in configure_file() emulation.
Most significantly, this makes bin/llvm-lit executable so that it
can be run in the usual way.
Differential Revision: https://reviews.llvm.org/D56423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350688
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Craig Topper [Wed, 9 Jan 2019 04:21:12 +0000 (04:21 +0000)]
[X86] Correct the MaskVT for avx512 gather/scatter intrinsics to use the min of the number of index and data elements.
When the result type is v2i64/v2f64 and the index element size is i32, the index vector has two unused elements making the type v4i32. The mask VT should match the number of memory accesses that will be made.
This is consistent with the isel patterns used for the target independent gather/scatter intrinsic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350687
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Peter Collingbourne [Wed, 9 Jan 2019 04:05:07 +0000 (04:05 +0000)]
gn build: Fix a Python2ism in write_vcsrevision.py.
Convert the output of "git rev-parse --short HEAD" to a string before
substituting it into the output file. Without this the output file
will look like this on Python 3:
#define LLVM_REVISION "git-b'
6a4895a025f'"
Differential Revision: https://reviews.llvm.org/D56459
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350686
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Zi Xuan Wu [Wed, 9 Jan 2019 02:31:10 +0000 (02:31 +0000)]
[PowerPC] Fix assert from machine verify pass that unmatched register class about fcmp selection in fast-isel
Bad machine code: Illegal virtual register for instruction
function: TestULE
basic block: %bb.0 entry (0x1000a39b158)
instruction: %2:crrc = FCMPUD %1:vsfrc, %3:f8rc
operand 1: %1:vsfrc
Fix assert about missing match between fcmp instruction and register class.
We should use vsx related cmp instruction xvcmpudp instead of fcmpu when vsx is opened.
add -verifymachineinstrs option into related test cases to enable the verify pass.
Differential Revision: https://reviews.llvm.org/D55686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350685
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Stanislav Mekhanoshin [Wed, 9 Jan 2019 02:24:22 +0000 (02:24 +0000)]
Remove check for single use in ShrinkDemandedConstant
This removes check for single use from general ShrinkDemandedConstant
to the BE because of the AArch64 regression after D56289/rL350475.
After several hours of experiments I did not come up with a testcase
failing on any other targets if check is not performed.
Moreover, direct call to ShrinkDemandedConstant is not really needed
and superceed by SimplifyDemandedBits.
Differential Revision: https://reviews.llvm.org/D56406
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350684
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Matt Arsenault [Tue, 8 Jan 2019 23:22:18 +0000 (23:22 +0000)]
RegisterCoalescer: Assume CR_Replace for SubRangeJoin
Currently it's possible for following
check on V.WriteLanes (which is not really meaningful
during SubRangeJoin) to pass for one half of the pair,
and then fall through to to one of the impossible
or unresolved states. This then fails as inconsistent
on the other half.
During the main range join, the check between V.WriteLanes
and OtherV.ValidLanes must have passed, meaning this
should be a CR_Replace.
Fixes most of the testcases in bugs 39542 and 39602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350678
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Matt Arsenault [Tue, 8 Jan 2019 23:10:47 +0000 (23:10 +0000)]
RegisterCoalescer: Defer clearing implicit_def lanes
We can't go back and recover the lanes if it turns
out the implicit_def really can't be erased.
Assume all lanes are valid if an unresolved conflict
is encountered. There aren't any tests where this
seems to matter either way, but this seems like a
safer option.
Fixes bug 39602
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350676
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Sanjay Patel [Tue, 8 Jan 2019 22:52:08 +0000 (22:52 +0000)]
[InstCombine] remove stale comments; NFC
These changed with rL350672.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350674
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Rong Xu [Tue, 8 Jan 2019 22:41:48 +0000 (22:41 +0000)]
[llvm-profdata] add value-cutoff functionality in show command
This patch improves llvm-profdata show command:
(1) add -value-cutoff=<N> option: Show only those functions whose max count
values are greater or equal to N.
(2) add -list-below-cutoff option: Only output names of functions whose max
count value are below the cutoff.
(3) formats value-profile counts and prints out percentage.
Differential Revision: https://reviews.llvm.org/D56342
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350673
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Sanjay Patel [Tue, 8 Jan 2019 22:39:55 +0000 (22:39 +0000)]
[InstCombine] canonicalize another raw IR rotate pattern to funnel shift
This is matching the equivalent of the DAG expansion,
so it should never end up with worse perf than the
original code even if the target doesn't have a rotate
instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350672
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Rong Xu [Tue, 8 Jan 2019 22:39:47 +0000 (22:39 +0000)]
[PGO] Use SourceFileName rather module name in PGOFuncName
In LTO or Thin-lto mode (though linker plugin), the module
names are of temp file names which are different for
different compilations. Using SourceFileName avoids the issue.
This should not change any functionality for current PGO as
all the current callers of getPGOFuncName() is before LTO.
Differential Revision: https://reviews.llvm.org/D56327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350671
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Rong Xu [Tue, 8 Jan 2019 22:37:12 +0000 (22:37 +0000)]
[PGO] Revert r350579 to fix commit message.
Will re-commit it using the correct commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350670
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Heejin Ahn [Tue, 8 Jan 2019 22:35:18 +0000 (22:35 +0000)]
[WebAssembly] Rename StoreResults to MemIntrinsicResults
Summary:
StoreResults pass does not optimize store instructions anymore because
store instructions don't return results values anymore. Now this pass is
used solely for memory intrinsics, so update the pass name accordingly
and fix outdated pass descriptions as well.
This patch does not change any meaningful behavior, but not marked as
NFC because it changes a comment check line in a test case.
Reviewers: dschuff
Subscribers: mgorny, sbc100, jgravelle-google, sunfiish, llvm-commits
Differential Revision: https://reviews.llvm.org/D56093
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350669
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Rong Xu [Tue, 8 Jan 2019 22:33:29 +0000 (22:33 +0000)]
[PGO] Revert r350442 to fix commit message.
Will re-commit it using the correct commit message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350667
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Evandro Menezes [Tue, 8 Jan 2019 22:29:58 +0000 (22:29 +0000)]
[AArch64] Adjust the cost model for Exynos
Improve the modeling of ALU instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350663
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Evandro Menezes [Tue, 8 Jan 2019 22:29:56 +0000 (22:29 +0000)]
[llvm-mca] Update the Exynos test cases (NFC)
Add more entropy to the test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350662
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Evandro Menezes [Tue, 8 Jan 2019 22:29:38 +0000 (22:29 +0000)]
[llvm-mca] Improve debugging (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350661
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Jorge Gorbe Moya [Tue, 8 Jan 2019 21:45:42 +0000 (21:45 +0000)]
Fix go bindings for r350647: missed a function rename
Differential Revision: https://reviews.llvm.org/D56452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350657
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Zachary Turner [Tue, 8 Jan 2019 21:05:51 +0000 (21:05 +0000)]
[llvm-undname] Add support for demangling msvc's noexcept types.
Starting in C++17, MSVC introduced a new mangling for function
parameters that are themselves noexcept functions. This patch
makes llvm-undname properly demangle them.
Patch by Zachary Henkel
Differential Revision: https://reviews.llvm.org/D55769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350656
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Zachary Turner [Tue, 8 Jan 2019 21:05:34 +0000 (21:05 +0000)]
Don't write #include "Windows/WindowsSupport.h" from the Windows dir.
This generates -Wnonportable-include-dir warnings, and doesn't need
to be there. It seems this was just checked in on accident.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350655
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Adrian Prantl [Tue, 8 Jan 2019 21:05:10 +0000 (21:05 +0000)]
Revert "Revert "Revert "Resubmit rL345008 "Split MachinePipeliner code into header and cpp files""""
This reverts commit D56084.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350654
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Adrian Prantl [Tue, 8 Jan 2019 21:05:08 +0000 (21:05 +0000)]
Revert "Work around a linker error caused by https://reviews.llvm.org/D56084."
This reverts commit r350650
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350653
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Adrian Prantl [Tue, 8 Jan 2019 20:38:22 +0000 (20:38 +0000)]
Work around a linker error caused by https://reviews.llvm.org/D56084.
This unbreaks all bots that build with -DLLVM_ENABLE_MODULES=1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350650
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Philip Pfaffe [Tue, 8 Jan 2019 19:21:57 +0000 (19:21 +0000)]
[NewPM] Port tsan
A straightforward port of tsan to the new PM, following the same path
as D55647.
Differential Revision: https://reviews.llvm.org/D56433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350647
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Sanjay Patel [Tue, 8 Jan 2019 19:15:21 +0000 (19:15 +0000)]
[x86] add tests for PR40243; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350646
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Paul Robinson [Tue, 8 Jan 2019 17:52:29 +0000 (17:52 +0000)]
Rename DIFlagFixedEnum to DIFlagEnumClass. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350641
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Anna Thomas [Tue, 8 Jan 2019 17:16:25 +0000 (17:16 +0000)]
[UnrollRuntime] Fix domTree failures in multiexit unrolling
Summary:
This fixes the IDom for exit blocks and all blocks reachable from the exit blocks, when runtime unrolling under multiexit/exiting case.
We initially had a restrictive check that the IDom is only updated when
it is the header of the loop.
However, we also need to update the IDom to the correct one when the
IDom is any block within the original loop. See added test cases (which
fail dom tree verification without the patch).
Reviewers: reames, mzolotukhin, mkazantsev, hfinkel
Reviewed by: brzycki, kuhar
Subscribers: zzheng, dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D56284
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350640
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Yonghong Song [Tue, 8 Jan 2019 16:36:06 +0000 (16:36 +0000)]
[BPF] Fix .BTF.ext reloc type assigment issue
Commit
f1db33c5c1a9 ("[BPF] Disable relocation for .BTF.ext section")
assigned relocation type R_BPF_NONE if the fixup type
is FK_Data_4 and the symbol is temporary.
The reason is we use FK_Data_4 as a fixup type
for insn offsets in .BTF.ext section.
Just checking whether the symbol is temporary is not enough.
For example, .debug_info may reference some strings whose
fixup is FK_Data_4 with a temporary symbol as well.
To truely reflect the case for .BTF.ext section,
this patch further checks that the section associateed with the symbol
must be SHF_ALLOC and SHF_EXECINSTR, i.e., in the text section.
This fixed the above-mentioned problem.
Signed-off-by: Yonghong Song <yhs@fb.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350637
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Nico Weber [Tue, 8 Jan 2019 15:19:00 +0000 (15:19 +0000)]
[gn build] Update readme
Differential Revision: https://reviews.llvm.org/D56375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350632
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Nico Weber [Tue, 8 Jan 2019 15:17:19 +0000 (15:17 +0000)]
[gn build] Make sync_source_lists_from_cmake.py check that all LLVM unittests are present
Now that the PowerPC and WebAssembly targets are added, this check passes.
Differential Revision: https://reviews.llvm.org/D56417
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350631
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Florian Hahn [Tue, 8 Jan 2019 15:16:23 +0000 (15:16 +0000)]
[MachineVerifier] Include offending register in allocatable live-in error msg.
This patch adds a convenience report() method for physical registers and
uses it to print the offending register with the 'MBB has allocatable
live-in' error.
Reviewers: MatzeB, rtereshin, dsanders
Reviewed By: dsanders
Differential Revision: https://reviews.llvm.org/D55946
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350630
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Nico Weber [Tue, 8 Jan 2019 15:16:14 +0000 (15:16 +0000)]
[gn build] Add build files for llvm/lib/Target/PowerPC + tests
The PowerPC target itself is similar to the X86 target in https://reviews.llvm.org/rL348903
The llvm-exegesis unittests bits are similar to the corresponding AArch64 in https://reviews.llvm.org/rL350499
The whole patch is very similar to the WebAssembly target being added in https://reviews.llvm.org/rL350628
Also add a dep from tools/llvm-exegesis/lib to the AArch64 subdir, which I
failed to do in r350499.
The motivation for this target is solely that it has a unit test and I want to
enable the GN<->CMake unittest syncing check for llvm.
Differential Revision: https://reviews.llvm.org/D56416
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350629
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Nico Weber [Tue, 8 Jan 2019 15:12:42 +0000 (15:12 +0000)]
[gn build] Add build files for llvm/lib/Target/WebAssembly + tests
The WebAssembly target itself is similar to the X86 target in https://reviews.llvm.org/rL348903
The unittests bits are similar to the corresponding AArch64 in https://reviews.llvm.org/rL350499
The motivation for this target is solely that it has a unit test and I want to
enable the GN<->CMake unittest syncing check for llvm. (After this, only the
PowerPC target is needed and I can turn it on.)
Differential Revision: https://reviews.llvm.org/D56374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350628
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Petr Pavlu [Tue, 8 Jan 2019 14:19:06 +0000 (14:19 +0000)]
[GlobalISel] Fix choice of instruction selector for AArch64 at -O0 with -global-isel=0
Commit rL347861 introduced an unintentional change in the behaviour when
compiling for AArch64 at -O0 with -global-isel=0. Previously, explicitly
disabling GlobalISel resulted in using FastISel but an updated condition
in the commit changed it to using SelectionDAG. The patch fixes this
condition and slightly better organizes the code that chooses the
instruction selector.
Fixes PR40131.
Differential Revision: https://reviews.llvm.org/D56266
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350626
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Philip Pfaffe [Tue, 8 Jan 2019 14:06:58 +0000 (14:06 +0000)]
[DA][NewPM] Add a printerpass and port the testsuite
The new-pm version of DA is untested. Testing requires a printer, so
add that and use it in the existing DA tests.
Differential Revision: https://reviews.llvm.org/D56386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350624
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Francis Visoiu Mistrih [Tue, 8 Jan 2019 13:53:15 +0000 (13:53 +0000)]
[X86][Darwin] Emit compact-unwind for register-sized stack adjustments
For stack frames on the size of a register in x86, a code size optimization
emits "push rax/eax" instead of "sub" for stack allocation. For example:
foo:
.cfi_startproc
BB#0:
pushq %rax
Ltmp0:
.cfi_def_cfa_offset 16
...
.cfi_endproc
However, we are falling back to DWARF in this case because we cannot
encode %rax as a saved register.
This requirement is wrong, since we don't care about the contents of
%rax, it is the equivalent of a sub.
In order to specify that we care about the contents of %rax, we would
need a .cfi_offset %rax, <offset>.
It's also overzealous in the case where there are pushes for callee saved
registers followed by a "push rax/eax" instead of "sub", in which case we should
also be able to encode the callee saved regs and everything else using compact
unwind.
Patch authored by Bruno Cardoso Lopes.
Differential Revision: https://reviews.llvm.org/D13793
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350623
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Lama Saba [Tue, 8 Jan 2019 13:30:36 +0000 (13:30 +0000)]
Revert "Revert "Resubmit rL345008 "Split MachinePipeliner code into header and cpp files"""
This reverts commit rL350497
reported remaining issues seem to be unrelated to modules or this change.
more info: https://reviews.llvm.org/D56084
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350621
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Tim Northover [Tue, 8 Jan 2019 13:30:27 +0000 (13:30 +0000)]
AArch64: avoid splitting vector truncating stores.
We have code to split vector splats (of zero and non-zero) for performance
reasons, but it ignores the fact that a store might be truncating.
Actually, truncating stores are formed for vNi8 and vNi16 types. Since the
truncation is from a legal type, the size of the store is always <= 64-bits and
so they don't actually benefit from being split up anyway, so this patch just
disables that transformation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350620
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Benjamin Kramer [Tue, 8 Jan 2019 12:54:26 +0000 (12:54 +0000)]
[GlobalISel] Fix unused variable warning in Release builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350618
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James Henderson [Tue, 8 Jan 2019 10:58:05 +0000 (10:58 +0000)]
[llvm-readobj] Don't print '@' at end of unversioned dynsym names
This fixes https://bugs.llvm.org/show_bug.cgi?id=40097. The problem was
caused by a regression in r188022.
See also r350614.
Reviewed by: rupprecht, mstorsjo, Higuoxing, jakehehrlich
Differential Revision: https://reviews.llvm.org/D56319
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350615
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Sam Parker [Tue, 8 Jan 2019 10:12:36 +0000 (10:12 +0000)]
[ARM] Add missing patterns for DSP muls
Using a PatLeaf for sext_16_node allowed matching smulbb and smlabb
instructions once the operands had been sign extended. But we also
need to use sext_inreg operands along with sext_16_node to catch a
few more cases that enable use to remove the unnecessary sxth.
Differential Revision: https://reviews.llvm.org/D55992
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350613
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Matt Arsenault [Tue, 8 Jan 2019 06:30:53 +0000 (06:30 +0000)]
AMDGPU/GlobalISel: Introduce vcc reg bank
I'm not entirely sure this is the correct thing
to do with the global isel philosophy, but I think
this is necessary to handle how differently SGPRs
are used normally vs. from a condition.
For example, it makes sense to allow a copy
from a VGPR to an SGPR, but it makes no sense
to allow a copy from VGPRs to SGPRs used as
select mask.
This avoids regbankselecting strange code with
a truncate feeding directly into a condition field.
Now a copy is forced from sgpr(s1) to vcc, which is
more sensible to handle.
Some of these issues could probably avoided with making enough
operations resulting in i1 illegal. I think we can't avoid
this register bank for legality.
For example, an i1 and where one source is from a truncate, and
one source is a compare needs some kind of copy inserted to
make sure both are in condition registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350611
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Thomas Lively [Tue, 8 Jan 2019 06:25:55 +0000 (06:25 +0000)]
[WebAssembly] Massive instruction renaming
Summary:
An automated renaming of all the instructions listed at
https://github.com/WebAssembly/spec/issues/884#issuecomment-
426433329
as well as some similarly-named identifiers.
Reviewers: aheejin, dschuff, aardappel
Subscribers: sbc100, jgravelle-google, eraman, sunfish, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D56338
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350609
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Robert Widmann [Tue, 8 Jan 2019 06:24:19 +0000 (06:24 +0000)]
[LLVM-C] Allow For Creating a BasicBlock without a Parent Function
Summary: Add a utility function for creating a basic block without a parent function. A useful operation for compilers that need to synthesize and conditionally insert code without having to bother with appending and immediately unlinking a block.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D56279
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350608
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Robert Widmann [Tue, 8 Jan 2019 06:23:22 +0000 (06:23 +0000)]
[LLVM-C] Allow Specifying Signedness in Int Cast
Summary: Fix an old outstanding problem with the int cast builder binding always assuming the cast is signed by introducing a new LLVMBuildIntCast2 operation and deprecating the old prototype.
Reviewers: whitequark, deadalnix
Reviewed By: whitequark
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D56280
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350607
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Mandeep Singh Grang [Tue, 8 Jan 2019 04:48:00 +0000 (04:48 +0000)]
[MC] [AArch64] Support resolving signed fixups for :abs_g0_s: etc.
Summary: This patch is a follow-up to D55896.
Reviewers: efriedma, mstorsjo
Reviewed By: efriedma
Subscribers: javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D56029
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350606
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Chris Kennelly [Tue, 8 Jan 2019 04:04:51 +0000 (04:04 +0000)]
[NFC] Remove empty line as a test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350605
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Peter Collingbourne [Tue, 8 Jan 2019 04:00:22 +0000 (04:00 +0000)]
gn build: Stop passing -o to ar.
The -o flag means something different to ar than what appears to be
intended here. Also, llvm-ar doesn't accept the flag in this position.
Differential Revision: https://reviews.llvm.org/D56426
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350604
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Peter Collingbourne [Tue, 8 Jan 2019 01:46:57 +0000 (01:46 +0000)]
gn build: Merge r350580.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350600
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Matt Arsenault [Tue, 8 Jan 2019 01:30:02 +0000 (01:30 +0000)]
AMDGPU/GlobalISel: Legalize concat_vectors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350598
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Matt Arsenault [Tue, 8 Jan 2019 01:25:47 +0000 (01:25 +0000)]
Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350597
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Heejin Ahn [Tue, 8 Jan 2019 01:25:12 +0000 (01:25 +0000)]
[WebAssembly] Move CFG-changing passes before RegStackify
Summary:
FixIrreducibleControlFlow and LateEHPrepare both possibly modify CFG and
create new registers. There seems to be no reason these passes go after
register-related optimization passes (PrepareForLiveIntervals,
OptimizeLiveIntervals, StoreResults, RegStackify, and RegColoring), and
this also possibly create new optimization opportunities. I think we
should put all current and future optimization passes before RegStackify
(and related passes) unless there's a reason not to.
Reviewers: kripken
Subscribers: dschuff, sbc100, sunfish, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D56356
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350596
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Matt Arsenault [Tue, 8 Jan 2019 01:22:47 +0000 (01:22 +0000)]
RegBankSelect: Fix copy insertion point for terminators
If a copy was needed to handle the condition of brcond, it was being
inserted before the defining instruction. Add tests for iterator edge
cases.
I find the existing code here suspect for the case where it's looking
for terminators that modify the register. It's going to insert a copy
in the middle of the terminators, which isn't allowed (it might be
necessary to have a COPY_terminator if anybody actually needs this).
Also legalize brcond for AMDGPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350595
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Heejin Ahn [Tue, 8 Jan 2019 01:15:15 +0000 (01:15 +0000)]
[WebAssembly] Use 'I' multiclass template for br_table (NFC)
Summary:
We don't need to explicitly use `NI` anymore because we now don't use
`let` statements within the definitions.
Reviewers: aardappel
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D56376
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350594
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Matt Arsenault [Tue, 8 Jan 2019 01:13:20 +0000 (01:13 +0000)]
AMDGPU/GlobalISel: Disallow VGPR->SCC copies
This fixes using scalar adds when only the carry in is a VGPR
using greedy regbankselect.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350593
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Matt Arsenault [Tue, 8 Jan 2019 01:09:09 +0000 (01:09 +0000)]
AMDGPU/GlobalISel: RegBankSelect for carry-in
I'm not sure we should be allowing the truncate
to s1 for the inputs. It may be necessary to
create a new VCC reg bank.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350592
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Jonas Devlieghere [Tue, 8 Jan 2019 01:08:09 +0000 (01:08 +0000)]
[dsymutil] Fix assertion triggered by empty address range.
An assertion was hit when running dsymutil on a gcc generated binary
that contained an empty address range. Address ranges are stored in an
interval map of half open intervals. Since the interval is empty and
therefore meaningless, we simply don't add it to the map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350591
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Matt Arsenault [Tue, 8 Jan 2019 01:03:58 +0000 (01:03 +0000)]
AMDGPU/GlobalISel: RegBankSelect for add/sub with carry out
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350589
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Matt Arsenault [Tue, 8 Jan 2019 00:46:19 +0000 (00:46 +0000)]
AMDGPU/GlobalISel: InstrMapping for G_UNMERGE_VALUES
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350588
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Chen Zheng [Tue, 8 Jan 2019 00:40:01 +0000 (00:40 +0000)]
fix comment typo - NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350587
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Wei Mi [Tue, 8 Jan 2019 00:26:11 +0000 (00:26 +0000)]
[RegisterCoalescer] dst register's live interval needs to be updated when
merging a src register in ToBeUpdated set.
This is to fix PR40061 related with https://reviews.llvm.org/rL339035.
In https://reviews.llvm.org/rL339035, live interval of source pseudo register
in rematerialized copy may be saved in ToBeUpdated set and its update may be
postponed.
In PR40061, %t2 = %t1 is rematerialized and %t1 is added into toBeUpdated set
to postpone its live interval update. After the rematerialization, the live
interval of %t1 is larger than necessary. Then %t1 is merged into %t3 and %t1
gets removed. After the merge, %t3 contains live interval larger than necessary.
Because %t3 is not in toBeUpdated set, its live interval is not updated after
register coalescing and it will break some assumption in regalloc.
The patch requires the live interval of destination register in a merge to be
updated if the source register is in ToBeUpdated.
Differential revision: https://reviews.llvm.org/D55867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350586
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Jonas Devlieghere [Mon, 7 Jan 2019 23:27:25 +0000 (23:27 +0000)]
[dsymutil] Upstream unobfuscation logic.
The unobufscation support for BCSymbolMaps was the last piece of code
that hasn't been upstreamed yet. This patch contains a reworked version
of the existing code and relevant tests.
Differential revision: https://reviews.llvm.org/D56346
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350580
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Rong Xu [Mon, 7 Jan 2019 23:25:56 +0000 (23:25 +0000)]
[PGO] Use SourceFileName rather module name in PGOFuncName
In LTO or Thin-lto mode (though linker plugin), the module
names are of temp file names which are different for
different compilations. Using SourceFileName avoids the issue.
This should not change any functionality for current PGO as
all the current callers of getPGOFuncName() is before LTO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350579
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Davide Italiano [Mon, 7 Jan 2019 23:09:09 +0000 (23:09 +0000)]
[Verifier] Reject invalid type for DILocalVariable.
Reviewers: aprantl
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D56414
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350578
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Michael Ferguson [Mon, 7 Jan 2019 21:02:22 +0000 (21:02 +0000)]
[ValueTracking] Adjust comment in test
Adjusts a comment in this test to verify commit access.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350569
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Craig Topper [Mon, 7 Jan 2019 21:00:32 +0000 (21:00 +0000)]
Recommit r350554 "[X86] Remove AVX512VBMI2 concat and shift intrinsics. Replace with target independent funnel shift intrinsics."
The MSVC limit we hit on AutoUpgrade.cpp has been worked around for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350567
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Martin Storsjo [Mon, 7 Jan 2019 20:55:33 +0000 (20:55 +0000)]
[ObjectYAML] [COFF] Support multiple symbols with the same name
Differential Revision: https://reviews.llvm.org/D56294
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350566
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Craig Topper [Mon, 7 Jan 2019 20:13:45 +0000 (20:13 +0000)]
[X86][AutoUpgrade] Make some tweaks to reduce the number of nested if/else in the intrinsic upgrade code to avoid an MSVC compiler limit.
MSVC has a nesting limit of around 110-130. An if/else if/else if counts against this next level. The autoupgrade code consists a long chain of these checking matches against strings.
This commit moves some code to a helper function to move out a large if/else chain that was inside of one of the blocks into a separate function. There are more of these we could move or we could change some to lookup tables.
I've also merged together a few similar blocks in the outer chain. This should buy us some margin for a little bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350564
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Craig Topper [Mon, 7 Jan 2019 19:39:05 +0000 (19:39 +0000)]
Revert r350554 "[X86] Remove AVX512VBMI2 concat and shift intrinsics. Replace with target independent funnel shift intrinsics."
The AutoUpgrade.cpp if/else cascade hit an MSVC limit again.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350562
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Alina Sbirlea [Mon, 7 Jan 2019 19:38:47 +0000 (19:38 +0000)]
[MemorySSA] Add SkipSelfWalker.
Summary: Add implementation of SkipSelfWalker.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D56285
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350561
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Craig Topper [Mon, 7 Jan 2019 19:30:43 +0000 (19:30 +0000)]
[TargetLowering][AMDGPU] Remove the SimplifyDemandedBits function that takes a User and OpIdx. Stop using it in AMDGPU target for simplifyI24.
As we saw in D56057 when we tried to use this function on X86, it's unsafe. It allows the operand node to have multiple users, but doesn't prevent recursing past the first node when it does have multiple users. This can cause other simplifications earlier in the graph without regard to what bits are needed by the other users of the first node. Ideally all we should do to the first node if it has multiple uses is bypass it when its not needed by the user we started from. Doing any other transformation that SimplifyDemandedBits can do like turning ZEXT/SEXT into AEXT would result in an increase in instructions.
Fortunately, we already have a function that can do just that, GetDemandedBits. It will only make transformations that involve bypassing a node.
This patch changes AMDGPU's simplifyI24, to use a combination of GetDemandedBits to handle the multiple use simplifications. And then uses the regular SimplifyDemandedBits on each operand to handle simplifications allowed when the operand only has a single use. Unfortunately, GetDemandedBits simplifies constants more aggressively than SimplifyDemandedBits. This caused the -7 constant in the changed test to be simplified to remove the upper bits. I had to modify computeKnownBits to account for this by ignoring the upper 8 bits of the input.
Differential Revision: https://reviews.llvm.org/D56087
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350560
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Alina Sbirlea [Mon, 7 Jan 2019 19:22:37 +0000 (19:22 +0000)]
[MemorySSA] Refactor CachingWalker.
Summary:
Refactor caching walker to make creating a walker that skips the
starting access strightforward.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits, jfb
Differential Revision: https://reviews.llvm.org/D55957
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350558
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Craig Topper [Mon, 7 Jan 2019 19:10:12 +0000 (19:10 +0000)]
[X86] Remove AVX512VBMI2 concat and shift intrinsics. Replace with target independent funnel shift intrinsics.
Differential Revision: https://reviews.llvm.org/D56377
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350554
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Diogo N. Sampaio [Mon, 7 Jan 2019 19:01:47 +0000 (19:01 +0000)]
[ARM] ComputeKnownBits to handle extract vectors
This patch adds the sign/zero extension done by
vgetlane to ARM computeKnownBitsForTargetNode.
Differential revision: https://reviews.llvm.org/D56098
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350553
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Alina Sbirlea [Mon, 7 Jan 2019 18:40:27 +0000 (18:40 +0000)]
[MemorySSA] Extend the clobber walker with the option to skip the starting access.
Summary:
The option enables loop transformations to hoist accesses that do not
have clobbers in the loop. If the clobber queries skips the starting
access, the result may be outside the loop instead of the header Phi.
Adding the walker that uses this option in a separate patch.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Differential Revision: https://reviews.llvm.org/D55944
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350551
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Nikita Popov [Mon, 7 Jan 2019 18:15:11 +0000 (18:15 +0000)]
Revert "[DemandedBits] Use SetVector for Worklist"
This reverts commit r350547.
Seeing assertion failures on clang tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350549
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Simon Pilgrim [Mon, 7 Jan 2019 18:07:56 +0000 (18:07 +0000)]
[X86] Add OR(AND(X,C),AND(Y,~C)) bit select tests
Based off work for D55935
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350548
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Nikita Popov [Mon, 7 Jan 2019 18:03:36 +0000 (18:03 +0000)]
[DemandedBits] Use SetVector for Worklist
DemandedBits currently uses a simple vector for the worklist, which
means that instructions may be inserted multiple times into it.
Especially in combination with the deep lattice, this may cause
instructions too be recomputed very often. To avoid this, switch
to a SetVector.
Differential Revision: https://reviews.llvm.org/D56362
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350547
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Armando Montanez [Mon, 7 Jan 2019 17:33:10 +0000 (17:33 +0000)]
[elfabi] Add option to manually specify file read format
Although llvm-elfabi will attempt to read input files without needing the format to be manually specified, doing so has the potential to introduce extraneous errors that can hinder debugging (since multiple readers may fail in attempts to read the file). This change allows the input file format to be manually specified to force elfabi to use a single reader. This makes it easier to test and debug errors specific to a given reader.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350545
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Jordan Rupprecht [Mon, 7 Jan 2019 16:59:12 +0000 (16:59 +0000)]
[llvm-objcopy] Handle -O <format> flag.
Summary:
The -O flag is currently being mostly ignored; it's only checked whether or not the output format is "binary". This adds support for a few formats (e.g. elf64-x86-64), so that when specified, the output can change between 32/64 bit and sizes/alignments are updated accordingly.
This fixes PR39135
Reviewers: jakehehrlich, jhenderson, alexshap, espindola
Reviewed By: jhenderson
Subscribers: emaste, arichardson, llvm-commits
Differential Revision: https://reviews.llvm.org/D53667
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350541
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David Greene [Mon, 7 Jan 2019 16:24:37 +0000 (16:24 +0000)]
[lit] Respect PYTHONPATH
If a user has PYTHONPATH set in the environment, append new entries to
it rather than blindly setting PYTHONPATH to a fixed string. This
allows tests to, for example, find psutil if it is in
PYTHONPATH. Without this change, lit will detect psutil but then
various tests will fail because PYTHONPATH has been overwritten and
psutil cannot be found.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350536
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Matt Morehouse [Mon, 7 Jan 2019 16:14:00 +0000 (16:14 +0000)]
[llvm-demangle-fuzzer] Also fuzz microsoftDemangle().
Summary:
Use first byte of input to determine whether to call itaniumDemangle()
or microsoftDemangle().
Addresses https://bugs.llvm.org/show_bug.cgi?id=39582.
Reviewers: kcc, thakis
Reviewed By: kcc, thakis
Subscribers: mgorny, thakis, erik.pilkington, llvm-commits
Differential Revision: https://reviews.llvm.org/D54780
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350534
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Sanjay Patel [Mon, 7 Jan 2019 16:10:14 +0000 (16:10 +0000)]
[x86] add more tests for LowerToHorizontalOp(); NFC
These tests show missed optimizations and a miscompile
similar to PR40243 - https://bugs.llvm.org/show_bug.cgi?id=40243
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350533
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Rhys Perry [Mon, 7 Jan 2019 15:52:28 +0000 (15:52 +0000)]
AMDGPU: test for uniformity of branch instruction, not its condition
Summary:
If a divergent branch instruction is marked as divergent by propagation
rule 2 in DivergencePropagator::exploreSyncDependency() and its condition
is uniform, that branch would incorrectly be assumed to be uniform.
Reviewers: arsenm, tstellar
Reviewed By: arsenm
Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D56331
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350532
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James Henderson [Mon, 7 Jan 2019 14:12:51 +0000 (14:12 +0000)]
[llvm-nm] Add --portability as alias for --format=posix
GNU nm supports this alias, so supporting it in llvm-nm makes it easier
to transition between the two.
Fixes https://bugs.llvm.org/show_bug.cgi?id=40002
Reviewed by: mstorsjo, rupprecht
Differential Revision: https://reviews.llvm.org/D56312
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350522
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Alexandre Ganea [Mon, 7 Jan 2019 13:53:16 +0000 (13:53 +0000)]
[CodeView] More appropriate name and type for a Microsoft precompiled headers parameter. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350520
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Matt Arsenault [Mon, 7 Jan 2019 13:31:55 +0000 (13:31 +0000)]
AMDGPU: Remove v16i8 from register classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350518
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Matt Arsenault [Mon, 7 Jan 2019 13:21:36 +0000 (13:21 +0000)]
AMDGPU: Remove VS/SV mappings from select
These would violate the constant bus restriction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350517
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Simon Pilgrim [Mon, 7 Jan 2019 12:21:13 +0000 (12:21 +0000)]
Regenerate test.
Prep work towards enabling SimplifyDemandedBits vector support for TRUNCATE as discussed on D56118.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350514
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Simon Pilgrim [Mon, 7 Jan 2019 12:20:35 +0000 (12:20 +0000)]
Regenerate test.
Prep work towards enabling SimplifyDemandedBits vector support for TRUNCATE as discussed on D56118.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350513
91177308-0d34-0410-b5e6-
96231b3b80d8