OSDN Git Service
Richard Henderson [Fri, 29 Apr 2022 21:18:40 +0000 (14:18 -0700)]
semihosting: Use env more often in do_common_semihosting
We've already loaded cs->env_ptr into a local variable; use it.
Since env is unconditionally used, we don't need a dummy use.
Reviewed-by: Luc Michel <lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 7 Jun 2022 17:31:22 +0000 (10:31 -0700)]
semihosting: Split out common-semi-target.h
Move the ARM and RISCV specific helpers into
their own header file.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Luc Michel <lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 29 Apr 2022 21:16:01 +0000 (14:16 -0700)]
semihosting: Split out common_semi_has_synccache
We already have some larger ifdef blocks for ARM and RISCV;
split out a boolean test for SYS_SYNCCACHE.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 29 Apr 2022 20:59:52 +0000 (13:59 -0700)]
semihosting: Split common_semi_flen_buf per target
We already have some larger ifdef blocks for ARM and RISCV;
split out common_semi_stack_bottom per target.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 18:31:04 +0000 (11:31 -0700)]
semihosting: Split is_64bit_semihosting per target
We already have some larger ifdef blocks for ARM and RISCV;
split the function into multiple implementations per arch.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 29 Apr 2022 21:55:21 +0000 (14:55 -0700)]
semihosting: Use struct gdb_stat in common_semi_flen_cb
Load the entire 64-bit size value. While we're at it,
use offsetof instead of an integer constant.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 7 Jun 2022 19:38:26 +0000 (12:38 -0700)]
gdbstub: Convert GDB error numbers to host error numbers
Provide the callback with consistent state -- always use
host error numbers. The individual callback can then
decide if the errno requires conversion for the guest.
Reviewed-by: Luc Michel <lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 2 May 2022 01:35:18 +0000 (18:35 -0700)]
include/exec: Define errno values in gdbstub.h
Define constants for the errno values defined by the
gdb remote fileio protocol.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 29 Apr 2022 21:41:37 +0000 (14:41 -0700)]
include/exec: Move gdb_stat and gdb_timeval to gdbstub.h
We have two copies of these structures, and require them
in semihosting/ going forward.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 08:29:54 +0000 (01:29 -0700)]
include/exec: Move gdb open flags to gdbstub.h
There were 3 copies of these flags. Place them in the
file with gdb_do_syscall, with which they belong.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 7 Jun 2022 17:50:43 +0000 (10:50 -0700)]
semihosting: Remove GDB_O_BINARY
The value is zero, and gdb always opens files in binary mode.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 08:14:02 +0000 (01:14 -0700)]
semihosting: Move common-semi.h to include/semihosting/
This header is not private to the top-level semihosting directory,
so place it in the public include directory.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 08:10:55 +0000 (01:10 -0700)]
semihosting: Return void from do_common_semihosting
Perform the cleanup in the FIXME comment in common_semi_gdb_syscall.
Do not modify guest registers until the syscall is complete,
which in the gdbstub case is asynchronous.
In the synchronous non-gdbstub case, use common_semi_set_ret
to set the result. Merge set_swi_errno into common_semi_cb.
Rely on the latter for combined return value / errno setting.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 17 May 2022 02:37:14 +0000 (19:37 -0700)]
semihosting: Clean up common_semi_open_cb
Use common_semi_cb to return results instead of calling
set_swi_errno and common_semi_set_ret directly.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 17 May 2022 02:34:06 +0000 (19:34 -0700)]
semihosting: Clean up common_semi_flen_cb
Do not read from the gdb struct stat buffer if the callback is
reporting an error. Use common_semi_cb to finish returning results.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Fri, 29 Apr 2022 19:32:24 +0000 (12:32 -0700)]
semihosting: Adjust error checking in common_semi_cb
The err parameter is non-zero if and only if an error occured.
Use this instead of ret == -1 for determining if we need to
update the saved errno.
This fixes the errno setting of SYS_ISTTY, which returns 0 on
error, not -1.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Tue, 17 May 2022 02:25:19 +0000 (19:25 -0700)]
semihosting: Inline set_swi_errno into common_semi_cb
Do not store 'err' into errno only to read it back immediately.
Use 'ret' for the return value, not 'reg0'.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 04:38:02 +0000 (21:38 -0700)]
semihosting: Split out guestfd.c
In arm-compat-semi.c, we have more advanced treatment of
guest file descriptors than we do in other implementations.
Split out GuestFD and related functions to a new file so
that they can be shared.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 04:06:58 +0000 (21:06 -0700)]
semihosting: Simplify softmmu_lock_user_string
We are not currently bounding the search to the 1024 bytes
that we allocated, possibly overrunning the buffer.
Use softmmu_strlen_user to find the length and allocate the
correct size from the beginning.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 04:03:12 +0000 (21:03 -0700)]
semihosting: Add target_strlen for softmmu-uaccess.h
Mirror the interface of the user-only function of the same name.
Use probe_access_flags for the common case of ram, and
cpu_memory_rw_debug for the uncommon case of mmio.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Use probe_access_flags (pmm)
Richard Henderson [Sat, 21 May 2022 05:12:08 +0000 (22:12 -0700)]
accel/stubs: Add tcg stub for probe_access_flags
Reviewed-by: Luc Michel <lmichel@kalray.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 03:44:17 +0000 (20:44 -0700)]
semihosting: Move softmmu-uaccess.h functions out of line
Rather that static (and not even inline) functions within a
header, move the functions to semihosting/uaccess.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sat, 30 Apr 2022 01:32:35 +0000 (18:32 -0700)]
semihosting: Improve condition for config.c and console.c
While CONFIG_SEMIHOSTING is currently only set for softmmu,
this will not continue to be true.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 03:01:24 +0000 (20:01 -0700)]
semihosting: Return failure from softmmu-uaccess.h functions
We were reporting unconditional success for these functions;
pass on any failure from cpu_memory_rw_debug.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Thu, 28 Apr 2022 03:48:41 +0000 (20:48 -0700)]
semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.h
We have a subdirectory for semihosting; move this file out of exec.
Rename to emphasize the contents are a replacement for the functions
in linux-user/bsd-user uaccess.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Mon, 27 Jun 2022 11:17:39 +0000 (16:47 +0530)]
Merge tag 'pull-target-arm-
20220627' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* sphinx: change default language to 'en'
* Diagnose attempts to emulate EL3 in hvf as well as kvm
* More SME groundwork patches
* virt: Fix calculation of physical address space size
for v7VE CPUs (eg cortex-a15)
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmK5hKEZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lggEACtE2balVHrVCeSQkRW+FnS
# avm5i54MIGf3cgNhTKwD9ED3hl03Xm49yQkaq0gB6Qa4wQPEcYQLSyzP+UYIILO5
# 3xoWEw0nbtKWBuCzdiolynL1VFht6GV+Ga8lShoBiQsI/eARC6ZELvBv7gbApf4p
# DpDq1ty7fXMmMCNM5vgX9fu/LXahSONDXbYMpHpohnaLXCEF9MwqpO5TJf65Bgze
# z2+NO4R5u26mCcad7ltoiz3OKkq4Bq+b+QXrm6LmvSCIkvk6MUZuU1NwHSiqUoV/
# nOwhJriOVl8JG0sX0xzNZADYBt0YlcVuDZzyxP8eOiQ54CVK7rJOJSi+aiGkg2Mn
# YC4CkFZY9iM5YTA6y6T5mye7kLb/pJ746rLM1ia6Ng3rUwoE9bdvruqTMfPPJuoo
# XxMBQrjRjY6BzESG0NbjLgg80dPtqeOipjglYI7GCvh0i2yQVmKLQon5TK9DsScC
# 7Gu6IPVWZAb3axGEuqjJ4E+7PyyEW7zYgWNOpZoQW958WHDK0KSPrOwqxAC+QdEi
# vagKJGCQPuZiOARpXm6F/nscEDcy7P33z120O9/R6HuticGaM/oBaWy89CR4hbHB
# NWx5+0h5M/je8hJFJJVfHldR3nIpvnUtb4KEVoiNuxkrGZoejgTlBdKNL4Nph0U0
# E+CQyMuBBQ88LEbyCjJS5w==
# =GILG
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 27 Jun 2022 03:51:21 PM +0530
# gpg: using RSA key
E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
* tag 'pull-target-arm-
20220627' of https://git.linaro.org/people/pmaydell/qemu-arm: (25 commits)
target/arm: Check V7VE as well as LPAE in arm_pamax
target/arm: Extend arm_pamax to more than aarch64
target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h
target/arm: Add SVL to TB flags
target/arm: Introduce sve_vqm1_for_el_sm
target/arm: Add cpu properties for SME
target/arm: Unexport aarch64_add_*_properties
target/arm: Move arm_cpu_*_finalize to internals.h
target/arm: Generalize cpu_arm_{get, set}_default_vec_len
target/arm: Generalize cpu_arm_{get,set}_vq
target/arm: Create ARMVQMap
target/arm: Move error for sve%d property to arm_cpu_sve_finalize
target/arm: Implement SMSTART, SMSTOP
target/arm: Add the SME ZA storage to CPUARMState
target/arm: Add PSTATE.{SM,ZA} to TB flags
target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2
target/arm: Add SMCR_ELx
target/arm: Add SVCR
target/arm: Add ARM_CP_SME
target/arm: Add syn_smetrap
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Richard Henderson [Sun, 19 Jun 2022 00:15:41 +0000 (17:15 -0700)]
target/arm: Check V7VE as well as LPAE in arm_pamax
In machvirt_init we create a cpu but do not fully initialize it.
Thus the propagation of V7VE to LPAE has not been done, and we
compute the wrong value for some v7 cpus, e.g. cortex-a15.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1078
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: He Zhe <zhe.he@windriver.com>
Message-id:
20220619001541.131672-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sun, 19 Jun 2022 00:15:40 +0000 (17:15 -0700)]
target/arm: Extend arm_pamax to more than aarch64
Move the code from hw/arm/virt.c that is supposed
to handle v7 into the one function.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: He Zhe <zhe.he@windriver.com>
Message-id:
20220619001541.131672-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:52:04 +0000 (10:52 -0700)]
target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h
We will need these functions in translate-sme.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:52:03 +0000 (10:52 -0700)]
target/arm: Add SVL to TB flags
We need SVL separate from VL for RDSVL et al, as well as
ZA storage loads and stores, which do not require PSTATE.SM.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:52:02 +0000 (10:52 -0700)]
target/arm: Introduce sve_vqm1_for_el_sm
When Streaming SVE mode is enabled, the size is taken from
SMCR_ELx instead of ZCR_ELx. The format is shared, but the
set of vector lengths is not. Further, Streaming SVE does
not require any particular length to be supported.
Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM
to the new function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:52:01 +0000 (10:52 -0700)]
target/arm: Add cpu properties for SME
Mirror the properties for SVE. The main difference is
that any arbitrary set of powers of 2 may be supported,
and not the stricter constraints that apply to SVE.
Include a property to control FEAT_SME_FA64, as failing
to restrict the runtime to the proper subset of insns
could be a major point for bugs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id:
20220620175235.60881-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:52:00 +0000 (10:52 -0700)]
target/arm: Unexport aarch64_add_*_properties
These functions are not used outside cpu64.c,
so make them static.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:59 +0000 (10:51 -0700)]
target/arm: Move arm_cpu_*_finalize to internals.h
Drop the aa32-only inline fallbacks,
and just use a couple of ifdefs.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:58 +0000 (10:51 -0700)]
target/arm: Generalize cpu_arm_{get, set}_default_vec_len
Rename from cpu_arm_{get,set}_sve_default_vec_len,
and take the pointer to default_vq from opaque.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:57 +0000 (10:51 -0700)]
target/arm: Generalize cpu_arm_{get,set}_vq
Rename from cpu_arm_{get,set}_sve_vq, and take the
ARMVQMap as the opaque parameter.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:56 +0000 (10:51 -0700)]
target/arm: Create ARMVQMap
Pull the three sve_vq_* values into a structure.
This will be reused for SME.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:55 +0000 (10:51 -0700)]
target/arm: Move error for sve%d property to arm_cpu_sve_finalize
Keep all of the error messages together. This does mean that
when setting many sve length properties we'll only generate
one error, but we only really need one.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:54 +0000 (10:51 -0700)]
target/arm: Implement SMSTART, SMSTOP
These two instructions are aliases of MSR (immediate).
Use the two helpers to properly implement svcr_write.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:53 +0000 (10:51 -0700)]
target/arm: Add the SME ZA storage to CPUARMState
Place this late in the resettable section of the structure,
to keep the most common element offsets from being > 64k.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-10-richard.henderson@linaro.org
[PMM: expanded comment on zarray[] format]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:52 +0000 (10:51 -0700)]
target/arm: Add PSTATE.{SM,ZA} to TB flags
These are required to determine if various insns
are allowed to issue.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:51 +0000 (10:51 -0700)]
target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2
Implement the streaming mode identification register, and the
two streaming priority registers. For QEMU, they are all RES0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:50 +0000 (10:51 -0700)]
target/arm: Add SMCR_ELx
These cpregs control the streaming vector length and whether the
full a64 instruction set is allowed while in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:49 +0000 (10:51 -0700)]
target/arm: Add SVCR
This cpreg is used to access two new bits of PSTATE
that are not visible via any other mechanism.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:48 +0000 (10:51 -0700)]
target/arm: Add ARM_CP_SME
This will be used for controlling access to SME cpregs.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:47 +0000 (10:51 -0700)]
target/arm: Add syn_smetrap
This will be used for raising various traps for SME.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:46 +0000 (10:51 -0700)]
target/arm: Add SMEEXC_EL to TB flags
This is CheckSMEAccess, which is the basis for a set of
related tests for various SME cpregs and instructions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Mon, 20 Jun 2022 17:51:45 +0000 (10:51 -0700)]
target/arm: Implement TPIDR2_EL0
This register is part of SME, but isn't closely related to the
rest of the extension.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620175235.60881-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Fri, 24 Jun 2022 14:42:56 +0000 (15:42 +0100)]
target/arm: Catch invalid kvm state also for hvf
Some features such as running in EL3 or running M profile code are
incompatible with virtualization as QEMU implements it today. To prevent
users from picking invalid configurations on other virt solutions like
Hvf, let's run the same checks there too.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1073
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620192242.70573-2-agraf@csgraf.de
[PMM: Allow qtest accelerator too; tweak comment]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alexander Graf [Fri, 24 Jun 2022 14:42:56 +0000 (15:42 +0100)]
accel: Introduce current_accel_name()
We need to fetch the name of the current accelerator in flexible error
messages more going forward. Let's create a helper that gives it to us
without casting in the target code.
Signed-off-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
20220620192242.70573-1-agraf@csgraf.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Martin Liška [Fri, 24 Jun 2022 14:42:55 +0000 (15:42 +0100)]
sphinx: change default language to 'en'
Fixes the following Sphinx warning (treated as error) starting
with 5.0 release:
Warning, treated as error:
Invalid configuration value found: 'language = None'. Update your configuration to a valid langauge code. Falling back to 'en' (English).
Signed-off-by: Martin Liska <mliska@suse.cz>
Message-id:
e91e51ee-48ac-437e-6467-
98b56ee40042@suse.cz
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Richard Henderson [Sun, 26 Jun 2022 23:51:05 +0000 (05:21 +0530)]
Merge tag 'qemu-sparc-
20220626' of https://github.com/mcayland/qemu into staging
qemu-sparc queue
# -----BEGIN PGP SIGNATURE-----
#
# iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmK4moUeHG1hcmsuY2F2
# ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfaXsH/0+FT9TbHXCplB8h
# gvOETq9r5UscYMqUIbRPv7eFIhhZUfq4mCzpthZHYfMA6Tag0jMqaP5ymATm6Jm/
# GgS/7Fx+14uO54Cu4NwIFylRuDt39cESrBHrVjmXmYzOXx7a040+TPxtHHwSRXiQ
# Vvx5Oo0P8qQfADQe/Y9iray3JBdFMg4yejO37yrdfP58Nh2dzr9dNKw6apY8dwcv
# eTVTqVbYY5AAKOjStpxb0x8dFq/WXttclbeaiSZsK1wnuqhJdUtiMY3UaAfYdMEW
# kputMhTZqV/oopUY0mHmBEUK843s8bSQs2aoCSXLamGTWcrm27XNOsX0f4AYwf/y
# jWBcSvg=
# =0MrK
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 26 Jun 2022 11:12:29 PM +0530
# gpg: using RSA key
CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg: issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* tag 'qemu-sparc-
20220626' of https://github.com/mcayland/qemu: (55 commits)
artist: set memory region owners for buffers to the artist device
ps2: remove update_irq() function and update_arg parameter
pckbd: add QEMU interface comment for I8042 device
pckbd: switch I8042 device from update_irq() function to PS2 device gpio
pckbd: add i8042_reset() function to I8042 device
pckbd: add QEMU interface comment for I8042_MMIO device
pckbd: switch I8042_MMIO device from update_irq() function to PS2 device gpio
lasips2: add QEMU interface comment
lasips2: switch over from update_irq() function to PS2 device gpio
lasips2: use sysbus IRQ for output IRQ
lasips2: implement lasips2_realize()
lasips2: add base property
lasips2: move initialisation of PS2 ports from lasi_initfn() to lasi_init()
lasips2: move mapping of LASIPS2 registers to HPPA machine
lasips2: implement lasips2_init() function
lasips2: rename lasips2_init() to lasips2_initfn() and update it to return the LASIPS2 device
lasips2: move lasips2 QOM types from lasips2.c to lasips2.h
lasips2: QOMify LASIPS2State
pl050: add QEMU interface comment
pl050: switch over from update_irq() function to PS2 device gpio
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 16:08:39 +0000 (17:08 +0100)]
artist: set memory region owners for buffers to the artist device
This fixes the output of "info qom-tree" so that the buffers appear as children
of the artist device, rather than underneath the "unattached" container.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <
20220624160839.886649-1-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Helge Deller <deller@gmx.de>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:09 +0000 (14:41 +0100)]
ps2: remove update_irq() function and update_arg parameter
Now that all the PS2 devices have been converted to use GPIOs the update_irq()
callback function and the update_arg parameter can be removed.
This allows these arguments to be completely removed from ps2_kbd_init() and
ps2_mouse_init(), along with the transitional logic that was added to
ps2_raise_irq() and ps2_lower_irq().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-55-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:08 +0000 (14:41 +0100)]
pckbd: add QEMU interface comment for I8042 device
This describes the I8042 device interface implemented within QEMU.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <
20220624134109.881989-54-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:07 +0000 (14:41 +0100)]
pckbd: switch I8042 device from update_irq() function to PS2 device gpio
Define a new qdev input gpio for handling incoming PS2 IRQs, and then wire up the
PS2 keyboard and mouse devices to use it. At the same time set update_irq() and
update_arg to NULL in ps2_kbd_init() and ps2_mouse_init() to ensure that any
accidental attempt to use the legacy update_irq() function will cause a NULL
pointer dereference.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-53-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:06 +0000 (14:41 +0100)]
pckbd: add i8042_reset() function to I8042 device
This means that it is no longer necessary to call qemu_register_reset() manually
within i8042_realizefn().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-52-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:05 +0000 (14:41 +0100)]
pckbd: add QEMU interface comment for I8042_MMIO device
This describes the I8042_MMIO device interface implemented within QEMU.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <
20220624134109.881989-51-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:04 +0000 (14:41 +0100)]
pckbd: switch I8042_MMIO device from update_irq() function to PS2 device gpio
Define a new qdev input gpio for handling incoming PS2 IRQs, and then wire up the
PS2 keyboard and mouse devices to use it. At the same time set update_irq() and
update_arg to NULL in ps2_kbd_init() and ps2_mouse_init() to ensure that any
accidental attempt to use the legacy update_irq() function will cause a NULL
pointer dereference.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-50-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:03 +0000 (14:41 +0100)]
lasips2: add QEMU interface comment
This describes the LASI PS2 device interface implemented within QEMU.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <
20220624134109.881989-49-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:02 +0000 (14:41 +0100)]
lasips2: switch over from update_irq() function to PS2 device gpio
Add a qdev gpio input in lasips2_init() by taking the existing lasips2_port_set_irq()
function, updating it accordingly and then renaming to lasips2_set_irq(). Use these
new qdev gpio inputs to wire up the PS2 keyboard and mouse devices.
At the same time set update_irq() and update_arg to NULL in ps2_kbd_init() and
ps2_mouse_init() to ensure that any accidental attempt to use the legacy update_irq()
function will cause a NULL pointer dereference.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-48-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:01 +0000 (14:41 +0100)]
lasips2: use sysbus IRQ for output IRQ
This enables the IRQ to be wired up using sysbus_connect_irq() in
lasips2_initfn().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-47-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:41:00 +0000 (14:41 +0100)]
lasips2: implement lasips2_realize()
Move ps2_kbd_init() and ps2_mouse_init() from lasips2_initfn() to lasips2_realize.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-46-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:59 +0000 (14:40 +0100)]
lasips2: add base property
This is in preparation for handling vmstate_register() within the device.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-45-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:58 +0000 (14:40 +0100)]
lasips2: move initialisation of PS2 ports from lasi_initfn() to lasi_init()
This can be improved once the ps2_kbd_init() and ps2_mouse_init() functions have
been removed, but for now move the existing logic from lasi_initfn() to
lasi_init(). At the same time explicitly set keyboard port id to 0, even if it
isn't technically required.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-44-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:57 +0000 (14:40 +0100)]
lasips2: move mapping of LASIPS2 registers to HPPA machine
Now that the register memory regions are exposed as SysBus memory regions, move
the mapping of the LASIPS2 registers from lasips2_initfn() to the HPPA machine
(which is its only user).
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-43-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:56 +0000 (14:40 +0100)]
lasips2: implement lasips2_init() function
Move the initialisation of the keyboard and mouse memory regions to lasips2_init()
and expose them as SysBus memory regions.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-42-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:55 +0000 (14:40 +0100)]
lasips2: rename lasips2_init() to lasips2_initfn() and update it to return the LASIPS2 device
When QOMifying a device it is typical to use _init() as the suffix for an
instance_init function, however this name is already in use by the legacy LASIPS2
wrapper function. Eventually the wrapper function will be removed, but for now
rename it to lasips2_initfn() to avoid a naming collision.
At the same time update lasips2_initfn() return the LASIPS2 device so that it
can later be accessed using qdev APIs by the HPPA machine.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-41-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:54 +0000 (14:40 +0100)]
lasips2: move lasips2 QOM types from lasips2.c to lasips2.h
This allows the QOM types in lasips2.c to be used elsewhere by simply including
lasips2.h.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-40-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:53 +0000 (14:40 +0100)]
lasips2: QOMify LASIPS2State
Currently lasip2_init() creates a new LASIPS2State directly which is used by the HPPA
machine. Introduce a new LASIPS2 QOM type that will soon be used to allow the HPPA
machine to be wired up using standard qdev GPIOs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-39-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:52 +0000 (14:40 +0100)]
pl050: add QEMU interface comment
This describes the PL050 device interface implemented within QEMU.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <
20220624134109.881989-38-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:51 +0000 (14:40 +0100)]
pl050: switch over from update_irq() function to PS2 device gpio
Add a new pl050_init() function which initialises a qdev input gpio for handling
incoming PS2 IRQs, and then wire up the PS2 device to use it. At the same time
set update_irq() and update_arg to NULL in ps2_kbd_init() and ps2_mouse_init()
to ensure that any accidental attempt to use the legacy update_irq() function will
cause a NULL pointer dereference.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-37-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:50 +0000 (14:40 +0100)]
pckbd: replace irq_kbd and irq_mouse with qemu_irq array in KBDState
This allows both IRQs to be declared as a single qdev gpio array.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-36-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:49 +0000 (14:40 +0100)]
ps2: add gpio for output IRQ and optionally use it in ps2_raise_irq() and ps2_lower_irq()
Define the gpio for the PS2 output IRQ in ps2_init() and add logic to optionally
use it in ps2_raise_irq() and ps2_lower_irq() if the gpio is connected. If the
gpio is not connected then call the legacy update_irq() function as before.
This allows the incremental conversion of devices from the legacy update_irq()
function to use gpios instead.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-35-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:48 +0000 (14:40 +0100)]
ps2: introduce ps2_lower_irq() instead of calling update_irq() directly
This consolidates the logic of lowering the PS2 IRQ into one single function.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-34-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:47 +0000 (14:40 +0100)]
ps2: use ps2_raise_irq() instead of calling update_irq() directly
This consolidates the logic of raising the PS2 IRQ into one single function.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-33-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:46 +0000 (14:40 +0100)]
ps2: make ps2_raise_irq() function static
This function is no longer used outside of ps2.c and so can be declared static.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-32-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:45 +0000 (14:40 +0100)]
pckbd: move ps2_kbd_init() and ps2_mouse_init() to i8042_mmio_realize()
Move ps2_kbd_init() and ps2_mouse_init() from i8042_mm_init() to
i8042_mmio_realize() to further reduce the initialisation logic done in
i8042_mm_init().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-31-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:44 +0000 (14:40 +0100)]
pckbd: more vmstate_register() from i8042_mm_init() to i8042_mmio_realize()
Note in this case it is not possible to register a (new) VMStateDescription in
the DeviceClass without breaking migration compatibility for the MIPS magnum
machine.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-30-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:43 +0000 (14:40 +0100)]
pckbd: move mapping of I8042_MMIO registers to MIPS magnum machine
Now that the register memory region is exposed as a SysBus memory region, move
the mapping of the I8042_MMIO registers from i8042_mm_init() to the MIPS magnum
machine (which is its only user).
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-29-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:42 +0000 (14:40 +0100)]
pckbd: alter i8042_mm_init() to return a I8042_MMIO device
This exposes the I8042_MMIO device to the caller to allow the register memory
region to be mapped outside of i8042_mm_init().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-28-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:41 +0000 (14:40 +0100)]
pckbd: implement i8042_mmio_init() function
This enables use to set the required value of extended_state directly during
device init rather than in i8042_mm_init().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-27-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:40 +0000 (14:40 +0100)]
pckbd: implement i8042_mmio_realize() function
Move the initialisation of the register memory region to the I8042_MMIO device
realize function and expose it using sysbus_init_mmio().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-26-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:39 +0000 (14:40 +0100)]
pckbd: add size qdev property to I8042_MMIO device
This will soon be used to set the size of the register memory region using a
qdev property.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-25-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:38 +0000 (14:40 +0100)]
pckbd: add mask qdev property to I8042_MMIO device
This allows the KBDState mask value to be set using a qdev property rather
than directly in i8042_mm_init().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-24-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:37 +0000 (14:40 +0100)]
pckbd: implement i8042_mmio_reset() for I8042_MMIO device
This allows the I8042_MMIO reset function to be registered directly within the
DeviceClass rather than using qemu_register_reset() directly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-23-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:36 +0000 (14:40 +0100)]
pckbd: introduce new I8042_MMIO QOM type
Currently i8042_mm_init() creates a new KBDState directly which is used by the MIPS
magnum machine. Introduce a new I8042_MMIO QOM type that will soon be used to
allow the MIPS magnum machine to be wired up using standard qdev GPIOs.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Helge Deller <deller@gmx.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <
20220624134109.881989-22-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:35 +0000 (14:40 +0100)]
pckbd: move ISAKBDState from pckbd.c to i8042.h
This allows the QOM types in pckbd.c to be used elsewhere by simply including
i8042.h.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-21-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:34 +0000 (14:40 +0100)]
pckbd: move KBDState from pckbd.c to i8042.h
This allows the QOM types in pckbd.c to be used elsewhere by simply including
i8042.h.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-20-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:33 +0000 (14:40 +0100)]
pckbd: checkpatch fixes
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-19-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:32 +0000 (14:40 +0100)]
lasips2: rename ps2dev_update_irq() to lasips2_port_set_irq()
This better reflects that the IRQ input opaque is a LASIPS2Port structure
and not a PS2_DEVICE.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-18-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:31 +0000 (14:40 +0100)]
lasips2: spacing fixes
This helps improve the readability of lasips2.c.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-17-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:30 +0000 (14:40 +0100)]
pl050: split pl050_update_irq() into separate pl050_set_irq() and pl050_update_irq() functions
This will soon allow pl050_set_irq() to be used as a GPIO input function.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-16-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:29 +0000 (14:40 +0100)]
pl050: checkpatch fixes
This patch also includes a couple of minor spacing updates.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-15-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:28 +0000 (14:40 +0100)]
ps2: don't use vmstate_register() in ps2_mouse_init()
Since PS2_MOUSE_DEVICE is a qdev device then vmstate_ps2_mouse can be registered
using the DeviceClass vmsd field instead. There is no need to use
qdev_set_legacy_instance_id() to ensure migration compatibility since the first 2
parameters to vmstate_register() are NULL and 0 respectively.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-14-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:27 +0000 (14:40 +0100)]
ps2: don't use vmstate_register() in ps2_kbd_init()
Since PS2_KBD_DEVICE is a qdev device then vmstate_ps2_keyboard can be registered
using the DeviceClass vmsd field instead. There is no need to use
qdev_set_legacy_instance_id() to ensure migration compatibility since the first 2
parameters to vmstate_register() are NULL and 0 respectively.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-13-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:26 +0000 (14:40 +0100)]
ps2: implement ps2_mouse_realize() and use it to register ps2_mouse_handler
Move the registration of ps2_mouse_handler from ps2_mouse_init() to a new
ps2_mouse_realize() function. Since the abstract PS2_DEVICE parent class doesn't
have a realize() function then it is not necessary to store the reference to
it in PS2DeviceClass and use device_class_set_parent_realize().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-12-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:25 +0000 (14:40 +0100)]
ps2: implement ps2_kbd_realize() and use it to register ps2_keyboard_handler
Move the registration of ps2_keyboard_handler from ps2_kbd_init() to a new
ps2_kbd_realize() function. Since the abstract PS2_DEVICE parent class doesn't
have a realize() function then it is not necessary to store the reference to
it in PS2DeviceClass and use device_class_set_parent_realize().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-11-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:24 +0000 (14:40 +0100)]
ps2: remove duplicate setting of scancode_set in ps2_kbd_init()
The default value for scancode_set is already set in ps2_kbd_reset() so there is no
need to duplicate this in ps2_kbd_init().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-10-mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland [Fri, 24 Jun 2022 13:40:23 +0000 (14:40 +0100)]
ps2: implement ps2_reset() for the PS2_DEVICE QOM type based upon ps2_common_reset()
The functionality of ps2_common_reset() can be moved into a new ps2_reset() function
for the PS2_DEVICE QOM type. Update PS2DeviceClass to hold a reference to the parent
reset function and update the PS2_KBD_DEVICE and PS2_MOUSE_DEVICE types to use
device_class_set_parent_reset() accordingly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Helge Deller <deller@gmx.de>
Message-Id: <
20220624134109.881989-9-mark.cave-ayland@ilande.co.uk>