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Konstantin Zhuravlyov [Wed, 20 Mar 2019 19:44:47 +0000 (19:44 +0000)]
AMDHSA: Fix COMPUTE_PGM_RSRC2.USER_SGPR calculation when parsing ISA assembly
It must match https://llvm.org/docs/AMDGPUUsage.html#initial-kernel-execution-state
Differential Revision: https://reviews.llvm.org/D59570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356603
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Eli Friedman [Wed, 20 Mar 2019 19:40:45 +0000 (19:40 +0000)]
[ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1.
This takes sequences like "mov r4, sp; str r0, [r4]", and optimizes them
to something like "str r0, [sp]".
For regular stack variables, this optimization was already implemented:
we lower loads and stores using frame indexes, which are expanded later.
However, when constructing a call frame for a call with more than four
arguments, the existing optimization doesn't apply. We need to use
stores which are actually relative to the current value of sp, and don't
have an associated frame index.
This patch adds a special case to handle that construct. At the DAG
level, this is an ISD::STORE where the address is a CopyFromReg from SP
(plus a small constant offset).
This applies only to Thumb1: in Thumb2 or ARM mode, a regular store
instruction can access SP directly, so the COPY gets eliminated by
existing code.
The change to ARMDAGToDAGISel::SelectThumbAddrModeSP is a related
cleanup: we shouldn't pretend that it can select anything other than
frame indexes.
Differential Revision: https://reviews.llvm.org/D59568
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356601
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Rafael Auler [Wed, 20 Mar 2019 19:20:07 +0000 (19:20 +0000)]
[Linker] Fix crash handling appending linkage
Summary:
When linking two llvm.used arrays, if the resulting merged
array ends up with duplicated elements (with the same name) but with
different types, the IRLinker was crashing. This was supposed to be
legal, as the IRLinker bitcasts elements to match types in these
situations.
This bug was exposed by D56928 in clang to support attribute used
in member functions of class templates. Crash happened when self-hosting
with LTO. Since LLVM depends on attribute used to generate code
for the dump() method, ubiquitous in the code base, many input bc
had a definition of this method referenced in their llvm.used array.
Some of these classes got optimized, changing the type of the first
parameter (this) in the dump method, leading to a scenario with a
pool of valid definitions but some with a different type, triggering
this bug.
This is a memory bug: ValueMapper depends on (calls) the materializer
provided by IRLinker, and this materializer was freely calling RAUW
methods whenever a global definition was updated in the temporary merged
output file. However, replaceAllUsesWith may or may not destroy
constants that use this global. If the linked definition has a type
mismatch regarding the new def and the old def, the materializer would
bitcast the old type to the new type and the elements of the llvm.used
array, which already uses bitcast to i8*, would end up with elements
cascading two bitcasts. RAUW would then indirectly call the
constantfolder to update the constant to the new ref, which would,
instead of updating the constant, destroy it to be able to create
a new constant that folds the two bitcasts into one. The problem is that
ValueMapper works with pointers to the same constants that may be
getting destroyed by RAUW. Obviously, RAUW can update references in the
Module to do not use the old destroyed constant, but it can't update
ValueMapper's internal pointers to these constants, which are now
invalid.
The approach here is to move the task of RAUWing old definitions
outside of the materializer.
Test Plan:
Added LIT test case, tested clang self-hosting with D56928 and
verified it works
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D59552
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356597
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Alina Sbirlea [Wed, 20 Mar 2019 19:18:55 +0000 (19:18 +0000)]
[NFC] Fix brace indentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356596
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Robert Lougher [Wed, 20 Mar 2019 19:08:18 +0000 (19:08 +0000)]
Resubmit r356511 "[TailCallElim] Add tailcall elimination pass to LTO pipelines"
Failing LLD tests have been fixed in r356593.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356594
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Tim Renouf [Wed, 20 Mar 2019 18:47:21 +0000 (18:47 +0000)]
[AMDGPU] Added MsgPack format PAL metadata
Summary:
PAL metadata now supports both the old linear reg=val pairs format and
the new MsgPack format.
The MsgPack format uses YAML as its textual representation. On output to
YAML, a mnemonic name is provided for some hardware registers.
Differential Revision: https://reviews.llvm.org/D57028
Change-Id: I2bbaabaaca4b3574f7e03b80fbef7c7a69d06a94
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356591
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Philip Reames [Wed, 20 Mar 2019 18:44:58 +0000 (18:44 +0000)]
Simplify operands of masked stores and scatters based on demanded elements
If we know we're not storing a lane, we don't need to compute the lane. This could be improved by using the undef element result to further prune the mask, but I want to separate that into its own change since it's relatively likely to expose other problems.
Differential Revision: https://reviews.llvm.org/D57247
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356590
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Alina Sbirlea [Wed, 20 Mar 2019 18:33:37 +0000 (18:33 +0000)]
[LICM & MemorySSA] Don't sink/hoist stores in the presence of ordered loads.
Summary:
Before this patch, if any Use existed in the loop, with a defining
access in the loop, we conservatively decide to not move the store.
What this approach was missing, is that ordered loads are not Uses, they're Defs
in MemorySSA. So, even when the clobbering walker does not find that
volatile load to interfere, we still cannot hoist a store past a
volatile load.
Resolves PR41140.
Reviewers: george.burgess.iv
Subscribers: sanjoy, jlebar, Prazek, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59564
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356588
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Nikita Popov [Wed, 20 Mar 2019 18:16:02 +0000 (18:16 +0000)]
[ValueTracking] Compute range for abs without nsw
This is a small followup to D59511. The code that was moved into
computeConstantRange() there is a bit overly conversative: If the
abs is not nsw, it does not compute any range. However, abs without
nsw still has a well-defined contiguous unsigned range from 0 to
SIGNED_MIN. This is a lot less useful than the usual 0 to SIGNED_MAX
range, but if we're already here we might as well specify it...
Differential Revision: https://reviews.llvm.org/D59563
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356586
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Nikita Popov [Wed, 20 Mar 2019 18:00:27 +0000 (18:00 +0000)]
[InstCombine] Fold add nuw + uadd.with.overflow
Fold add nuw and uadd.with.overflow with constants if the
addition does not overflow.
Part of https://bugs.llvm.org/show_bug.cgi?id=38146.
Patch by Dan Robertson.
Differential Revision: https://reviews.llvm.org/D59471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356584
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Jordan Rupprecht [Wed, 20 Mar 2019 17:44:24 +0000 (17:44 +0000)]
[Remarks] Fix mismatched delete due to missing virtual destructor
This fixes an asan failure introduced in r356519.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356583
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Tim Renouf [Wed, 20 Mar 2019 17:42:00 +0000 (17:42 +0000)]
[AMDGPU] Factored PAL metadata handling out into its own class
Summary:
This commit introduces a new AMDGPUPALMetadata class that:
* is inside the AMDGPU target;
* keeps an in-memory representation of PAL metadata;
* provides a method to read the frontend-supplied metadata from LLVM IR;
* provides methods for the asm printer to set metadata items;
* provides methods to write the metadata as a binary blob to put in a
.note record or as an asm directive;
* provides a method to read the metadata as a binary blob from a .note
record.
Because llvm-readobj cannot call directly into a target, I had to remove
llvm-readobj's ability to dump PAL metadata, pending a resolution to
https://reviews.llvm.org/D52821
Differential Revision: https://reviews.llvm.org/D57027
Change-Id: I756dc830894fcb6850324cdcfa87c0120eb2cf64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356582
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Nico Weber [Wed, 20 Mar 2019 17:26:11 +0000 (17:26 +0000)]
Remove HAVE_REALPATH from config.h
Its last use was removed in r352916.
No behavior change.
Differential Revision: https://reviews.llvm.org/D59601
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356579
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Dmitry Preobrazhensky [Wed, 20 Mar 2019 17:13:58 +0000 (17:13 +0000)]
[AMDGPU][MC] Corrected checks for DS offset0 range
See bug 40889: https://bugs.llvm.org/show_bug.cgi?id=40889
Reviewers: artem.tamazov, arsenm
Differential Revision: https://reviews.llvm.org/D59313
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356576
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Sanjay Patel [Wed, 20 Mar 2019 16:47:53 +0000 (16:47 +0000)]
[CGP] fix formatting; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356572
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Clement Courbet [Wed, 20 Mar 2019 16:14:59 +0000 (16:14 +0000)]
Fix sanitizer failures for 356550.
Mark bcmp as having optimized codegen, so that asan can detect it and
mark users as nobuiltin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356568
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Nico Weber [Wed, 20 Mar 2019 16:14:16 +0000 (16:14 +0000)]
gn build: Add build files for some clang-tools-extra
Adds clang-change-namespace, clang-move, clang-query,
clang-reorder-fields.
Differential Revision: https://reviews.llvm.org/D59554
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356567
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Sanjay Patel [Wed, 20 Mar 2019 15:53:06 +0000 (15:53 +0000)]
[CGP] convert chain of 'if' to 'switch'; NFC
This should be extended, but CGP does some strange things,
so I'm intentionally not changing the potential order of
any transforms yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356566
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Nico Weber [Wed, 20 Mar 2019 15:41:25 +0000 (15:41 +0000)]
gn build: Merge r356508
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356563
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Dmitry Preobrazhensky [Wed, 20 Mar 2019 15:40:52 +0000 (15:40 +0000)]
[AMDGPU][MC][GFX9] Added support of operands shared_base, shared_limit, private_base, private_limit, pops_exiting_wave_id
See bug 39297: https://bugs.llvm.org/show_bug.cgi?id=39297
Reviewers: artem.tamazov, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D59290
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356561
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Nico Weber [Wed, 20 Mar 2019 15:36:11 +0000 (15:36 +0000)]
gn build: Merge r356519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356560
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Sanjay Patel [Wed, 20 Mar 2019 15:02:35 +0000 (15:02 +0000)]
[CGP][x86] add tests for usubo regression (PR41129); NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356559
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Sjoerd Meijer [Wed, 20 Mar 2019 14:33:39 +0000 (14:33 +0000)]
Follow up of rL356555
Pacify buildbot that complained about a member function not marked with
override.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356557
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Sjoerd Meijer [Wed, 20 Mar 2019 14:15:46 +0000 (14:15 +0000)]
[TTI] getMemcpyCost
This adds new function getMemcpyCost to TTI so that the cost of a memcpy can be
modeled and queried. The default implementation returns Expensive, but targets
can override this function to model the cost more accurately.
Differential Revision: https://reviews.llvm.org/D59252
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356555
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George Rimar [Wed, 20 Mar 2019 13:57:47 +0000 (13:57 +0000)]
[llvm-objcopy] - Use replaceSectionReferences to update the sections for symbols in symbol table.
If the compression was used and we had a symbol not involved in relocation,
we never updated its section and it was silently removed from the output.
Differential revision: https://reviews.llvm.org/D59542
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356554
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Simon Pilgrim [Wed, 20 Mar 2019 12:24:15 +0000 (12:24 +0000)]
Remove out of date comment. NFCI.
DAGCombiner::convertBuildVecZextToZext just requires the extractions to be sequential, they don't have to start from 0'th index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356552
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Clement Courbet [Wed, 20 Mar 2019 11:51:11 +0000 (11:51 +0000)]
[ExpandMemCmp] Trigger on bcmp too.
Summary: Fixes 41150.
Reviewers: gchatelet
Subscribers: hiraditya, llvm-commits, ckennelly, sbenza, jyknight
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59593
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356550
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Simon Pilgrim [Wed, 20 Mar 2019 11:41:52 +0000 (11:41 +0000)]
[X86] Use getConstantOperandAPInt to detect out-of-range shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356549
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Andrea Di Biagio [Wed, 20 Mar 2019 11:21:15 +0000 (11:21 +0000)]
[X86] Remove X86 specific dag nodes for RDTSC/RDTSCP/RDPMC. NFCI
This patch removes the following dag node opcodes from namespace X86ISD:
RDTSC_DAG,
RDTSCP_DAG,
RDPMC_DAG
The logic that expands RDTSC/RDPMC/XGETBV intrinsics is basically the same. The
only differences are:
RDTSC/RDTSCP don't implicitly read ECX.
RDTSCP also implicitly writes ECX.
I moved the common expansion logic into a helper function with the goal to get
rid of code repetition. That helper is now used for the expansion of
RDTSC/RDTSCP/RDPMC/XGETBV intrinsics.
No functional change intended.
Differential Revision: https://reviews.llvm.org/D59547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356546
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Sylvestre Ledru [Wed, 20 Mar 2019 10:02:18 +0000 (10:02 +0000)]
[perf][DebugInfo] follow up for "add SectionedAddress to DebugInfo interfaces"
Summary: Fix the build failure when perf jit is enabled
Reviewers: avl, dblaikie
Reviewed By: avl
Subscribers: modocache, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59189
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356542
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David Stuttard [Wed, 20 Mar 2019 09:29:55 +0000 (09:29 +0000)]
[AMDGPU] Allow MIMG with no uses in adjustWritemask in isel
Summary:
If an MIMG instruction has managed to get through to adjustWritemask in isel but
has no uses (and doesn't enable TFC) then prevent an assertion by not attempting
to adjust the writemask.
The instruction will be removed anyway.
Change-Id: I9a5dba6bafe1f35ac99c1b73df390936e2ac27a7
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D58964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356540
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Philip Reames [Wed, 20 Mar 2019 03:36:05 +0000 (03:36 +0000)]
[instcombine] Add todos describing missing transforms for masked.* intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356536
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Craig Topper [Wed, 20 Mar 2019 03:13:28 +0000 (03:13 +0000)]
[X86] Remove X32 check lines from a test that doesn't have an X32 FileCheck prefix. Regenerate the test using update_llc_test_checks. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356535
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Douglas Yung [Wed, 20 Mar 2019 01:52:40 +0000 (01:52 +0000)]
Retry to add workaround to build scoped enums with VS2015. NFCI.
We need this as we still have internal build bots on VS2015.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356534
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Douglas Yung [Wed, 20 Mar 2019 00:41:12 +0000 (00:41 +0000)]
Revert "Add workaround to build scoped enums with VS2015. NFCI."
This reverts commit
6080a6fb1949a2bdf053245d6062c7bf58dae7a6 (r356532).
Clang does not accept this syntax, so reverting this until I can find something that works across all compilers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356533
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Douglas Yung [Wed, 20 Mar 2019 00:26:56 +0000 (00:26 +0000)]
Add workaround to build scoped enums with VS2015. NFCI.
We need this as we still have internal build bots on VS2015.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356532
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Craig Topper [Tue, 19 Mar 2019 23:57:16 +0000 (23:57 +0000)]
[X86] Re-disable cmpxchg16b for 32-bit mode assembly parsing.
This was broken recently when I factored the 64 bit mode check into hasCmpxchg16 without thinking about the AssemblerPredicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356531
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Eli Friedman [Tue, 19 Mar 2019 21:48:08 +0000 (21:48 +0000)]
[ARM] Make sure to save/restore LR when we use tBfar.
This change does two things. One, it ensures compilation will abort
instead of miscompiling if ARMFrameLowering::determineCalleeSaves
chooses not to save LR in a case where it's necessary. Two, it changes
the way we estimate the size of a function to be more conservative in
the presence of constant pool entries and jump tables.
EstimateFunctionSizeInBytes probably still isn't really conservative
enough, but I'm not sure how we can come up with a reliable estimate
before constant islands runs.
Differential Revision: https://reviews.llvm.org/D59439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356527
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Amara Emerson [Tue, 19 Mar 2019 21:43:05 +0000 (21:43 +0000)]
[AArch64][GlobalISel] Add an optimization to select vector DUP instructions.
This adds pattern matching for the insert+shufflevector sequence so we can
generate dup instructions instead of the current TBL sequence.
Differential Revision: https://reviews.llvm.org/D59558
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356526
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Amara Emerson [Tue, 19 Mar 2019 21:43:02 +0000 (21:43 +0000)]
[AArch64][GlobalISel] Make v4s32 G_IMPLICIT_DEF legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356525
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Reid Kleckner [Tue, 19 Mar 2019 21:40:59 +0000 (21:40 +0000)]
Remove MSVC compat hack since the inline keyword was added in 2015
Our minimum MSVC toolchain requirement is greater than 2015, so we don't
need this conditional macro anymore. New versions of MSVC apparently
have a header, xkeycheck.h, to check that keywords haven't been
redefined.
Fixes PR41144
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356524
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Francis Visoiu Mistrih [Tue, 19 Mar 2019 21:32:03 +0000 (21:32 +0000)]
[Remarks] Fix gcc build for r356519
Fails here:
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/20046/steps/build%20stage%201/logs/stdio
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356522
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Florian Hahn [Tue, 19 Mar 2019 21:18:59 +0000 (21:18 +0000)]
[DwarfDebug] Add triple to test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356521
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Nikita Popov [Tue, 19 Mar 2019 21:12:21 +0000 (21:12 +0000)]
[InstSimplify] Add additional cmp of abs without nsw tests; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356520
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Francis Visoiu Mistrih [Tue, 19 Mar 2019 21:11:07 +0000 (21:11 +0000)]
Reland "[Remarks] Add a new Remark / RemarkParser abstraction"
This adds a Remark class that allows us to share code when working with
remarks.
The C API has been updated to reflect this. Instead of the parser
generating C structs, it's now using a C++ object that is used through
opaque pointers in C. This gives us much more flexibility on what
changes we can make to the internal state of the object and interacts
much better with scenarios where the library is used through dlopen.
* C API updates:
* move from C structs to opaque pointers and functions
* the remark type is now an enum instead of a string
* unit tests updates:
* use mostly the C++ API
* keep one test for the C API
* rename to YAMLRemarksParsingTest
* a typo was fixed: AnalysisFPCompute -> AnalysisFPCommute.
* a new error message was added: "expected a remark tag."
* llvm-opt-report has been updated to use the C++ parser instead of the
C API
Differential Revision: https://reviews.llvm.org/D59049
Original llvm-svn: 356491
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356519
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Robert Lougher [Tue, 19 Mar 2019 20:54:20 +0000 (20:54 +0000)]
Revert r356511 "[TailCallElim] Add tailcall elimination pass to LTO pipelines"
Due to buildbot failures (LLD tests).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356516
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Florian Hahn [Tue, 19 Mar 2019 20:37:06 +0000 (20:37 +0000)]
[DwarfDebug] Skip entries to big for 16 bit size field in Dwarf < 5.
Nothing prevents entries from being bigger than the 16 bit size field in
Dwarf < 5. For entries that are too big, just emit an empty entry
instead of crashing.
This fixes PR41038.
Reviewers: probinson, aprantl, davide
Reviewed By: probinson
Differential Revision: https://reviews.llvm.org/D59518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356514
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Robert Lougher [Tue, 19 Mar 2019 20:24:28 +0000 (20:24 +0000)]
[TailCallElim] Add tailcall elimination pass to LTO pipelines
LTO provides additional opportunities for tailcall elimination due to
link-time inlining and visibility of nocapture attribute. Testing showed
negligible impact on compilation times.
Differential Revision: https://reviews.llvm.org/D58391
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356511
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Philip Reames [Tue, 19 Mar 2019 20:10:00 +0000 (20:10 +0000)]
Demanded elements support for masked.load and masked.gather
Teach instcombine to propagate demanded elements through a masked load or masked gather instruction. This is in the broader context of improving vector pointer instcombine under https://reviews.llvm.org/D57140.
Differential Revision: https://reviews.llvm.org/D57372
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356510
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Matt Arsenault [Tue, 19 Mar 2019 19:33:12 +0000 (19:33 +0000)]
CodeGen: Refactor regallocator command line and target selection
This will allow targets more flexibility to replace the
register allocator core passes. In a future commit,
AMDGPU will run the core register assignment passes
twice, and will also want to disallow using the
standard -regalloc option.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356506
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Matt Arsenault [Tue, 19 Mar 2019 19:16:04 +0000 (19:16 +0000)]
RegAllocFast: Do not allocate registers for undef uses
Do not actually allocate a register for an undef use. Previously we we
would create unnecessary reload instruction for undef uses where the
register wasn't live.
Patch by Matthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356501
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Matt Arsenault [Tue, 19 Mar 2019 19:01:34 +0000 (19:01 +0000)]
RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
The 2nd loop calculates spill costs but reports free registers as cost
0 anyway, so there is little benefit from having a separate early
loop.
Surprisingly this is not NFC, as many register are marked regDisabled
so the first loop often picks up later registers unnecessarily instead
of the first one available in the allocation order...
Patch by Matthias Braun
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356499
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Simon Pilgrim [Tue, 19 Mar 2019 18:55:46 +0000 (18:55 +0000)]
Fix for ABS legalization on PPC buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356498
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Philip Reames [Tue, 19 Mar 2019 18:27:18 +0000 (18:27 +0000)]
Allow unordered loads to be considered invariant in CodeGen
The actual code change is fairly straight forward, but exercising it isn't. First, it turned out we weren't adding the appropriate flags in SelectionDAG. Second, it turned out that we've got some optimization gaps, so obvious test cases don't work.
My first attempt (in atomic-unordered.ll) points out a deficiency in our peephole-opt folding logic which I plan to fix separately. Instead, I'm exercising this through MachineLICM.
Differential Revision: https://reviews.llvm.org/D59375
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356494
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Francis Visoiu Mistrih [Tue, 19 Mar 2019 18:21:43 +0000 (18:21 +0000)]
Revert "[Remarks] Add a new Remark / RemarkParser abstraction"
This reverts commit
51dc6a8c84cd6a58562e320e1828a0158dbbf750.
Breaks
http://lab.llvm.org:8011/builders/clang-cmake-x86_64-sde-avx512-linux/builds/20034/steps/build%20stage%201/logs/stdio.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356492
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Francis Visoiu Mistrih [Tue, 19 Mar 2019 18:09:51 +0000 (18:09 +0000)]
[Remarks] Add a new Remark / RemarkParser abstraction
This adds a Remark class that allows us to share code when working with
remarks.
The C API has been updated to reflect this. Instead of the parser
generating C structs, it's now using a C++ object that is used through
opaque pointers in C. This gives us much more flexibility on what
changes we can make to the internal state of the object and interacts
much better with scenarios where the library is used through dlopen.
* C API updates:
* move from C structs to opaque pointers and functions
* the remark type is now an enum instead of a string
* unit tests updates:
* use mostly the C++ API
* keep one test for the C API
* rename to YAMLRemarksParsingTest
* a typo was fixed: AnalysisFPCompute -> AnalysisFPCommute.
* a new error message was added: "expected a remark tag."
* llvm-opt-report has been updated to use the C++ parser instead of the
C API
Differential Revision: https://reviews.llvm.org/D59049
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356491
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Nikita Popov [Tue, 19 Mar 2019 17:53:56 +0000 (17:53 +0000)]
[ValueTracking] Use computeConstantRange() for unsigned add/sub overflow
Improve computeOverflowForUnsignedAdd/Sub in ValueTracking by
intersecting the computeConstantRange() result into the ConstantRange
created from computeKnownBits(). This allows us to detect some
additional never/always overflows conditions that can't be determined
from known bits.
This revision also adds basic handling for constants to
computeConstantRange(). Non-splat vectors will be handled in a followup.
The signed case will also be handled in a followup, as it needs some
more groundwork.
Differential Revision: https://reviews.llvm.org/D59386
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356489
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Peter Collingbourne [Tue, 19 Mar 2019 17:30:59 +0000 (17:30 +0000)]
gn build: Merge r356387.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356485
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Peter Collingbourne [Tue, 19 Mar 2019 17:30:50 +0000 (17:30 +0000)]
gn build: Merge r356451.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356484
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Simon Pilgrim [Tue, 19 Mar 2019 17:23:25 +0000 (17:23 +0000)]
[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - handle repeated shift amounts
If a value with multiple uses is only ever used for SSE shift amounts then we know that only the bottom 64-bits are needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356483
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Philip Reames [Tue, 19 Mar 2019 17:20:49 +0000 (17:20 +0000)]
[AtomicExpand] Fix a crash bug when lowering unordered loads to cmpxchg
Add tests for wider atomic loads and stores. In the process, fix a crasher where we appearently handled unorder stores, but not loads, when lowering to cmpxchg idioms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356482
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Simon Atanasyan [Tue, 19 Mar 2019 17:01:24 +0000 (17:01 +0000)]
[MIPS][microMIPS] Enable dynamic stack realignment
Dynamic stack realignment was disabled on micromips by checking if
target has standard encoding. We simply change the condition to skip
Mips16 only.
Patch by Mirko Brkusanin.
Differential Revision: http://reviews.llvm.org/D59499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356478
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Jordan Rupprecht [Tue, 19 Mar 2019 16:52:40 +0000 (16:52 +0000)]
[NFC] Fix unused variable in release builds
This was introduced in rL356468.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356477
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Justin Bogner [Tue, 19 Mar 2019 16:52:00 +0000 (16:52 +0000)]
[DAGCombine] Fix a miscompile when reducing BUILD_VECTORs to a shuffle
In r311255 we added a case where we split vectors whose elements are
all derived from the same input vector so that we could shuffle it
more efficiently. In doing so, createBuildVecShuffle was taught to
adjust for the fact that all indices would be based off of the first
vector when this happens, but it's possible for the code that checked
that to fire incorrectly if we happen to have a BUILD_VECTOR of
extracts from subvectors and don't hit this new optimization.
Instead of trying to detect if we've split the vector by checking if
we have extracts from the same base vector, we can just pass that
information into createBuildVecShuffle, avoiding the miscompile.
Differential Revision: https://reviews.llvm.org/D59507
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356476
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Simon Pilgrim [Tue, 19 Mar 2019 16:49:59 +0000 (16:49 +0000)]
Fix unused variable warning. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356474
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Philip Reames [Tue, 19 Mar 2019 16:46:56 +0000 (16:46 +0000)]
[Tests] Update to newer ISA
There are some issues w/missed opts on older platforms, but that's not the purpose of this test. Using a newer API points out that some TODOs are already handled, and allows addition of tests to exercise other issues (future patch.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356473
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Sanjay Patel [Tue, 19 Mar 2019 16:39:17 +0000 (16:39 +0000)]
[InstCombine] fold logic-of-nan-fcmps (PR41069)
Combine 2 fcmps that are checking for nan-ness:
and (fcmp ord X, 0), (and (fcmp ord Y, 0), Z) --> and (fcmp ord X, Y), Z
or (fcmp uno X, 0), (or (fcmp uno Y, 0), Z) --> or (fcmp uno X, Y), Z
This is an exact match for a minimal reassociation pattern.
If we want to handle this more generally that should go in
the reassociate pass and allow removing this code.
This should fix:
https://bugs.llvm.org/show_bug.cgi?id=41069
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356471
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Neil Henning [Tue, 19 Mar 2019 16:32:24 +0000 (16:32 +0000)]
[AMDGPU] Add convergent attribute to WWM.
Add the convergent attribute to the WWM intrinsic to stop it ever being
sunk out of cfg.
Differential Revision: https://reviews.llvm.org/D59536
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356470
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Simon Pilgrim [Tue, 19 Mar 2019 16:24:55 +0000 (16:24 +0000)]
[SelectionDAG] Handle unary SelectPatternFlavor for ABS case in SelectionDAGBuilder::visitSelect
These changes are related to PR37743 and include:
SelectionDAGBuilder::visitSelect handles the unary SelectPatternFlavor::SPF_ABS case to build ABS node.
Delete the redundant recognizer of the integer ABS pattern from the DAGCombiner.
Add promoting the integer ABS node in the LegalizeIntegerType.
Expand-based legalization of integer result for the ABS nodes.
Expand-based legalization of ABS vector operations.
Add some integer abs testcases for different typesizes for Thumb arch
Add the custom ABS expanding and change the SAD pattern recognizer for X86 arch: The i64 result of the ABS is expanded to:
tmp = (SRA, Hi, 31)
Lo = (UADDO tmp, Lo)
Hi = (XOR tmp, (ADDCARRY tmp, hi, Lo:1))
Lo = (XOR tmp, Lo)
The "detectZextAbsDiff" function is changed for the recognition of pattern with the ABS node. Given a ABS node, detect the following pattern:
(ABS (SUB (ZERO_EXTEND a), (ZERO_EXTEND b))).
Change integer abs testcases for codegen with the ABS node support for AArch64.
Indicate that the ABS is legal for the i64 type when the NEON is supported.
Change the integer abs testcases to show changing of codegen.
Add combine and legalization of ABS nodes for Thumb arch.
Extend 'matchSelectPattern' to recognize the ABS patterns with ICMP_SGE condition.
For discussion, see https://bugs.llvm.org/show_bug.cgi?id=37743
Patch by: @ikulagin (Ivan Kulagin)
Differential Revision: https://reviews.llvm.org/D49837
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356468
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Jordan Rupprecht [Tue, 19 Mar 2019 16:09:54 +0000 (16:09 +0000)]
[llvm-ar] Support N [count] modifier
Summary:
GNU ar supports the 'N' count modifier for the extract (x) and delete (d) operations. When an archive contains multiple members with the same name, this can be used to extract (or delete) them individually. For example:
```
$ llvm-ar t archive.a
foo
foo
$ llvm-ar x archive.a
-> Writes foo twice, overwriting it the second time :( :(
$ llvm-ar xN 1 archive.a foo && mv foo foo.1
$ llvm-ar xN 2 archive.a foo && mv foo foo.2
-> Write foo twice, renaming it in between invocations to preserve all versions
```
Reviewers: ruiu, MaskRay
Reviewed By: ruiu, MaskRay
Subscribers: jdoerfert, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59503
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356466
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Ryan Taylor [Tue, 19 Mar 2019 16:07:00 +0000 (16:07 +0000)]
[AMDGPU] Add buffer/load 8/16 bit overloaded intrinsics
Summary:
Add buffer store/load 8/16 overloaded intrinsics for buffer, raw_buffer and struct_buffer
Change-Id: I166a29f071b2ff4e4683fb0392564b1f223ac61d
Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59265
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356465
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Neil Henning [Tue, 19 Mar 2019 15:50:24 +0000 (15:50 +0000)]
[AMDGPU] Ban i8 min3 promotion.
I found this really weird WWM-related case whereby through the WWM
transformations our isel lowering was trying to promote 2 min's into a
min3 for the i8 type, which our hardware doesn't support.
The new min3_i8.ll test case would previously spew the error:
PromoteIntegerResult #0: t69: i8 = SMIN3 t70, Constant:i8<0>, t68
Before the simple fix to our isel lowering to not do it for i8 MVT's.
Differential Revision: https://reviews.llvm.org/D59543
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356464
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Teresa Johnson [Tue, 19 Mar 2019 15:43:56 +0000 (15:43 +0000)]
[InstCombine] Add missing test for icmp transformation (NFC)
This was split out of D59378. There was no testing for the EQ case in
foldICmpWithDominatingICmp, add one here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356463
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Simon Atanasyan [Tue, 19 Mar 2019 15:15:35 +0000 (15:15 +0000)]
[mips] Fix crash on recursive using of .set
Switch to the `MCParserUtils::parseAssignmentExpression` for parsing
assignment expressions in the `.set` directive reduces code and allows
to print an error message instead of crashing in case of incorrect
recursive using of the `.set`.
Fix for the bug https://bugs.llvm.org/show_bug.cgi?id=41053.
Differential Revision: http://reviews.llvm.org/D59452
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356461
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Markus Lavin [Tue, 19 Mar 2019 15:15:28 +0000 (15:15 +0000)]
[DebugInfo] Move test files added in r356451
Moved the X86 dependant .ll tests added in r356451 from
test/DebugInfo/Generic to test/DebugInfo/X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356460
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Simon Pilgrim [Tue, 19 Mar 2019 14:08:23 +0000 (14:08 +0000)]
[InstSimplify] SimplifyICmpInst - icmp eq/ne %X, undef -> undef
As discussed on PR41125 and D59363, we have a mismatch between icmp eq/ne cases with an undef operand:
When the other operand is constant we fold to undef (handled in ConstantFoldCompareInstruction)
When the other operand is non-constant we fold to a bool constant based on isTrueWhenEqual (handled in SimplifyICmpInst).
Neither is really wrong, but this patch changes the logic in SimplifyICmpInst to consistently fold to undef.
The NewGVN test change is annoying (as with most heavily reduced tests) but AFAICT I have kept the purpose of the test based on rL291968.
Differential Revision: https://reviews.llvm.org/D59541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356456
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Petar Jovanovic [Tue, 19 Mar 2019 13:49:03 +0000 (13:49 +0000)]
[DebugInfoMetadata] Move main subprogram DIFlag into DISPFlags
Moving subprogram specific flags into DISPFlags makes IR code more readable.
In addition, we provide free space in DIFlags for other
'non-subprogram-specific' debug info flags.
Patch by Djordje Todorovic.
Differential Revision: https://reviews.llvm.org/D59288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356454
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Sanjay Patel [Tue, 19 Mar 2019 13:39:29 +0000 (13:39 +0000)]
[InstCombine] add FMF to tests for extra coverage; NFC
ninf is probably the only relevant possible flag here
(nnan allows simplification and nsz never makes a difference).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356453
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Markus Lavin [Tue, 19 Mar 2019 13:16:28 +0000 (13:16 +0000)]
[DebugInfo] Introduce DW_OP_LLVM_convert
Introduce a DW_OP_LLVM_convert Dwarf expression pseudo op that allows
for a convenient way to perform type conversions on the Dwarf expression
stack. As an additional bonus it paves the way for using other Dwarf
v5 ops that need to reference a base_type.
The new DW_OP_LLVM_convert is used from lib/Transforms/Utils/Local.cpp
to perform sext/zext on debug values but mainly the patch is about
preparing terrain for adding other Dwarf v5 ops that need to reference a
base_type.
For Dwarf v5 the op maps to DW_OP_convert and for earlier versions a
complex shift & mask pattern is generated to emulate sext/zext.
This is a recommit of r356442 with trivial fixes for the failing tests.
Differential Revision: https://reviews.llvm.org/D56587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356451
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Simon Pilgrim [Tue, 19 Mar 2019 11:44:22 +0000 (11:44 +0000)]
[InstCombine] Regenerate + add icmp with undef tests
Better test coverage for PR41125 and D59363
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356448
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Markus Lavin [Tue, 19 Mar 2019 09:17:28 +0000 (09:17 +0000)]
Revert "[DebugInfo] Introduce DW_OP_LLVM_convert"
This reverts commit
1cf4b593a7ebd666fc6775f3bd38196e8e65fafe.
Build bots found failing tests not detected locally.
Failing Tests (3):
LLVM :: DebugInfo/Generic/convert-debugloc.ll
LLVM :: DebugInfo/Generic/convert-inlined.ll
LLVM :: DebugInfo/Generic/convert-linked.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356444
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Serge Guelton [Tue, 19 Mar 2019 09:14:09 +0000 (09:14 +0000)]
Use response file when generating LLVM-C.dll
As discovered in D56774 the command line gets to long, so use a response file
to give the script the libs. This change has been tested and is confirmed
working for me.
Commited on behalf of Jakob Bornecrantz.
Differential Revision: https://reviews.llvm.org/D56781
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356443
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Markus Lavin [Tue, 19 Mar 2019 08:48:19 +0000 (08:48 +0000)]
[DebugInfo] Introduce DW_OP_LLVM_convert
Introduce a DW_OP_LLVM_convert Dwarf expression pseudo op that allows
for a convenient way to perform type conversions on the Dwarf expression
stack. As an additional bonus it paves the way for using other Dwarf
v5 ops that need to reference a base_type.
The new DW_OP_LLVM_convert is used from lib/Transforms/Utils/Local.cpp
to perform sext/zext on debug values but mainly the patch is about
preparing terrain for adding other Dwarf v5 ops that need to reference a
base_type.
For Dwarf v5 the op maps to DW_OP_convert and for earlier versions a
complex shift & mask pattern is generated to emulate sext/zext.
Differential Revision: https://reviews.llvm.org/D56587
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356442
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Heejin Ahn [Tue, 19 Mar 2019 05:26:33 +0000 (05:26 +0000)]
[WebAssembly] Small improvements in FixIrreducibleControlFlow (NFC)
Summary:
- Make some class member methods const
- Delete unnecessary includes
- Use a simpler form of `BuildMI`
Reviewers: kripken
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59454
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356440
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Heejin Ahn [Tue, 19 Mar 2019 05:10:39 +0000 (05:10 +0000)]
[WebAssembly] Improve readability of irreducibility tests
Summary:
This adds `preds` comment lines to BB names for readability, while also
fixes some of existing incorrect comment lines. Also deletes a few
unnecessary attributes. Autogenerated by `opt`.
Reviewers: kripken
Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356439
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Heejin Ahn [Tue, 19 Mar 2019 05:07:33 +0000 (05:07 +0000)]
[WebAssembly] Rename methods according to instruction name changes (NFC)
Reviewers: tlively, sbc100
Subscribers: dschuff, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59469
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356438
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Heejin Ahn [Tue, 19 Mar 2019 05:02:30 +0000 (05:02 +0000)]
[WebAssembly] Add immarg attribute to intrinsics
Summary:
After r355981, intrinsic arguments that are immediate values should be
marked as `ImmArg`.
Reviewers: dschuff, tlively
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59447
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356437
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Thomas Lively [Tue, 19 Mar 2019 00:55:34 +0000 (00:55 +0000)]
[WebAssembly] Lower SIMD nnan setcc nodes
Summary:
Adds patterns to lower all the remaining setcc modes: lt, gt,
le, and ge. Fixes PR40912.
Reviewers: aheejin, sbc100, dschuff
Reviewed By: dschuff
Subscribers: jgravelle-google, hiraditya, sunfish, jdoerfert, llvm-commits, srj
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59519
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356431
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Nikita Popov [Mon, 18 Mar 2019 22:26:27 +0000 (22:26 +0000)]
Revert "[ValueTracking][InstSimplify] Support min/max selects in computeConstantRange()"
This reverts commit
106f0cdefb02afc3064268dc7a71419b409ed2f3.
This change impacts the AMDGPU smed3.ll and umed3.ll codegen tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356424
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Kostya Serebryany [Mon, 18 Mar 2019 22:20:47 +0000 (22:20 +0000)]
[libFuzzer] document -len_control
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356422
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Craig Topper [Mon, 18 Mar 2019 22:06:19 +0000 (22:06 +0000)]
[X86] Add coverage for 16-bit and 64-bit versions of bsf/bsr/bt/btc/btr/bts in the assembly tests that are supposed to provide full coverage. Add coverage for cwtl/cltq/cwtd/cqto as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356420
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Craig Topper [Mon, 18 Mar 2019 22:06:14 +0000 (22:06 +0000)]
[X86] Disable CQTO and CLTQ instructions in the assembly parser outside 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356419
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Nikita Popov [Mon, 18 Mar 2019 21:35:19 +0000 (21:35 +0000)]
[ValueTracking][InstSimplify] Support min/max selects in computeConstantRange()
Add support for min/max flavor selects in computeConstantRange(),
which allows us to fold comparisons of a min/max against a constant
in InstSimplify. This was suggested by spatel as an alternative
approach to D59378. I've also added the infinite looping test from
that revision here.
Differential Revision: https://reviews.llvm.org/D59506
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356415
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Nikita Popov [Mon, 18 Mar 2019 21:35:09 +0000 (21:35 +0000)]
[InstCombine] Add tests for add nuw + uaddo; NFC
Baseline tests for D59471 (InstCombine of `add nuw` and `uaddo` with
constants).
Patch by Dan Robertson.
Differential Revision: https://reviews.llvm.org/D59472
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356414
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Craig Topper [Mon, 18 Mar 2019 21:33:59 +0000 (21:33 +0000)]
[X86] Allow any 8-bit immediate to be used with BT/BTC/BTR/BTS not just sign extended 8-bit immediates.
We need to allow [128,255] in addition to [-128, 127] to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356413
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Amara Emerson [Mon, 18 Mar 2019 21:29:21 +0000 (21:29 +0000)]
[GlobalISel] Include missing change from r356396
Forgot to add a change to relax some asserts in r356396.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356411
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Sam Clegg [Mon, 18 Mar 2019 21:21:12 +0000 (21:21 +0000)]
[WebAssembly] Don't override default implementation of isOffsetFoldingLegal. NFC.
The default implementation does we want and is going to more compatible
with dynamic linking (-fPIC) support that is planned.
This is NFC because currently we only build wasm with
`-relocation-model=static` which in turn means that the default
`isOffsetFoldingLegal` always returns true today.
Differential Revision: https://reviews.llvm.org/D54661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356410
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Nikita Popov [Mon, 18 Mar 2019 21:20:03 +0000 (21:20 +0000)]
[ValueTracking][InstSimplify] Move abs handling into computeConstantRange(); NFC
This is preparation for D59506. The InstructionSimplify abs handling
is moved into computeConstantRange(), which is the general place for
such calculations. This is NFC and doesn't affect the existing tests
in test/Transforms/InstSimplify/icmp-abs-nabs.ll.
Differential Revision: https://reviews.llvm.org/D59511
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356409
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Nikita Popov [Mon, 18 Mar 2019 21:19:56 +0000 (21:19 +0000)]
[InstSimplify] Add additional icmp of min/max tests; NFC
These are baseline tests for D59506.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356408
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Craig Topper [Mon, 18 Mar 2019 20:43:15 +0000 (20:43 +0000)]
[X86] Use relocImm in the ROL8ri/ROL16ri/ROL32ri/ROL64ri patterns to be consistent with the ROR patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356407
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