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Matt Arsenault [Tue, 5 Jun 2018 19:52:56 +0000 (19:52 +0000)]
AMDGPU: Preserve metadata when widening loads
Preserves the low bound of the !range. I don't think
it's legal to do anything with the top half since it's
theoretically reading garbage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334045
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Matt Arsenault [Tue, 5 Jun 2018 19:52:46 +0000 (19:52 +0000)]
AMDGPU: Use more custom insert/extract_vector_elt lowering
Apply to i8 vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334044
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Krzysztof Parzyszek [Tue, 5 Jun 2018 19:52:39 +0000 (19:52 +0000)]
[Hexagon] Add pattern to generate 64-bit neg instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334043
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Krzysztof Parzyszek [Tue, 5 Jun 2018 19:00:50 +0000 (19:00 +0000)]
[Hexagon] Add more patterns for generating abs/absp instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334038
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Michael Berg [Tue, 5 Jun 2018 18:49:47 +0000 (18:49 +0000)]
guard fneg with fmf sub flags
Summary: This change uses fmf subflags to guard optimizations as well as unsafe. These changes originated from D46483.
Reviewers: spatel, hfinkel
Reviewed By: spatel
Subscribers: nemanjai
Differential Revision: https://reviews.llvm.org/D47389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334037
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Michael Berg [Tue, 5 Jun 2018 18:12:25 +0000 (18:12 +0000)]
NFC: adding baseline fneg case for fmf
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334035
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Simon Dardis [Tue, 5 Jun 2018 17:53:22 +0000 (17:53 +0000)]
[mips] Fix the predicates for arithmetic operations
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47635
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334031
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Greg Bedwell [Tue, 5 Jun 2018 17:16:19 +0000 (17:16 +0000)]
[UpdateTestChecks] Error if --llvm-mca-binary gets an empty string
If the command line was mistyped like:
./update_mca_test_checks.py --llvm-mca-binary= /path/to/llvm-mca *.s
^-- extra whitespace
then /path/to/llvm-mca would get treated by argparse as a test-path
pattern and could actually be opened in write mode and overwritten.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334029
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Andrea Di Biagio [Tue, 5 Jun 2018 17:12:02 +0000 (17:12 +0000)]
[llvm-mca] Correctly update the CyclesLeft of a register read in the presence of partial register updates.
This patch fixe the logic in ReadState::cycleEvent(). That method was not
correctly updating field `TotalCycles`.
Added extra code comments in class ReadState to better describe each field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334028
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Fangrui Song [Tue, 5 Jun 2018 16:59:40 +0000 (16:59 +0000)]
Remove a self-referencing #include
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334027
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Simon Pilgrim [Tue, 5 Jun 2018 15:17:39 +0000 (15:17 +0000)]
[X86][SSE] Use multiplication scale factors for v8i16 SHL on pre-AVX2 targets.
Similar to v4i32 SHL, convert v8i16 shift amounts to scale factors instead to improve performance and reduce instruction count. We were already doing this for constant shifts, this adds variable shift support.
Reduces the serial nature of the codegen, which relies on chains of plendvb/pand+pandn+por shifts.
This is a step towards adding support for vXi16 vector rotates.
Differential Revision: https://reviews.llvm.org/D47546
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334023
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Nirav Dave [Tue, 5 Jun 2018 15:13:39 +0000 (15:13 +0000)]
[MC][X86] Allow assembler variable assignment to register name.
Summary:
Allow extended parsing of variable assembler assignment syntax and modify X86 to permit
VAR = register assignment. As we emit these as .set directives when possible, we inline
such expressions in output assembly.
Fixes PR37425.
Reviewers: rnk, void, echristo
Reviewed By: rnk
Subscribers: nickdesaulniers, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D47545
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334022
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Matt Arsenault [Tue, 5 Jun 2018 14:52:24 +0000 (14:52 +0000)]
DAG: Stop dropping invariant/dereferencable
When legalizing illegal FP load results, this was
for some reason dropping the invariant and dereferencable
memory flags. There doesn't seem to be any reason for this,
and the equivalent isn't done for integer loads.
Fixes an issue in a future AMDGPU commit where some identical
loads fail to merge because one of the loads ends up
dropping the flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334020
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John Brawn [Tue, 5 Jun 2018 14:10:55 +0000 (14:10 +0000)]
[InstCombine] Correct the cmp operand type used when canonicalizing abs/nabs
When adjusting a cmp in order to canonicalize an abs/nabs select pattern we need
to use the type of the existing operand when creating a new operand not the
type of a select operand, as the two may be different.
This fixes PR37686.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334019
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Gabor Buella [Tue, 5 Jun 2018 12:55:12 +0000 (12:55 +0000)]
[X86] NFC Fix typo introduced in r328016 HSI->HDI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334016
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Krzysztof Parzyszek [Tue, 5 Jun 2018 12:49:19 +0000 (12:49 +0000)]
[Hexagon] Minor cleanups in isel lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334015
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Hiroshi Inoue [Tue, 5 Jun 2018 11:58:01 +0000 (11:58 +0000)]
[PowerPC] reduce rotate in BitPermutationSelector
BitPermutationSelector builds the output value by repeating rotate-and-mask instructions with input registers.
Here, we may avoid one rotate instruction if we start building from an input register that does not require rotation.
For example of the test case bitfieldinsert.ll, it first rotates left r4 by 8 bits and then inserts some bits from r5 without rotation.
This can be executed by one rlwimi instruction, which rotates r4 by 8 bits and inserts its bits into r5.
This patch adds a check for rotation amounts in the comparator used in sorting to process the input without rotation first.
Differential Revision: https://reviews.llvm.org/D47765
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334011
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Simon Pilgrim [Tue, 5 Jun 2018 11:38:11 +0000 (11:38 +0000)]
[X86][SSE] Fix line endings for shuffle-vs-trunc tests. NFCI.
Strip native eol property which we don't use in this folder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334010
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Clement Courbet [Tue, 5 Jun 2018 10:56:19 +0000 (10:56 +0000)]
[llvm-exegesis] Add instructions to BenchmarkResult Key.
We want llvm-exegesis to explore instructions (effect of initial register values, effect of operand selection). To enable this a BenchmarkResult muststore all the relevant data in its key. This patch starts adding such data. Here we simply allow to store the generated instructions, following patches will add operands and initial values for registers.
https://reviews.llvm.org/D47764
Authored by: Guilluame Chatelet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334008
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Simon Pilgrim [Tue, 5 Jun 2018 10:52:29 +0000 (10:52 +0000)]
[X86][SSE] Add target shuffle support to X86TargetLowering::computeKnownBitsForTargetNode
Ideally we'd use resolveTargetShuffleInputs to handle faux shuffles as well but:
(a) that code path doesn't handle general/pre-legalized ops/types very well.
(b) I'm concerned about the compute time as they recurse to calls to computeKnownBits/ComputeNumSignBits which would need depth limiting somehow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334007
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Gabor Buella [Tue, 5 Jun 2018 10:41:39 +0000 (10:41 +0000)]
[X86] NFC Refactor some code in InstPrinters
Summary:
Bringing some come duplicated in the AT&T and the Intel printers
into a common parent class.
Reviewers: craig.topper
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D47682
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@334005
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Peter Smith [Tue, 5 Jun 2018 10:00:56 +0000 (10:00 +0000)]
[MC][ARM] Add range checking for Thumb2 resolved fixups.
When the branch target of a Thumb2 unconditional or conditonal branch is
resolved at assembly time, no range checking is performed on the result
leading to incorrect immediates. This change adds a range check:
+- 16 Megabytes for unconditional branches, +- 1 Megabyte for the
conditional branch.
Differential Revision: https://reviews.llvm.org/D46306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333997
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Simon Pilgrim [Tue, 5 Jun 2018 09:45:03 +0000 (09:45 +0000)]
[X86][SSE] Add basic PACKUS support to X86TargetLowering::computeKnownBitsForTargetNode
Helps improve analysis of saturation ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333995
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Peter Smith [Tue, 5 Jun 2018 09:32:28 +0000 (09:32 +0000)]
[MC][ARM] Correct Thumb BL instruction range
The Thumb BL range is + or - either 16 Megabytes or 4 Megabytes depending
on whether the CPU supports Thumb2 or the v8-m baseline ops. The existing
check for BL range is incorrectly set at +- 32 Megabytes. This change
corrects the higher range and uses the lower range if the featurebits
don't have the necessary support for it.
Differential Revision: https://reviews.llvm.org/D46305
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333991
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Alexander Ivchenko [Tue, 5 Jun 2018 09:22:30 +0000 (09:22 +0000)]
[X86][CET] Shadow stack fix for setjmp/longjmp
This is the new version of D46181, allowing setjmp/longjmp
to work correctly with the Intel CET shadow stack by storing
SSP on setjmp and fixing it on longjmp. The patch has been
updated to use the cf-protection-return module flag instead
of HasSHSTK, and the bug that caused D46181 to be reverted
has been fixed with the test expanded to track that fix.
patch by mike.dvoretsky
Differential Revision: https://reviews.llvm.org/D47311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333990
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Craig Topper [Tue, 5 Jun 2018 06:20:06 +0000 (06:20 +0000)]
[X86] Make all instructions that operate on MMX types, but were added after the initial MMX support via one of the SSE features flags make them require the MMX feature as well.
Passing -mattr=-mmx needs to disable these instructions since the MMX register class won't have been set up. But we don't want -mattr=-mmx to disable SSE so we have to do it separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333984
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Nirav Dave [Tue, 5 Jun 2018 03:16:28 +0000 (03:16 +0000)]
[RegAllocGreedy] Use simpler map class for EvicteeInfo. NFCI.
RegAlloc keeps a insertion-time ordered map of evictee information,
but we only use membership. Replace MapVector with contextually
equivalent DenseMap which is smaller and faster.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333981
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Vedant Kumar [Tue, 5 Jun 2018 00:56:08 +0000 (00:56 +0000)]
[opt] Introduce -strip-named-metadata
This renames and generalizes -strip-module-flags to erase all named
metadata from a module. This makes it easier to diff IR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333977
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Vedant Kumar [Tue, 5 Jun 2018 00:56:07 +0000 (00:56 +0000)]
[Debugify] Don't insert debug values after terminating deopts
As is the case with musttail calls, the IR does not allow for
instructions inserted after a terminating deopt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333976
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Vedant Kumar [Tue, 5 Jun 2018 00:56:07 +0000 (00:56 +0000)]
Apply clang-format on a file, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333975
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Francis Visoiu Mistrih [Tue, 5 Jun 2018 00:27:28 +0000 (00:27 +0000)]
Use MF instead of Fn for MachineFunction references. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333973
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Francis Visoiu Mistrih [Tue, 5 Jun 2018 00:27:24 +0000 (00:27 +0000)]
[ShrinkWrap] Add optimization remarks to the shrink-wrapping pass
Start by emitting remarks for very basic unsupported cases such as
irreducible CFGs and EHFunclets. The end goal is to be able to cover all
the cases where we give up with an explanation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333972
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Amara Emerson [Tue, 5 Jun 2018 00:17:13 +0000 (00:17 +0000)]
[MIRParser] Add parser support for 'true' and 'false' i1s.
We already output true and false in the printer, but the parser isn't able to
read it.
Differential Revision: https://reviews.llvm.org/D47424
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333970
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Reid Kleckner [Mon, 4 Jun 2018 23:47:29 +0000 (23:47 +0000)]
Fix -Wcovered-switch-default warning and clang-format it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333967
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David Blaikie [Mon, 4 Jun 2018 22:53:38 +0000 (22:53 +0000)]
Move Compiler.h from Demangle back to Support
Code review feedback from r328123 prefers copying the few feature test
macros used by Demangle into there, rather than sinking the header into
an odd corner like Demangle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333965
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Derek Schuff [Mon, 4 Jun 2018 22:53:36 +0000 (22:53 +0000)]
Simplified WebAssemblyAsmBackend by removing explicit ELF variant.
The ELF version was broken (does not deal with wasm specific fixups),
and now is slightly less broken. It will be removed in its entirety
in the future which this change makes slightly easier (just remove
the IsELF bool).
Differential Revision: https://reviews.llvm.org/D47745
Patch by Wouter van Oortmerssen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333964
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Sanjay Patel [Mon, 4 Jun 2018 22:26:45 +0000 (22:26 +0000)]
[InstCombine] refine UB-handling in shuffle-binop transform
As noted in rL333782, we can be both better for optimization and
safer with this transform:
BinOp (shuffle V1, Mask), C --> shuffle (BinOp V1, NewC), Mask
The only potentially unsafe-to-speculate binops are integer div/rem.
All other binops are always safe (although I don't see a way to
assert that in code here).
For opcodes like shifts that can produce poison, it can't matter
here because we know the lanes with undef are dropped by the
subsequent shuffle.
Differential Revision: https://reviews.llvm.org/D47686
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333962
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Amaury Sechet [Mon, 4 Jun 2018 22:09:26 +0000 (22:09 +0000)]
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333961
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Amaury Sechet [Mon, 4 Jun 2018 21:49:23 +0000 (21:49 +0000)]
Revert "Regenerate expected test results for test/CodeGen/X86/pr23103.ll . NFC"
This reverts commit
cf25dfc503c861845947f3e6a9d308811ebb9da3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333960
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Vedant Kumar [Mon, 4 Jun 2018 21:43:28 +0000 (21:43 +0000)]
[Debugify] Preserve analyses in -check-debugify
The -check-debugify pass should preserve all analyses. Otherwise, it may
invalidate an optional analysis and inadvertently alter codegen.
The test case is reduced from deopt-bundle.ll. The result of `opt -O1`
on this file would differ when -debugify-each was toggled. That happened
because CheckDebugify failed to preserve GlobalsAA.
Thanks to Davide Italiano for his help chasing this down!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333959
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David Blaikie [Mon, 4 Jun 2018 21:33:56 +0000 (21:33 +0000)]
Add missing header
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333957
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David Blaikie [Mon, 4 Jun 2018 21:23:21 +0000 (21:23 +0000)]
Move Analysis/Utils/Local.h back to Transforms
Review feedback from r328165. Split out just the one function from the
file that's used by Analysis. (As chandlerc pointed out, the original
change only moved the header and not the implementation anyway - which
was fine for the one function that was used (since it's a
template/inlined in the header) but not in general)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333954
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Amaury Sechet [Mon, 4 Jun 2018 21:20:45 +0000 (21:20 +0000)]
Revert "Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC"
This reverts commit
f0e85c194ae5e87476bc767304470dec85b6774f.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333953
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Jessica Paquette [Mon, 4 Jun 2018 21:14:16 +0000 (21:14 +0000)]
[MachineOutliner] NFC - Move intermediate data structures to MachineOutliner.h
This is setting up to fix bug 37573 cleanly.
This moves data structures that are technically both used in some way by the
target and the general-purpose outlining algorithm into MachineOutliner.h. In
particular, the `Candidate` class is of importance.
Before, the outliner passed the locations of `Candidates` to the target, which
would then make some decisions about the prospective outlined function. This
change allows us to just pass `Candidates` along to the target. This will allow
the target to discard `Candidates` that would be considered unsafe before cost
calculation. Thus, we will be able to remove the unsafe candidates described in
the bug without resorting to torching the entire prospective function.
Also, as a side-effect, it makes the outliner a bit cleaner.
https://bugs.llvm.org/show_bug.cgi?id=37573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333952
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Alexander Ivchenko [Mon, 4 Jun 2018 21:07:35 +0000 (21:07 +0000)]
[X86][ELF][CET] Adding the .note.gnu.property ELF section in X86
In preparation for the proposed linker ABI changes
(https://github.com/hjl-tools/linux-abi/wiki/linux-abi-draft.pdf,
https://github.com/hjl-tools/x86-psABI/wiki/x86-64-psABI-cet.pdf),
this patch enables emission of the .note.gnu.property section to
ELF object files when building CET-enabled modules.
patch by mike.dvoretsky
Differential Revision: https://reviews.llvm.org/D47145
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333951
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Amaury Sechet [Mon, 4 Jun 2018 20:57:27 +0000 (20:57 +0000)]
Remove various use of undef in the X86 test suite as patern involving undef can collapse them. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333950
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Amaury Sechet [Mon, 4 Jun 2018 20:47:00 +0000 (20:47 +0000)]
Regenerate expected test results for test/CodeGen/X86/pr23103.ll . NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333949
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Scott Linder [Mon, 4 Jun 2018 20:19:45 +0000 (20:19 +0000)]
[CodeGen] Always update divergence in SelectionDAG::UpdateNodeOperands
Some overloads failed to update divergence.
Differential Revision: https://reviews.llvm.org/D47148
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333947
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Zachary Turner [Mon, 4 Jun 2018 19:38:11 +0000 (19:38 +0000)]
[Support] Add functions that operate on native file handles on Windows.
Windows' CRT has a limit of 512 open file descriptors, and fds which are
generated by converting a HANDLE via _get_osfhandle count towards this
limit as well.
Regardless, often you find yourself marshalling back and forth between
native HANDLE objects and fds anyway. If we know from the getgo that
we're going to need to work directly with the handle, we can cut out the
marshalling layer while also not contributing to filling up the CRT's
very limited handle table.
On Unix these functions just delegate directly to the existing set of
functions since an fd *is* the native file type. It would be nice, very
long term, if we could convert most uses of fds to file_t.
Differential Revision: https://reviews.llvm.org/D47688
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333945
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Amaury Sechet [Mon, 4 Jun 2018 19:23:22 +0000 (19:23 +0000)]
[DAGcombine] Teach the combiner about -a = ~a + 1
Summary: This include variant for add, uaddo and addcarry. usubo and subcarry require the carry to be flipped to preserve semantic, but we chose to do the transform anyway in that case as to push the transform down the carry chain.
Reviewers: efriedma, spatel, RKSimon, zvi, bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D46505
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333943
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Teresa Johnson [Mon, 4 Jun 2018 19:20:02 +0000 (19:20 +0000)]
Fix for llvm-dis/llvm-bcanalyzer overflows
Summary:
These tools failed for a very large bitcode file produced by LTO due to
64-bit values being assigned to 32-bit types. For the BitstreamReader.h
fix, the value initially fit into the 32-bit unsigned, but there was an
overflow when multiplying by 32 furter below to compute the bit offset.
No test case in the patch as this requires a huge bitcode file.
Reviewers: pcc, george.karpenkov
Subscribers: mehdi_amini, a.sidorin, llvm-commits
Differential Revision: https://reviews.llvm.org/D47731
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333942
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Alexander Shaposhnikov [Mon, 4 Jun 2018 18:55:41 +0000 (18:55 +0000)]
[llvm-strip] Add missing aliases for --strip-debug
Add missing aliases for --strip-debug: -g, -S, -d.
Test plan: make check-all
Differential revision: https://reviews.llvm.org/D47674
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333940
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Amaury Sechet [Mon, 4 Jun 2018 18:36:22 +0000 (18:36 +0000)]
Get rid of SETCCE
Summary: It has been deprecated in favor of SETCCCARRY for a year now and isn't used by any in tree backend.
Reviewers: efriedma, craig.topper, dblaikie, bkramer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47685
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333939
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Dmitry Mikulin [Mon, 4 Jun 2018 18:18:12 +0000 (18:18 +0000)]
In thin and full LTO + CFI, direct function calls may go through jump table
entries to reach the target. Since these calls don't require type checks,
we can short-circuit them to their real targets, except in cases when they
can be pre-empted.
Differential Revision: https://reviews.llvm.org/D46326
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333937
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Craig Topper [Mon, 4 Jun 2018 17:58:45 +0000 (17:58 +0000)]
[X86] Don't pass ParitySrc array into isAddSubOrSubAddMask. Instead use a bool output parameter to get the real piece of info we care about. NFC
The ParitySrc array is more of an implementation detail. A single bool to get the final parity is sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333935
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Stanislav Mekhanoshin [Mon, 4 Jun 2018 17:57:40 +0000 (17:57 +0000)]
[AMDGPU] Small refactoring in the scheduler
After last changes some code can be simplified.
Differential Revision: https://reviews.llvm.org/D47661
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333934
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Stanislav Mekhanoshin [Mon, 4 Jun 2018 17:21:54 +0000 (17:21 +0000)]
[AMDGPU] Factored out common part of GCNRPTracker::reset()
Differential Revision: https://reviews.llvm.org/D47664
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333931
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Sam Clegg [Mon, 4 Jun 2018 17:01:20 +0000 (17:01 +0000)]
[MachO] Add out-of-bounds check to MachOObjectFile.cpp
This is a followup to rL333496.
Differential Revision: https://reviews.llvm.org/D47544
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333929
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Sam Clegg [Mon, 4 Jun 2018 16:59:26 +0000 (16:59 +0000)]
[WebAssembly] Fix .td files after rL333900
Differential Revision: https://reviews.llvm.org/D47727
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333928
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John Brawn [Mon, 4 Jun 2018 16:53:57 +0000 (16:53 +0000)]
[ValueTracking] Match select abs pattern when there's an sext involved
When checking a select to see if it matches an abs, allow the true/false values
to be a sign-extension of the comparison value instead of requiring that they're
directly the comparison value, as all the comparison cares about is the sign of
the value.
This fixes a regression due to r333702, where we were no longer generating ctlz
due to isKnownNonNegative failing to match such a pattern.
Differential Revision: https://reviews.llvm.org/D47631
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333927
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Mark Searles [Mon, 4 Jun 2018 16:51:59 +0000 (16:51 +0000)]
[AMDGPU][Waitcnt] Fix handling of flat instrs
On GFX9 and earlier, flat memory ops may decrement VMCNT out-of-order as well as LGKMCNT out-of-order.
Differential Revision: https://reviews.llvm.org/D46616
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333926
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Simon Pilgrim [Mon, 4 Jun 2018 16:48:13 +0000 (16:48 +0000)]
[X86] Only accept const SelectionDAG to resolveTargetShuffleInputs/getFauxShuffleMask
These methods should only be using SelectionDAG for analysis (known/sign bits etc), not node creation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333925
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Benjamin Kramer [Mon, 4 Jun 2018 16:12:33 +0000 (16:12 +0000)]
[NVPTX] Delete dead code from the AsmPrinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333924
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Andrea Di Biagio [Mon, 4 Jun 2018 15:43:09 +0000 (15:43 +0000)]
[RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca.
This patch is the last of a sequence of three patches related to LLVM-dev RFC
"MC support for variant scheduling classes".
http://lists.llvm.org/pipermail/llvm-dev/2018-May/123181.html
This fixes PR36672.
The main goal of this patch is to teach llvm-mca how to solve variant scheduling
classes. This patch does that, plus it adds new variant scheduling classes to
the BtVer2 scheduling model to identify so-called zero-idioms (i.e. so-called
dependency breaking instructions that are known to generate zero, and that are
optimized out in hardware at register renaming stage).
Without the BtVer2 change, this patch would not have had any meaningful tests.
This patch is effectively the union of two changes:
1) a change that teaches llvm-mca how to resolve variant scheduling classes.
2) a change to the BtVer2 scheduling model that allows us to special-case
packed XOR zero-idioms (this partially fixes PR36671).
Differential Revision: https://reviews.llvm.org/D47374
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333909
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Alexander Ivchenko [Mon, 4 Jun 2018 15:14:18 +0000 (15:14 +0000)]
[llvm-readobj] Support GNU_PROPERTY_X86_FEATURE_1_AND notes in .note.gnu.property
Resubmit of r333424. This version contains the fix for fails found by buildbots
on some targets.
This patch allows parsing GNU_PROPERTY_X86_FEATURE_1_AND
notes in .note.gnu.property sections. These notes
indicate that the object file is built to support Intel CET.
patch by mike.dvoretsky
Differential Revision: https://reviews.llvm.org/D47473
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333908
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Krzysztof Parzyszek [Mon, 4 Jun 2018 14:54:53 +0000 (14:54 +0000)]
[SelectionDAG] Add missing closing parentheses in comments, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333907
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Nicolai Haehnle [Mon, 4 Jun 2018 14:45:20 +0000 (14:45 +0000)]
AMDGPU: Make various NamedOperands upper case
Summary:
Avoid name clashes with the corresponding bit fields in the instruction
encoding.
Change-Id: Id1644e703e976e78f7af93788d9f44cb48c3251f
Reviewers: arsenm, rampitec, kzhuravl
Subscribers: wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D47433
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333905
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Nicolai Haehnle [Mon, 4 Jun 2018 14:45:12 +0000 (14:45 +0000)]
TableGen/DAGPatterns: Allow bit constants in addition to int constants
Summary:
Implicit casting is a simple quality of life improvement.
Change-Id: I3d2b31b8b8f12cbb1e84f691e359fa713a9c4b42
Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D47432
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333904
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Nicola Zaghen [Mon, 4 Jun 2018 14:40:34 +0000 (14:40 +0000)]
[ReleaseNotes] Formatting fixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333902
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Nicolai Haehnle [Mon, 4 Jun 2018 14:26:12 +0000 (14:26 +0000)]
TableGen: some LangRef doc fixes
Summary: Change-Id: I1442e2daa09cab727a01d8c31893b50e644a5cd3
Reviewers: tra, simon_tatham, craig.topper
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47530
Change-Id: I397655dd18b7ff978c1affa3174740d9c1a82594
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333901
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Nicolai Haehnle [Mon, 4 Jun 2018 14:26:05 +0000 (14:26 +0000)]
TableGen: Streamline the semantics of NAME
Summary:
The new rules are straightforward. The main rules to keep in mind
are:
1. NAME is an implicit template argument of class and multiclass,
and will be substituted by the name of the instantiating def/defm.
2. The name of a def/defm in a multiclass must contain a reference
to NAME. If such a reference is not present, it is automatically
prepended.
And for some additional subtleties, consider these:
3. defm with no name generates a unique name but has no special
behavior otherwise.
4. def with no name generates an anonymous record, whose name is
unique but undefined. In particular, the name won't contain a
reference to NAME.
Keeping rules 1&2 in mind should allow a predictable behavior of
name resolution that is simple to follow.
The old "rules" were rather surprising: sometimes (but not always),
NAME would correspond to the name of the toplevel defm. They were
also plain bonkers when you pushed them to their limits, as the old
version of the TableGen test case shows.
Having NAME correspond to the name of the toplevel defm introduces
"spooky action at a distance" and breaks composability:
refactoring the upper layers of a hierarchy of nested multiclass
instantiations can cause unexpected breakage by changing the value
of NAME at a lower level of the hierarchy. The new rules don't
suffer from this problem.
Some existing .td files have to be adjusted because they ended up
depending on the details of the old implementation.
Change-Id: I694095231565b30f563e6fd0417b41ee01a12589
Reviewers: tra, simon_tatham, craig.topper, MartinO, arsenm, javed.absar
Subscribers: wdng, llvm-commits
Differential Revision: https://reviews.llvm.org/D47430
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333900
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Nicola Zaghen [Mon, 4 Jun 2018 13:55:09 +0000 (13:55 +0000)]
[ReleaseNotes] Add release note for the new LLVM_DEBUG macro.
This is to provide a way to migrate from the old DEBUG macro to the new one.
Differential Revision: https://reviews.llvm.org/D47528
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333898
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Simon Dardis [Mon, 4 Jun 2018 12:50:32 +0000 (12:50 +0000)]
[mips] Restore the availablity of trap for microMIPS
Reviewers: smaksimovic, atanasyan, abeserminji
Differential Revision: https://reviews.llvm.org/D47584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333895
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Greg Bedwell [Mon, 4 Jun 2018 12:30:10 +0000 (12:30 +0000)]
[llvm-mca][UpdateTestChecks] Prevent an IndexError being raised when given empty input
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333894
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Greg Bedwell [Mon, 4 Jun 2018 12:30:03 +0000 (12:30 +0000)]
[llvm-mca] Regenerate a test to remove a double newline
Command used: py update_mca_test_checks.py ..\test\tools\llvm-mca\*\*.s ..\test\tools\llvm-mca\*\*\*.s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333893
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Andrea Di Biagio [Mon, 4 Jun 2018 12:23:07 +0000 (12:23 +0000)]
[llvm-mca] Track cycles contributed by resources that are in a 'Super' relationship.
This is required if we want to correctly match the behavior of method
SubtargetEmitter::ExpandProcResource() in Tablegen. When computing the set of
"consumed" processor resources and resource cycles, the logic in
ExpandProcResource() doesn't update the number of resource cycles contributed by
a "Super" resource to a group. We need to take this into account when a model
declares a processor resource which is part of a 'processor resource group', and
it is also used as the "Super" of other resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333892
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Roman Lebedev [Mon, 4 Jun 2018 11:48:46 +0000 (11:48 +0000)]
[llvm-mca] Make sure not to end the test files with an empty line.
Summary:
It's super irritating.
[properly configured] git client then complains about that double-newline,
and you have to use `--force` to ignore the warning, since even if you
fix it manually, it will be reintroduced the very next runtime :/
Reviewers: RKSimon, andreadb, courbet, craig.topper, javed.absar, gbedwell
Reviewed By: gbedwell
Subscribers: javed.absar, tschuett, gbedwell, llvm-commits
Differential Revision: https://reviews.llvm.org/D47697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333887
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Clement Courbet [Mon, 4 Jun 2018 11:43:40 +0000 (11:43 +0000)]
[llvm-exegesis][NFC] Use an enum instead of a string for benchmark mode.
Summary: YAML encoding is backwards-compatible.
Reviewers: gchatelet
Subscribers: tschuett, llvm-commits
Differential Revision: https://reviews.llvm.org/D47705
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333886
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Clement Courbet [Mon, 4 Jun 2018 11:11:55 +0000 (11:11 +0000)]
[llvm-exegesis] Analysis: Show inconsistencies between checked-in and measured data.
Summary:
We now highlight any sched classes whose measurements do not match the
LLVM SchedModel. "bad" clusters are marked in red.
Screenshot in phabricator diff.
Reviewers: gchatelet
Subscribers: tschuett, mgrang, RKSimon, llvm-commits
Differential Revision: https://reviews.llvm.org/D47639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333884
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Luke Geeson [Mon, 4 Jun 2018 09:41:32 +0000 (09:41 +0000)]
[AArch64] Audit on rL333634 to fix FP16 Disasm BitPatterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333879
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Sander de Smalen [Mon, 4 Jun 2018 07:24:23 +0000 (07:24 +0000)]
[AArch64][SVE] Fix range for DUP immediates (16bit elts)
For immediates used in DUP instructions that have the range
-128 to 127, or a multiple of 256 in the range -32768 to 32512,
one could argue that when the result element size is 16bits (.h),
the value can be considered both signed and unsigned.
Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47619
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333873
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Sander de Smalen [Mon, 4 Jun 2018 07:07:35 +0000 (07:07 +0000)]
[AArch64][SVE] Asm: Print indexed element 0 as FPR.
Print the first indexed element as a FP register, for example:
mov z0.d, z1.d[0]
Is now printed as:
mov z0.d, d1
Next to printing, this patch also adds aliases to parse 'mov z0.d, d1'.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333872
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Sander de Smalen [Mon, 4 Jun 2018 06:40:55 +0000 (06:40 +0000)]
[AArch64][SVE] Asm: Support for indexed DUP instructions.
Unpredicated copy of indexed SVE element to SVE vector,
along with MOV-aliases.
For example:
dup z0.h, z1.h[0]
duplicates the first 16-bit element from z1 to all elements in
the result vector z0.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47570
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333871
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Sander de Smalen [Mon, 4 Jun 2018 05:58:06 +0000 (05:58 +0000)]
[AArch64][SVE] Asm: Support for FCPY immediate instructions.
Predicated copy of floating-point immediate value to SVE vector,
along with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: javed.absar
Differential Revision: https://reviews.llvm.org/D47518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333869
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Sander de Smalen [Mon, 4 Jun 2018 05:40:46 +0000 (05:40 +0000)]
[AArch64][SVE] Asm: Support for CPY immediate instructions
Predicated copy of possibly shifted immediate value into SVE
vector, along with MOV-aliases.
Reviewers: rengolin, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D47517
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333868
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Vedant Kumar [Mon, 4 Jun 2018 03:33:01 +0000 (03:33 +0000)]
[Debugify] Add debug intrinsics before terminating musttail calls
After r333856, opt -debugify would just stop emitting debug value
intrinsics after encountering a musttail call. This wasn't sufficient to
avoid verifier failures.
Debug value intrinicss for all instructions preceding a musttail call
must also be emitted before the musttail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333866
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Serguei Katkov [Mon, 4 Jun 2018 02:52:36 +0000 (02:52 +0000)]
[InstCombine] Fix div handling
When we optimize select basing on fact that div by 0 is undef
we should not traverse the instruction which are not guaranteed to
transfer execution to next instruction. Guard intrinsic is an example.
Reviewers: spatel, craig.topper
Reviewed By: spatel
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333864
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Vedant Kumar [Mon, 4 Jun 2018 00:11:49 +0000 (00:11 +0000)]
[Debugify] Don't apply DI before the bitcode writer pass
Applying synthetic debug info before the bitcode writer pass has no
testing-related purpose. This commit prevents that from happening.
It also adds tests which check that IR produced with/without
-debugify-each enabled is identical after stripping. This makes it
possible to check that individual passes (or full pipelines) are
invariant to debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333861
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Vedant Kumar [Mon, 4 Jun 2018 00:11:48 +0000 (00:11 +0000)]
[opt] Add a -strip-module-flags option
The -strip-module-flags option strips llvm.module.flags metadata from a
module at the beginning of the opt pipeline.
This will be used to test whether the output of a pass is debug info
(DI) invariant.
E.g, after applying synthetic debug info to a test case, we'd like to
strip out all DI-related metadata and check that the final IR is
identical to a baseline file without any DI applied, to check that
optimizations aren't inhibited by debug info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333860
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Vedant Kumar [Mon, 4 Jun 2018 00:11:47 +0000 (00:11 +0000)]
Reformat overflowing lines, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333859
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Craig Topper [Sun, 3 Jun 2018 23:24:17 +0000 (23:24 +0000)]
[X86] Remove and autoupgrade masked avx512vnni intrinsics using the unmasked intrinsics and select instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333857
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Vedant Kumar [Sun, 3 Jun 2018 22:50:22 +0000 (22:50 +0000)]
[Debugify] Skip dbg.value placement for EH pads, musttail
Placing meta-instructions into EH pads breaks certain IR invariants, as
does placing instructions after a musttail call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333856
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Chris Bieneman [Sun, 3 Jun 2018 20:33:42 +0000 (20:33 +0000)]
Re-land: [MachO] Fixing ub in MachO BinaryFormat
This re-lands r333797 with a fix for big endian systems.
Original commit message:
This isn't encountered anywhere inside LLVM, so I wrote a test case to expose the issue and verify that it is fixed.
The basic problem is that the macho_load_command union contains all load comamnd structs. Load command structs in 32-bit macho files can be 32-bit aligned instead of 64-bit aligned.
There are some strange circumstances in which this can be exposed in a 64-bit macho if the load commands are invalid or if a 32-bit aligned load command is used. In the past we've worked around this type of problem with changes like r264232.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333854
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Lang Hames [Sun, 3 Jun 2018 19:22:48 +0000 (19:22 +0000)]
[ORC] Add a constructor to create an IRMaterializationUnit from a module and
pre-existing SymbolFlags and SymbolToDefinition maps.
This constructor is useful when delegating work from an existing
IRMaterialiaztionUnit to a new one, as it avoids the cost of re-computing these
maps.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333852
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Simon Pilgrim [Sun, 3 Jun 2018 18:15:06 +0000 (18:15 +0000)]
[X86][TBM] Use realistic BEXTR control bits
Avoid constant values that are guaranteed to give zero
Found while investigating BEXTR optimizations for PR34042.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333849
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Sanjay Patel [Sun, 3 Jun 2018 16:35:26 +0000 (16:35 +0000)]
[InstCombine] improve sub with bool folds
There's a patchwork of existing transforms trying to handle
these cases, but as seen in the changed test, we weren't
catching them all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333845
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Simon Pilgrim [Sun, 3 Jun 2018 14:56:04 +0000 (14:56 +0000)]
[X86][AVX512] Cleanup intrinsics tests
Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage.
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333843
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Simon Pilgrim [Sun, 3 Jun 2018 14:31:30 +0000 (14:31 +0000)]
[X86][AVX512BW] Regenerate arithmetic tests using update_llc_test_checks.py script
Require manual stripping of existing CHECKs as update_llc_test_checks doesn't remove them if they're outside the function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333842
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Simon Pilgrim [Sun, 3 Jun 2018 14:11:34 +0000 (14:11 +0000)]
[X86][BMI1] Test i32 intrinsics on 32/64 bits + branch off i64 tests
Further refactoring will wait until D47452 has landed.
Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333841
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Simon Pilgrim [Sun, 3 Jun 2018 13:55:17 +0000 (13:55 +0000)]
[X86][BMI] Remove CTTZ tests - this is fully covered in clz.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333840
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